diff options
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wb.v | 20 | ||||
| -rw-r--r-- | usrp2/timing/time_64bit.v | 4 |
2 files changed, 13 insertions, 11 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v index bcf18f9a8..0ddb8398a 100644 --- a/usrp2/simple_gemac/simple_gemac_wb.v +++ b/usrp2/simple_gemac/simple_gemac_wb.v @@ -161,19 +161,19 @@ module simple_gemac_wb always @(posedge wb_clk) case(wb_adr[7:2]) - 0 : wb_dat_o <= misc_settings; - 1 : wb_dat_o <= ucast_addr[47:32]; - 2 : wb_dat_o <= ucast_addr[31:0]; - 3 : wb_dat_o <= mcast_addr[47:32]; - 4 : wb_dat_o <= mcast_addr[31:0]; - 5 : wb_dat_o <= {NoPre,Divider}; - 6 : wb_dat_o <= MIIADDRESS; - 7 : wb_dat_o <= CtrlData; + //0 : wb_dat_o <= misc_settings; + //1 : wb_dat_o <= ucast_addr[47:32]; + //2 : wb_dat_o <= ucast_addr[31:0]; + //3 : wb_dat_o <= mcast_addr[47:32]; + //4 : wb_dat_o <= mcast_addr[31:0]; + //5 : wb_dat_o <= {NoPre,Divider}; + //6 : wb_dat_o <= MIIADDRESS; + //7 : wb_dat_o <= CtrlData; 8 : wb_dat_o <= MIICOMMAND; 9 : wb_dat_o <= MIISTATUS; 10: wb_dat_o <= MIIRX_DATA; - 11: wb_dat_o <= pause_time; - 12: wb_dat_o <= pause_thresh; + //11: wb_dat_o <= pause_time; + //12: wb_dat_o <= pause_thresh; endcase // case (wb_adr[7:2]) endmodule // simple_gemac_wb diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 8c9090a35..4fefcc488 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -161,7 +161,9 @@ module time_64bit assign mimo_secs = vita_time_rcvd[63:32]; assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay}; - assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); + //assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); + // for timing purposes, assume sync_delay less than 10k + assign mimo_sync_now = mimo_sync & sync_rcvd & (vita_time_rcvd <= (TICKS_PER_SEC-10000)); assign debug = { { 24'b0} , { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} }; |