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-rw-r--r--host/lib/usrp/common/ad9361_ctrl.cpp40
-rw-r--r--host/lib/usrp/common/ad9361_ctrl.hpp3
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_client.h13
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.cpp170
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_device.h25
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h10
-rw-r--r--host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h8
7 files changed, 133 insertions, 136 deletions
diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp
index 0754d2c86..bf0bb75d2 100644
--- a/host/lib/usrp/common/ad9361_ctrl.cpp
+++ b/host/lib/usrp/common/ad9361_ctrl.cpp
@@ -24,35 +24,35 @@ using namespace uhd::usrp;
class ad9361_io_spi : public ad9361_io
{
public:
- ad9361_io_spi(uhd::spi_iface::sptr spi_iface, uint32_t slave_num) :
+ ad9361_io_spi(uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num) :
_spi_iface(spi_iface), _slave_num(slave_num) { }
virtual ~ad9361_io_spi() { }
- virtual uint8_t peek8(uint32_t reg)
+ virtual boost::uint8_t peek8(boost::uint32_t reg)
{
uhd::spi_config_t config;
config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
- uint32_t rd_word = AD9361_SPI_READ_CMD |
- ((uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK);
+ boost::uint32_t rd_word = AD9361_SPI_READ_CMD |
+ ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK);
- uint32_t val = (_spi_iface->read_spi(_slave_num, config, rd_word, AD9361_SPI_NUM_BITS));
+ boost::uint32_t val = (_spi_iface->read_spi(_slave_num, config, rd_word, AD9361_SPI_NUM_BITS));
val &= 0xFF;
- return static_cast<uint8_t>(val);
+ return static_cast<boost::uint8_t>(val);
}
- virtual void poke8(uint32_t reg, uint8_t val)
+ virtual void poke8(boost::uint32_t reg, boost::uint8_t val)
{
uhd::spi_config_t config;
config.mosi_edge = uhd::spi_config_t::EDGE_FALL;
config.miso_edge = uhd::spi_config_t::EDGE_FALL; //TODO (Ashish): FPGA SPI workaround. This should be EDGE_RISE
- uint32_t wr_word = AD9361_SPI_WRITE_CMD |
- ((uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK) |
- ((uint32_t(val) << AD9361_SPI_DATA_SHIFT) & AD9361_SPI_DATA_MASK);
+ boost::uint32_t wr_word = AD9361_SPI_WRITE_CMD |
+ ((boost::uint32_t(reg) << AD9361_SPI_ADDR_SHIFT) & AD9361_SPI_ADDR_MASK) |
+ ((boost::uint32_t(val) << AD9361_SPI_DATA_SHIFT) & AD9361_SPI_DATA_MASK);
_spi_iface->write_spi(_slave_num, config, wr_word, AD9361_SPI_NUM_BITS);
//TODO (Ashish): Is this necessary? The FX3 firmware does it right now but for
@@ -62,15 +62,15 @@ public:
private:
uhd::spi_iface::sptr _spi_iface;
- uint32_t _slave_num;
-
- static const uint32_t AD9361_SPI_WRITE_CMD = 0x00800000;
- static const uint32_t AD9361_SPI_READ_CMD = 0x00000000;
- static const uint32_t AD9361_SPI_ADDR_MASK = 0x003FFF00;
- static const uint32_t AD9361_SPI_ADDR_SHIFT = 8;
- static const uint32_t AD9361_SPI_DATA_MASK = 0x000000FF;
- static const uint32_t AD9361_SPI_DATA_SHIFT = 0;
- static const uint32_t AD9361_SPI_NUM_BITS = 24;
+ boost::uint32_t _slave_num;
+
+ static const boost::uint32_t AD9361_SPI_WRITE_CMD = 0x00800000;
+ static const boost::uint32_t AD9361_SPI_READ_CMD = 0x00000000;
+ static const boost::uint32_t AD9361_SPI_ADDR_MASK = 0x003FFF00;
+ static const boost::uint32_t AD9361_SPI_ADDR_SHIFT = 8;
+ static const boost::uint32_t AD9361_SPI_DATA_MASK = 0x000000FF;
+ static const boost::uint32_t AD9361_SPI_DATA_SHIFT = 0;
+ static const boost::uint32_t AD9361_SPI_NUM_BITS = 24;
};
/***********************************************************************
@@ -177,7 +177,7 @@ private:
// Make an instance of the AD9361 Control interface
//----------------------------------------------------------------------
ad9361_ctrl::sptr ad9361_ctrl::make_spi(
- ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, uint32_t slave_num)
+ ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num)
{
boost::shared_ptr<ad9361_io_spi> spi_io_iface = boost::make_shared<ad9361_io_spi>(spi_iface, slave_num);
return sptr(new ad9361_ctrl_impl(client_settings, spi_io_iface));
diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp
index 3b8738c51..ed778cadb 100644
--- a/host/lib/usrp/common/ad9361_ctrl.hpp
+++ b/host/lib/usrp/common/ad9361_ctrl.hpp
@@ -11,7 +11,6 @@
#include <boost/shared_ptr.hpp>
#include <ad9361_device.h>
#include <string>
-#include <stdint.h>
static const double AD9361_CLOCK_RATE_MAX = 61.44e6;
static const double AD9361_1_CHAN_CLOCK_RATE_MAX = AD9361_CLOCK_RATE_MAX;
@@ -29,7 +28,7 @@ public:
//! make a new codec control object
static sptr make_spi(
- ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, uint32_t slave_num);
+ ad9361_params::sptr client_settings, uhd::spi_iface::sptr spi_iface, boost::uint32_t slave_num);
//! Get a list of gain names for RX or TX
static std::vector<std::string> get_gain_names(const std::string &/*which*/)
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_client.h b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
index fa501b615..5e848d4c0 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_client.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
@@ -5,7 +5,6 @@
#ifndef INCLUDED_AD9361_CLIENT_H
#define INCLUDED_AD9361_CLIENT_H
-#include <stdint.h>
#include <boost/shared_ptr.hpp>
namespace uhd { namespace usrp {
@@ -39,10 +38,10 @@ typedef enum {
* Interface timing
*/
typedef struct {
- uint8_t rx_clk_delay;
- uint8_t rx_data_delay;
- uint8_t tx_clk_delay;
- uint8_t tx_data_delay;
+ boost::uint8_t rx_clk_delay;
+ boost::uint8_t rx_data_delay;
+ boost::uint8_t tx_clk_delay;
+ boost::uint8_t tx_data_delay;
} digital_interface_delays_t;
class ad9361_params {
@@ -64,8 +63,8 @@ public:
virtual ~ad9361_io() {}
- virtual uint8_t peek8(uint32_t reg) = 0;
- virtual void poke8(uint32_t reg, uint8_t val) = 0;
+ virtual boost::uint8_t peek8(boost::uint32_t reg) = 0;
+ virtual void poke8(boost::uint32_t reg, boost::uint8_t val) = 0;
};
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index 1e1e51412..95df62e9a 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -2,17 +2,13 @@
// Copyright 2014 Ettus Research LLC
//
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <cstring>
-#include <cmath>
-#include <iostream>
#include "ad9361_filter_taps.h"
#include "ad9361_gain_tables.h"
#include "ad9361_synth_lut.h"
-#include "ad9361_client.h" //Client (product) specific settings
+#include "ad9361_client.h"
#include "ad9361_device.h"
+#include <cstring>
+#include <cmath>
#include <boost/date_time/posix_time/posix_time.hpp>
#include <boost/thread/thread.hpp>
#include <boost/scoped_array.hpp>
@@ -116,9 +112,9 @@ int get_num_taps(int max_num_taps) {
* how many taps are in the filter, and given a vector of the taps
* themselves. */
-void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, uint16_t *coeffs)
+void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs)
{
- uint16_t base;
+ boost::uint16_t base;
/* RX and TX filters use largely identical sets of programming registers.
Select the appropriate bank of registers here. */
@@ -129,7 +125,7 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, int num_taps, u
}
/* Encode number of filter taps for programming register */
- uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5;
+ boost::uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5;
/* Turn on the filter clock. */
_io_iface->poke8(base + 5, reg_numtaps | 0x1a);
@@ -179,16 +175,16 @@ void ad9361_device_t::_setup_rx_fir(size_t num_taps)
for (size_t i = 0; i < num_taps; i++) {
switch (num_taps) {
case 128:
- coeffs[i] = (uint16_t) hb127_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb127_coeffs[i]);
break;
case 96:
- coeffs[i] = (uint16_t) hb95_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb95_coeffs[i]);
break;
case 64:
- coeffs[i] = (uint16_t) hb63_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb63_coeffs[i]);
break;
case 48:
- coeffs[i] = (uint16_t) hb47_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb47_coeffs[i]);
break;
default:
post_err_msg("Unsupported number of Rx FIR taps.");
@@ -205,16 +201,16 @@ void ad9361_device_t::_setup_tx_fir(size_t num_taps)
for (size_t i = 0; i < num_taps; i++) {
switch (num_taps) {
case 128:
- coeffs[i] = (uint16_t) hb127_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb127_coeffs[i]);
break;
case 96:
- coeffs[i] = (uint16_t) hb95_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb95_coeffs[i]);
break;
case 64:
- coeffs[i] = (uint16_t) hb63_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb63_coeffs[i]);
break;
case 48:
- coeffs[i] = (uint16_t) hb47_coeffs[i];
+ coeffs[i] = boost::uint16_t(hb47_coeffs[i]);
break;
default:
post_err_msg("Unsupported number of Tx FIR taps.");
@@ -315,10 +311,10 @@ double ad9361_device_t::_calibrate_baseband_rx_analog_filter()
double bbbw_mhz = bbbw / 1e6;
double temp = ((bbbw_mhz - floor_to_int(bbbw_mhz)) * 1000) / 7.8125;
- uint8_t bbbw_khz = (uint8_t) AD9361_MIN(127, (floor_to_int(temp + 0.5)));
+ boost::uint8_t bbbw_khz = (boost::uint8_t) AD9361_MIN(127, (floor_to_int(temp + 0.5)));
/* Set corner frequencies and dividers. */
- _io_iface->poke8(0x1fb, (uint8_t) (bbbw_mhz));
+ _io_iface->poke8(0x1fb, (boost::uint8_t) (bbbw_mhz));
_io_iface->poke8(0x1fc, bbbw_khz);
_io_iface->poke8(0x1f8, (_rx_bbf_tunediv & 0x00FF));
_io_iface->poke8(0x1f9, _regs.bbftune_config);
@@ -367,7 +363,7 @@ double ad9361_device_t::_calibrate_baseband_tx_analog_filter()
}
double txtune_clk = ((1.6 * bbbw * 2 * DOUBLE_PI) / DOUBLE_LN_2);
- uint16_t txbbfdiv = AD9361_MIN(511, (ceil_to_int(_bbpll_freq / txtune_clk)));
+ boost::uint16_t txbbfdiv = AD9361_MIN(511, (ceil_to_int(_bbpll_freq / txtune_clk)));
_regs.bbftune_mode = (_regs.bbftune_mode & 0xFE)
| ((txbbfdiv >> 8) & 0x0001);
@@ -437,7 +433,7 @@ void ad9361_device_t::_calibrate_secondary_tx_filter()
cap = 63;
}
- uint8_t reg0d0, reg0d1, reg0d2;
+ boost::uint8_t reg0d0, reg0d1, reg0d2;
/* Translate baseband bandwidths to register settings. */
if ((bbbw_mhz * 2) <= 9) {
@@ -478,14 +474,14 @@ void ad9361_device_t::_calibrate_secondary_tx_filter()
* the RX gain settings. */
void ad9361_device_t::_calibrate_rx_TIAs()
{
- uint8_t reg1eb = _io_iface->peek8(0x1eb) & 0x3F;
- uint8_t reg1ec = _io_iface->peek8(0x1ec) & 0x7F;
- uint8_t reg1e6 = _io_iface->peek8(0x1e6) & 0x07;
- uint8_t reg1db = 0x00;
- uint8_t reg1dc = 0x00;
- uint8_t reg1dd = 0x00;
- uint8_t reg1de = 0x00;
- uint8_t reg1df = 0x00;
+ boost::uint8_t reg1eb = _io_iface->peek8(0x1eb) & 0x3F;
+ boost::uint8_t reg1ec = _io_iface->peek8(0x1ec) & 0x7F;
+ boost::uint8_t reg1e6 = _io_iface->peek8(0x1e6) & 0x07;
+ boost::uint8_t reg1db = 0x00;
+ boost::uint8_t reg1dc = 0x00;
+ boost::uint8_t reg1dd = 0x00;
+ boost::uint8_t reg1de = 0x00;
+ boost::uint8_t reg1df = 0x00;
/* For calibration, baseband BW is half the complex BW, and must be
* between 28e6 and 0.2e6. */
@@ -516,12 +512,12 @@ void ad9361_device_t::_calibrate_rx_TIAs()
if (CTIA_fF > 2920) {
reg1dc = 0x40;
reg1de = 0x40;
- uint8_t temp = (uint8_t) AD9361_MIN(127,
+ boost::uint8_t temp = (boost::uint8_t) AD9361_MIN(127,
(floor_to_int(0.5 + ((CTIA_fF - 400.0) / 320.0))));
reg1dd = temp;
reg1df = temp;
} else {
- uint8_t temp = (uint8_t) floor_to_int(0.5 + ((CTIA_fF - 400.0) / 40.0))
+ boost::uint8_t temp = (boost::uint8_t) floor_to_int(0.5 + ((CTIA_fF - 400.0) / 40.0))
+ 0x40;
reg1dc = temp;
reg1de = temp;
@@ -556,9 +552,9 @@ void ad9361_device_t::_setup_adc()
bbbw_mhz = 0.20;
}
- uint8_t rxbbf_c3_msb = _io_iface->peek8(0x1eb) & 0x3F;
- uint8_t rxbbf_c3_lsb = _io_iface->peek8(0x1ec) & 0x7F;
- uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07;
+ boost::uint8_t rxbbf_c3_msb = _io_iface->peek8(0x1eb) & 0x3F;
+ boost::uint8_t rxbbf_c3_lsb = _io_iface->peek8(0x1ec) & 0x7F;
+ boost::uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07;
double fsadc = _adcclock_freq / 1e6;
@@ -587,71 +583,71 @@ void ad9361_device_t::_setup_adc()
/* Calculate the values for all 40 settings registers.
*
* DO NOT TOUCH THIS UNLESS YOU KNOW EXACTLY WHAT YOU ARE DOING. kthx.*/
- uint8_t data[40];
+ boost::uint8_t data[40];
data[0] = 0; data[1] = 0; data[2] = 0; data[3] = 0x24;
data[4] = 0x24; data[5] = 0; data[6] = 0;
- data[7] = (uint8_t) AD9361_MIN(124, (floor_to_int(-0.5
+ data[7] = (boost::uint8_t) AD9361_MIN(124, (floor_to_int(-0.5
+ (80.0 * scale_snr * scale_res
* AD9361_MIN(1.0, sqrt(maxsnr * fsadc / 640.0))))));
double data007 = data[7];
- data[8] = (uint8_t) AD9361_MIN(255, (floor_to_int(0.5
+ data[8] = (boost::uint8_t) AD9361_MIN(255, (floor_to_int(0.5
+ ((20.0 * (640.0 / fsadc) * ((data007 / 80.0))
/ (scale_res * scale_cap))))));
- data[10] = (uint8_t) AD9361_MIN(127, (floor_to_int(-0.5 + (77.0 * scale_res
+ data[10] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int(-0.5 + (77.0 * scale_res
* AD9361_MIN(1.0, sqrt(maxsnr * fsadc / 640.0))))));
double data010 = data[10];
- data[9] = (uint8_t) AD9361_MIN(127, (floor_to_int(0.8 * data010)));
- data[11] = (uint8_t) AD9361_MIN(255, (floor_to_int(0.5
+ data[9] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int(0.8 * data010)));
+ data[11] = (boost::uint8_t) AD9361_MIN(255, (floor_to_int(0.5
+ (20.0 * (640.0 / fsadc) * ((data010 / 77.0)
/ (scale_res * scale_cap))))));
- data[12] = (uint8_t) AD9361_MIN(127, (floor_to_int(-0.5
+ data[12] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int(-0.5
+ (80.0 * scale_res * AD9361_MIN(1.0,
sqrt(maxsnr * fsadc / 640.0))))));
double data012 = data[12];
- data[13] = (uint8_t) AD9361_MIN(255, (floor_to_int(-1.5
+ data[13] = (boost::uint8_t) AD9361_MIN(255, (floor_to_int(-1.5
+ (20.0 * (640.0 / fsadc) * ((data012 / 80.0)
/ (scale_res * scale_cap))))));
- data[14] = 21 * (uint8_t)(floor_to_int(0.1 * 640.0 / fsadc));
- data[15] = (uint8_t) AD9361_MIN(127, (1.025 * data007));
+ data[14] = 21 * (boost::uint8_t)(floor_to_int(0.1 * 640.0 / fsadc));
+ data[15] = (boost::uint8_t) AD9361_MIN(127, (1.025 * data007));
double data015 = data[15];
- data[16] = (uint8_t) AD9361_MIN(127, (floor_to_int((data015
+ data[16] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int((data015
* (0.98 + (0.02 * AD9361_MAX(1.0,
(640.0 / fsadc) / maxsnr)))))));
data[17] = data[15];
- data[18] = (uint8_t) AD9361_MIN(127, (0.975 * (data010)));
+ data[18] = (boost::uint8_t) AD9361_MIN(127, (0.975 * (data010)));
double data018 = data[18];
- data[19] = (uint8_t) AD9361_MIN(127, (floor_to_int((data018
+ data[19] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int((data018
* (0.98 + (0.02 * AD9361_MAX(1.0,
(640.0 / fsadc) / maxsnr)))))));
data[20] = data[18];
- data[21] = (uint8_t) AD9361_MIN(127, (0.975 * data012));
+ data[21] = (boost::uint8_t) AD9361_MIN(127, (0.975 * data012));
double data021 = data[21];
- data[22] = (uint8_t) AD9361_MIN(127, (floor_to_int((data021
+ data[22] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int((data021
* (0.98 + (0.02 * AD9361_MAX(1.0,
(640.0 / fsadc) / maxsnr)))))));
data[23] = data[21];
data[24] = 0x2e;
- data[25] = (uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
+ data[25] = (boost::uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
63.0 * (fsadc / 640.0))));
- data[26] = (uint8_t)(floor_to_int(AD9361_MIN(63.0, 63.0 * (fsadc / 640.0)
+ data[26] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0, 63.0 * (fsadc / 640.0)
* (0.92 + (0.08 * (640.0 / fsadc))))));
- data[27] = (uint8_t)(floor_to_int(AD9361_MIN(63.0,
+ data[27] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0,
32.0 * sqrt(fsadc / 640.0))));
- data[28] = (uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
+ data[28] = (boost::uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
63.0 * (fsadc / 640.0))));
- data[29] = (uint8_t)(floor_to_int(AD9361_MIN(63.0,
+ data[29] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0,
63.0 * (fsadc / 640.0)
* (0.92 + (0.08 * (640.0 / fsadc))))));
- data[30] = (uint8_t)(floor_to_int(AD9361_MIN(63.0,
+ data[30] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0,
32.0 * sqrt(fsadc / 640.0))));
- data[31] = (uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
+ data[31] = (boost::uint8_t)(floor_to_int(128.0 + AD9361_MIN(63.0,
63.0 * (fsadc / 640.0))));
- data[32] = (uint8_t)(floor_to_int(AD9361_MIN(63.0,
+ data[32] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0,
63.0 * (fsadc / 640.0) * (0.92
+ (0.08 * (640.0 / fsadc))))));
- data[33] = (uint8_t)(floor_to_int(AD9361_MIN(63.0,
+ data[33] = (boost::uint8_t)(floor_to_int(AD9361_MIN(63.0,
63.0 * sqrt(fsadc / 640.0))));
- data[34] = (uint8_t) AD9361_MIN(127, (floor_to_int(64.0
+ data[34] = (boost::uint8_t) AD9361_MIN(127, (floor_to_int(64.0
* sqrt(fsadc / 640.0))));
data[35] = 0x40;
data[36] = 0x40;
@@ -751,8 +747,8 @@ void ad9361_device_t::_tx_quadrature_cal_routine() {
* 3) Re-read 0A3 to get bits [5:0] because maybe they changed?
* 4) Update only the TX NCO freq bits in 0A3.
* 5) Profit (I hope). */
- uint8_t reg0a3 = _io_iface->peek8(0x0a3);
- uint8_t nco_freq = (reg0a3 & 0xC0);
+ boost::uint8_t reg0a3 = _io_iface->peek8(0x0a3);
+ boost::uint8_t nco_freq = (reg0a3 & 0xC0);
_io_iface->poke8(0x0a0, 0x15 | (nco_freq >> 1));
reg0a3 = _io_iface->peek8(0x0a3);
_io_iface->poke8(0x0a3, (reg0a3 & 0x3F) | nco_freq);
@@ -827,7 +823,7 @@ void ad9361_device_t::_calibrate_tx_quadrature()
/* This calibration must be done in a certain order, and for both TX_A
* and TX_B, separately. Store the original setting so that we can
* restore it later. */
- uint8_t orig_reg_inputsel = _regs.inputsel;
+ boost::uint8_t orig_reg_inputsel = _regs.inputsel;
/***********************************************************************
* TX1/2-A Calibration
@@ -862,9 +858,9 @@ void ad9361_device_t::_calibrate_tx_quadrature()
* Note that this table is fixed for all frequency settings. */
void ad9361_device_t::_program_mixer_gm_subtable()
{
- uint8_t gain[] = { 0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C, 0x58,
+ boost::uint8_t gain[] = { 0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C, 0x58,
0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x00 };
- uint8_t gm[] = { 0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C, 0x2F, 0x31,
+ boost::uint8_t gm[] = { 0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C, 0x2F, 0x31,
0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E };
/* Start the clock. */
@@ -895,8 +891,8 @@ void ad9361_device_t::_program_mixer_gm_subtable()
void ad9361_device_t::_program_gain_table() {
/* Figure out which gain table we should be using for our current
* frequency band. */
- uint8_t (*gain_table)[5] = NULL;
- uint8_t new_gain_table;
+ boost::uint8_t (*gain_table)[5] = NULL;
+ boost::uint8_t new_gain_table;
if (_rx_freq < 1300e6) {
gain_table = gain_table_sub_1300mhz;
new_gain_table = 1;
@@ -923,7 +919,7 @@ void ad9361_device_t::_program_gain_table() {
_io_iface->poke8(0x137, 0x1A);
/* IT'S PROGRAMMING TIME. */
- uint8_t index = 0;
+ boost::uint8_t index = 0;
for (; index < 77; index++) {
_io_iface->poke8(0x130, index);
_io_iface->poke8(0x131, gain_table[index][1]);
@@ -999,18 +995,18 @@ void ad9361_device_t::_setup_synth(direction_t direction, double vcorate)
post_err_msg("vcoindex > 53");
/* Parse the values out of the LUT based on our calculated index... */
- uint8_t vco_output_level = synth_cal_lut[vcoindex][0];
- uint8_t vco_varactor = synth_cal_lut[vcoindex][1];
- uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2];
- uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3];
- uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4];
- uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5];
- uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6];
- uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7];
- uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8];
- uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9];
- uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10];
- uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11];
+ boost::uint8_t vco_output_level = synth_cal_lut[vcoindex][0];
+ boost::uint8_t vco_varactor = synth_cal_lut[vcoindex][1];
+ boost::uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2];
+ boost::uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3];
+ boost::uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4];
+ boost::uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5];
+ boost::uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6];
+ boost::uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7];
+ boost::uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8];
+ boost::uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9];
+ boost::uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10];
+ boost::uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11];
/* ... annnd program! */
if (direction == RX) {
@@ -1484,9 +1480,9 @@ void ad9361_device_t::initialize()
/* Data delay for TX and RX data clocks */
digital_interface_delays_t timing =
_client_params->get_digital_interface_timing();
- uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4)
+ boost::uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4)
| (timing.rx_data_delay & 0xF);
- uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4)
+ boost::uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4)
| (timing.tx_data_delay & 0xF);
_io_iface->poke8(0x006, rx_delays);
_io_iface->poke8(0x007, tx_delays);
@@ -1638,7 +1634,7 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
/* We must be in the SLEEP / WAIT state to do this. If we aren't already
* there, transition the ENSM to State 0. */
- uint8_t current_state = _io_iface->peek8(0x017) & 0x0F;
+ boost::uint8_t current_state = _io_iface->peek8(0x017) & 0x0F;
switch (current_state) {
case 0x05:
/* We are in the ALERT state. */
@@ -1660,8 +1656,8 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
/* Store the current chain / antenna selections so that we can restore
* them at the end of this routine; all chains will be enabled from
* within setup_rates for calibration purposes. */
- uint8_t orig_tx_chains = _regs.txfilt & 0xC0;
- uint8_t orig_rx_chains = _regs.rxfilt & 0xC0;
+ boost::uint8_t orig_tx_chains = _regs.txfilt & 0xC0;
+ boost::uint8_t orig_rx_chains = _regs.rxfilt & 0xC0;
/* Call into the clock configuration / settings function. This is where
* all the hard work gets done. */
@@ -1776,8 +1772,8 @@ void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2)
}
/* Check for FDD state */
- uint8_t set_back_to_fdd = 0;
- uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F;
+ boost::uint8_t set_back_to_fdd = 0;
+ boost::uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F;
if (ensm_state == 0xA) // FDD
{
/* Put into ALERT state (via the FDD flush state). */
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
index f54e04473..4b637e95c 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
@@ -5,7 +5,6 @@
#ifndef INCLUDED_AD9361_DEVICE_H
#define INCLUDED_AD9361_DEVICE_H
-#include <stdint.h>
#include <ad9361_client.h>
#include <boost/noncopyable.hpp>
@@ -64,7 +63,7 @@ public:
void data_port_loopback(const bool loopback_enabled);
private: //Methods
- void _program_fir_filter(direction_t direction, int num_taps, uint16_t *coeffs);
+ void _program_fir_filter(direction_t direction, int num_taps, boost::uint16_t *coeffs);
void _setup_tx_fir(size_t num_taps);
void _setup_rx_fir(size_t num_taps);
void _calibrate_lock_bbpll();
@@ -90,13 +89,13 @@ private: //Methods
private: //Members
typedef struct {
- uint8_t vcodivs;
- uint8_t inputsel;
- uint8_t rxfilt;
- uint8_t txfilt;
- uint8_t bbpll;
- uint8_t bbftune_config;
- uint8_t bbftune_mode;
+ boost::uint8_t vcodivs;
+ boost::uint8_t inputsel;
+ boost::uint8_t rxfilt;
+ boost::uint8_t txfilt;
+ boost::uint8_t bbpll;
+ boost::uint8_t bbftune_config;
+ boost::uint8_t bbftune_mode;
} chip_regs_t;
//Interfaces
@@ -106,10 +105,10 @@ private: //Members
double _rx_freq, _tx_freq, _req_rx_freq, _req_tx_freq;
double _baseband_bw, _bbpll_freq, _adcclock_freq;
double _req_clock_rate, _req_coreclk;
- uint16_t _rx_bbf_tunediv;
- uint8_t _curr_gain_table;
- uint32_t _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain;
- int32_t _tfir_factor;
+ boost::uint16_t _rx_bbf_tunediv;
+ boost::uint8_t _curr_gain_table;
+ boost::uint32_t _rx1_gain, _rx2_gain, _tx1_gain, _tx2_gain;
+ boost::int32_t _tfir_factor;
//Register soft-copies
chip_regs_t _regs;
};
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h
index 2b4374025..4059ad7ee 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_filter_taps.h
@@ -5,6 +5,8 @@
#ifndef INCLUDED_AD9361_FILTER_TAPS_HPP
#define INCLUDED_AD9361_FILTER_TAPS_HPP
+#include <boost/cstdint.hpp>
+
/* A default 128-tap filter that can be used for generic circumstances. */
/* static uint16_t default_128tap_coeffs[] = {
0x0001,0xfff1,0xffcf,0xffc0,0xffe8,0x0020,0x001a,0xffe3,
@@ -45,25 +47,25 @@ static uint16_t lte10mhz_tx_coeffs[] = {
/* 127 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,32)) (center tap tweaked to 32767) */
-static int16_t hb127_coeffs[] = {
+static boost::int16_t hb127_coeffs[] = {
-0,0,1,-0,-2,0,3,-0,-5,0,8,-0,-11,0,17,-0,-24,0,33,-0,-45,0,61,-0,-80,0,104,-0,-134,0,169,-0,
-213,0,264,-0,-327,0,401,-0,-489,0,595,-0,-724,0,880,-0,-1075,0,1323,-0,-1652,0,2114,-0,-2819,0,4056,-0,-6883,0,20837,32767,
20837,0,-6883,-0,4056,0,-2819,-0,2114,0,-1652,-0,1323,0,-1075,-0,880,0,-724,-0,595,0,-489,-0,401,0,-327,-0,264,0,-213,-0,
169,0,-134,-0,104,0,-80,-0,61,0,-45,-0,33,0,-24,-0,17,0,-11,-0,8,0,-5,-0,3,0,-2,-0,1,0,-0, 0 };
/* 95 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,24)) (center tap tweaked to 32767) */
-static int16_t hb95_coeffs[] = {
+static boost::int16_t hb95_coeffs[] = {
-4,0,8,-0,-14,0,23,-0,-36,0,52,-0,-75,0,104,-0,-140,0,186,-0,-243,0,314,-0,-400,0,505,-0,-634,0,793,-0,
-993,0,1247,-0,-1585,0,2056,-0,-2773,0,4022,-0,-6862,0,20830,32767,20830,0,-6862,-0,4022,0,-2773,-0,2056,0,-1585,-0,1247,0,-993,-0,
793,0,-634,-0,505,0,-400,-0,314,0,-243,-0,186,0,-140,-0,104,0,-75,-0,52,0,-36,-0,23,0,-14,-0,8,0,-4,0};
/* 63 tap Halfband designed with: round(2^16 * halfgen4(0.9/4,16)) (center tap tweaked to 32767) */
-static int16_t hb63_coeffs[] = {
+static boost::int16_t hb63_coeffs[] = {
-58,0,83,-0,-127,0,185,-0,-262,0,361,-0,-488,0,648,-0,-853,0,1117,-0,-1466,0,1954,-0,-2689,0,3960,-0,-6825,0,20818,32767,
20818,0,-6825,-0,3960,0,-2689,-0,1954,0,-1466,-0,1117,0,-853,-0,648,0,-488,-0,361,0,-262,-0,185,0,-127,-0,83,0,-58,0};
/* 47 tap Halfband designed with: round(2^16 * halfgen4(0.85/4,12)) (center tap tweaked to 32767) */
-static int16_t hb47_coeffs[] = {
+static boost::int16_t hb47_coeffs[] = {
-50,0,98,-0,-181,0,307,-0,-489,0,747,-0,-1109,0,1628,-0,-2413,0,3750,-0,-6693,0,20773,32767,20773,0,-6693,-0,3750,0,-2413,-0,
1628,0,-1109,-0,747,0,-489,-0,307,0,-181,-0,98,0,-50,0};
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h
index d38efd11d..786029d6e 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_gain_tables.h
@@ -5,7 +5,9 @@
#ifndef INCLUDED_AD9361_GAIN_TABLES_HPP
#define INCLUDED_AD9361_GAIN_TABLES_HPP
-uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
+#include <boost/cstdint.hpp>
+
+boost::uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
@@ -34,7 +36,7 @@ uint8_t gain_table_sub_1300mhz[77][5] = { {0,0x00,0x00,0x20,1},
{76,0x6F,0x38,0x20,1}};
-uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1},
+boost::uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x01,0x00,0},
{4,0x00,0x02,0x00,0}, {5,0x00,0x03,0x00,0}, {6,0x00,0x04,0x00,0},
{7,0x00,0x05,0x00,0}, {8,0x01,0x03,0x20,1}, {9,0x01,0x04,0x00,0},
@@ -63,7 +65,7 @@ uint8_t gain_table_1300mhz_to_4000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{76,0x6F,0x38,0x20,1}};
-uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1},
+boost::uint8_t gain_table_4000mhz_to_6000mhz[77][5] = { {0,0x00,0x00,0x20,1},
{1,0x00,0x00,0x00,0}, {2,0x00,0x00,0x00,0}, {3,0x00,0x00,0x00,0},
{4,0x00,0x00,0x00,0}, {5,0x00,0x01,0x00,0}, {6,0x00,0x02,0x00,0},
{7,0x00,0x03,0x00,0}, {8,0x01,0x01,0x20,1}, {9,0x01,0x02,0x00,0},
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 16:50:28 +0000