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-rw-r--r--fpga/usrp2/fifo/fifo_2clock.v44
-rw-r--r--fpga/usrp2/gpif/packet_reframer.v5
-rw-r--r--fpga/usrp2/gpif/slave_fifo.v126
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
4 files changed, 92 insertions, 85 deletions
diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v
index 756ad508f..98aab18a5 100644
--- a/fpga/usrp2/fifo/fifo_2clock.v
+++ b/fpga/usrp2/fifo/fifo_2clock.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -31,42 +31,44 @@ module fifo_2clock
assign src_rdy_o = ~empty;
assign write = src_rdy_i & dst_rdy_o;
assign read = src_rdy_o & dst_rdy_i;
- wire dummy;
-
+
generate
- if(WIDTH==36)
+ if((WIDTH <= 36) && (WIDTH > 19)) begin
+ wire [35:0] data_in_wide, data_out_wide;
+ assign data_in_wide[WIDTH-1:0] = datain;
+ assign dataout = data_out_wide[WIDTH-1:0];
if(SIZE==9)
fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
(.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if(SIZE==11)
fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk
(.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else if(SIZE==6)
fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk
(.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
else
fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
(.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
- else if((WIDTH==19) & (SIZE==4))
- fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
- (.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
- else if((WIDTH==18) & (SIZE==4))
+ .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ end
+ else if((WIDTH <= 19) && (SIZE <= 4)) begin
+ wire [18:0] data_in_wide, data_out_wide;
+ assign data_in_wide[WIDTH-1:0] = datain;
+ assign dataout = data_out_wide[WIDTH-1:0];
fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
(.rst(arst),
- .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ .wr_clk(wclk),.din(data_in_wide),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+ .rd_clk(rclk),.dout(data_out_wide),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+ end
endgenerate
-
+
assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
assign space = ((1<<SIZE)+1)-level_wclk;
diff --git a/fpga/usrp2/gpif/packet_reframer.v b/fpga/usrp2/gpif/packet_reframer.v
index 8bb8a3678..e0ce9e174 100644
--- a/fpga/usrp2/gpif/packet_reframer.v
+++ b/fpga/usrp2/gpif/packet_reframer.v
@@ -20,7 +20,7 @@
module packet_reframer
(input clk, input reset, input clear,
- input [18:0] data_i,
+ input [15:0] data_i,
input src_rdy_i,
output dst_rdy_o,
output [18:0] data_o,
@@ -60,8 +60,7 @@ module packet_reframer
wire occ_out = 0;
assign eof_out = (state == RF_PKT) & (length == 2);
wire sof_out = (state == RF_IDLE);
- wire [15:0] data_out = data_i[15:0];
- assign data_o = {occ_out, eof_out, sof_out, data_out};
+ assign data_o = {occ_out, eof_out, sof_out, data_i[15:0]};
endmodule // packet_reframer
diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v
index 10740942b..b1d642fca 100644
--- a/fpga/usrp2/gpif/slave_fifo.v
+++ b/fpga/usrp2/gpif/slave_fifo.v
@@ -46,11 +46,15 @@ module slave_fifo
output [31:0] debug0, output [31:0] debug1
);
+ reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
+
// inputs to FPGA (all active low)
- wire FX2_DE = ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
- wire FX2_CE = ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
- wire FX2_DF = ~gpif_ctl[2]; //EP6 FX2 FIFO full (FLAGC)
- wire FX2_CF = ~gpif_ctl[3]; //EP8 FX2 FIFO full (FLAGD)
+ always @(posedge gpif_clk) begin
+ FX2_DE <= ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
+ FX2_CE <= ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
+ FX2_DF <= ~gpif_ctl[2]; //EP6 FX2 FIFO full (FLAGC)
+ FX2_CF <= ~gpif_ctl[3]; //EP8 FX2 FIFO full (FLAGD)
+ end
wire [17:0] gpif_d_out_ctrl, gpif_d_out_data, gpif_d_out;
@@ -68,7 +72,7 @@ module slave_fifo
//tx
wire ctrl_tx_dst_rdy; //sm input, ctrl tx path has space
wire ctrl_tx_src_rdy; //sm output, ctrl tx path enable
- reg data_tx_dst_rdy; //sm input, data tx path has space
+ wire data_tx_dst_rdy; //sm input, data tx path has space
wire data_tx_src_rdy; //sm output, data tx path enable
//rx
@@ -77,9 +81,9 @@ module slave_fifo
wire data_rx_dst_rdy; //sm output, data rx path enable
wire data_rx_src_rdy; //sm input, data rx path has space
- reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer
+ reg tx_data_enough_space;
- wire sop, eop; //SOP/EOP markers for TX data packets
+ reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer
reg pktend_latch;
@@ -93,6 +97,7 @@ module slave_fifo
localparam STATE_CTRL_TX_SLOE = 8;
localparam STATE_DATA_RX_ADR = 1;
localparam STATE_CTRL_RX_ADR = 4;
+ localparam STATE_PKTEND_ADR = 10;
localparam STATE_PKTEND = 7;
//logs the last bus user for xfer fairness
@@ -118,16 +123,16 @@ module slave_fifo
state <= STATE_CTRL_TX_SLOE;
else if(ctrl_rx_src_rdy & ~FX2_CF) //if the ctrl fifo has data and the FX2 isn't full
state <= STATE_CTRL_RX_ADR;
- else if(data_tx_dst_rdy & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX) //if there's room in the data fifo and the FX2 has data
+ else if(data_tx_dst_rdy & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX & tx_data_enough_space) //if there's room in the data fifo and the FX2 has data
state <= STATE_DATA_TX_SLOE;
else if(data_rx_src_rdy & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) //if the data fifo has data and the FX2 isn't full
state <= STATE_DATA_RX_ADR;
- else if(data_tx_dst_rdy & ~FX2_DE)
+ else if(data_tx_dst_rdy & ~FX2_DE & tx_data_enough_space)
state <= STATE_DATA_TX_SLOE;
else if(data_rx_src_rdy & ~FX2_DF)
state <= STATE_DATA_RX_ADR;
else if(~data_rx_src_rdy & ~dsp_rx_run & pktend_latch & ~FX2_DF)
- state <= STATE_PKTEND;
+ state <= STATE_PKTEND_ADR;
if(data_rx_src_rdy)
pktend_latch <= 1;
@@ -145,13 +150,18 @@ module slave_fifo
STATE_DATA_RX:
begin
- if((transfer_count == data_transfer_size) | FX2_DF | (~data_rx_src_rdy))
- state <= STATE_IDLE;
-
- transfer_count <= transfer_count + 1;
- last_data_bus_hog <= BUS_HOG_RX;
+ if(data_rx_src_rdy && data_rx_dst_rdy && (transfer_count != data_transfer_size))
+ transfer_count <= transfer_count + 1;
+ else
+ state <= STATE_IDLE;
+ last_data_bus_hog <= BUS_HOG_RX;
end
+ STATE_PKTEND_ADR:
+ begin
+ state <= STATE_PKTEND;
+ end
+
STATE_PKTEND:
begin
state <= STATE_IDLE;
@@ -160,22 +170,25 @@ module slave_fifo
STATE_DATA_TX:
begin
- if((transfer_count == data_transfer_size) | FX2_DE )/*| (~data_tx_dst_rdy))*/
- state <= STATE_IDLE;
- transfer_count <= transfer_count + 1;
- last_data_bus_hog <= BUS_HOG_TX;
+ if(data_tx_dst_rdy && data_tx_src_rdy && (transfer_count != data_transfer_size))
+ transfer_count <= transfer_count + 1;
+ else
+ state <= STATE_IDLE;
+ last_data_bus_hog <= BUS_HOG_TX;
end
STATE_CTRL_RX:
begin
- if(FX2_CF | (~ctrl_rx_src_rdy))
- state <= STATE_IDLE;
- transfer_count <= transfer_count + 1;
+ if(ctrl_rx_src_rdy && ctrl_rx_dst_rdy)
+ transfer_count <= transfer_count + 1;
+ else
+ state <= STATE_IDLE;
end
STATE_CTRL_TX:
begin
- if(FX2_CE | (~ctrl_tx_dst_rdy))
- state <= STATE_IDLE;
- transfer_count <= transfer_count + 1;
+ if(ctrl_tx_dst_rdy && ctrl_tx_src_rdy)
+ transfer_count <= transfer_count + 1;
+ else
+ state <= STATE_IDLE;
end
endcase
end
@@ -184,18 +197,15 @@ module slave_fifo
// fifo signal assignments and enables
//enable fifos
- assign data_rx_dst_rdy = (state == STATE_DATA_RX);
- assign data_tx_src_rdy = (state == STATE_DATA_TX);
- assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX);
- assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX);
-
- //tx framing (this is super suspect)
- //eop should be used only to set the EOP bit going into FIFOs
- wire eop_data, eop_ctrl;
- assign sop = (transfer_count == 0);
- assign eop_data = (transfer_count == (data_transfer_size-1));
+ assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF;
+ assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE;
+ assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF;
+ assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE;
+
+ //framing for TX ctrl packets
+ wire sop_ctrl, eop_ctrl;
+ assign sop_ctrl = (transfer_count == 0);
assign eop_ctrl = (transfer_count == (ctrl_transfer_size-1));
- assign eop = (state == STATE_DATA_TX) ? eop_data : eop_ctrl;
// ////////////////////////////////////////////////////////////////////
// set GPIF pins
@@ -205,15 +215,15 @@ module slave_fifo
// {0,1}: EP4, ctrl TX from host
// {1,0}: EP6, data RX to host
// {1,1}: EP8, ctrl RX to host
- assign fifoadr = {(state == STATE_DATA_RX) | (state == STATE_CTRL_RX) | (state == STATE_DATA_RX_ADR) | (state == STATE_CTRL_RX_ADR) | (state == STATE_PKTEND),
+ assign fifoadr = {(state == STATE_DATA_RX) | (state == STATE_CTRL_RX) | (state == STATE_DATA_RX_ADR) | (state == STATE_CTRL_RX_ADR) | (state == STATE_PKTEND) | (state == STATE_PKTEND_ADR),
(state == STATE_CTRL_RX) | (state == STATE_CTRL_RX_ADR) | (state == STATE_CTRL_TX) | (state == STATE_CTRL_TX_SLOE)};
//set sloe, slwr, slrd (all active low)
//SLOE gets asserted when we want data from the FX2; i.e., TX mode
assign sloe = ~{(state == STATE_DATA_TX) | (state == STATE_CTRL_TX) | (state == STATE_DATA_TX_SLOE) | (state == STATE_CTRL_TX_SLOE)};
//"read" and "write" here are from the master's point of view;
//so "read" means "transmit" and "write" means "receive"
- assign slwr = ~{(state == STATE_DATA_RX) | (state == STATE_CTRL_RX)};
- assign slrd = ~{(state == STATE_DATA_TX) | (state == STATE_CTRL_TX)};
+ assign slwr = ~{(data_rx_src_rdy && data_rx_dst_rdy) || (ctrl_rx_src_rdy && ctrl_rx_dst_rdy)};
+ assign slrd = ~{(data_tx_src_rdy && data_tx_dst_rdy) || (ctrl_tx_src_rdy && ctrl_tx_dst_rdy)};
wire pktend_ctrl, pktend_data;
assign pktend_ctrl = ((~ctrl_rx_src_rdy | gpif_d_out_ctrl[17]) & (state == STATE_CTRL_RX));
@@ -228,43 +238,39 @@ module slave_fifo
// ////////////////////////////////////////////////////////////////////
// TX Data Path
- wire [18:0] tx19_data;
- wire tx19_src_rdy, tx19_dst_rdy;
+ wire [15:0] txfifo_data;
+ wire txfifo_src_rdy, txfifo_dst_rdy;
wire [35:0] tx36_data;
wire tx36_src_rdy, tx36_dst_rdy;
- wire [17:0] data_tx_int;
- wire tx_src_rdy_int, tx_dst_rdy_int;
+ wire [15:0] data_tx_2clk;
+ wire tx_src_rdy_2clk, tx_dst_rdy_2clk;
wire [15:0] wr_fifo_space;
-
+
always @(posedge gpif_clk)
- if(gpif_rst)
- data_tx_dst_rdy <= 0;
- else
- data_tx_dst_rdy <= wr_fifo_space >= 256;
+ tx_data_enough_space <= (wr_fifo_space >= data_transfer_size);
- fifo_cascade #(.WIDTH(18), .SIZE(12)) wr_fifo
+ fifo_cascade #(.WIDTH(16), .SIZE(12)) wr_fifo
(.clk(gpif_clk), .reset(gpif_rst), .clear(clear_tx),
- .datain({eop,sop,gpif_d}), .src_rdy_i(data_tx_src_rdy), .dst_rdy_o(/*data_tx_dst_rdy*/), .space(wr_fifo_space),
- .dataout(data_tx_int), .src_rdy_o(tx_src_rdy_int), .dst_rdy_i(tx_dst_rdy_int), .occupied());
+ .datain(gpif_d), .src_rdy_i(data_tx_src_rdy), .dst_rdy_o(data_tx_dst_rdy), .space(wr_fifo_space),
+ .dataout(txfifo_data), .src_rdy_o(txfifo_src_rdy), .dst_rdy_i(txfifo_dst_rdy), .occupied());
- fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk
- (.wclk(gpif_clk), .datain(data_tx_int), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), .space(),
- .rclk(fifo_clk), .dataout(tx19_data[17:0]), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), .occupied(),
+ fifo_2clock_cascade #(.WIDTH(16), .SIZE(4)) wr_fifo_2clk
+ (.wclk(gpif_clk), .datain(txfifo_data), .src_rdy_i(txfifo_src_rdy), .dst_rdy_o(txfifo_dst_rdy), .space(),
+ .rclk(fifo_clk), .dataout(data_tx_2clk), .src_rdy_o(tx_src_rdy_2clk), .dst_rdy_i(tx_dst_rdy_2clk), .occupied(),
.arst(fifo_rst));
-
- assign tx19_data[18] = 1'b0;
- // join vita packets which are longer than one frame, drop frame padding
+ // join vita packets which are longer than one frame, add SOP/EOP/OCC
wire [18:0] refr_data;
wire refr_src_rdy, refr_dst_rdy;
+ //below 3 signals for debug only
wire refr_state;
wire refr_eof;
wire [15:0] refr_len;
packet_reframer tx_packet_reframer
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
- .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy),
+ .data_i(data_tx_2clk), .src_rdy_i(tx_src_rdy_2clk), .dst_rdy_o(tx_dst_rdy_2clk),
.data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy),
.state(refr_state), .eof_out(refr_eof), .length(refr_len));
@@ -308,7 +314,7 @@ module slave_fifo
.arst(fifo_rst));
//rd_fifo buffers writes to the 2clock fifo above
- fifo_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rd_fifo
+ fifo_cascade #(.WIDTH(16), .SIZE(RXFIFOSIZE)) rd_fifo
(.clk(~gpif_clk), .reset(gpif_rst), .clear(clear_rx),
.datain(data_rx_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .space(rxfifospace),
.dataout(gpif_d_out_data), .src_rdy_o(data_rx_src_rdy), .dst_rdy_i(data_rx_dst_rdy), .occupied());
@@ -341,7 +347,7 @@ module slave_fifo
//how does this use fifo_clk instead of wb_clk
//answer: on b100 fifo clk IS wb clk
fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk
- (.wclk(gpif_clk), .datain({1'b0,eop,sop,gpif_d}),
+ (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop_ctrl,gpif_d}),
.src_rdy_i(ctrl_tx_src_rdy), .dst_rdy_o(ctrl_tx_dst_rdy), .space(),
.rclk(fifo_clk), .dataout(ctrl_data),
.src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy), .occupied(),
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index e335fb8bb..26714b669 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd0}; //major, minor
+ localparam compat_num = {16'd9, 16'd1}; //major, minor
wire [31:0] reg_test32;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 12:04:43 +0000