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-rw-r--r--host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml50
-rw-r--r--host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml70
-rw-r--r--host/include/uhd/rfnoc/blocks/ddc_1x64.yml39
-rw-r--r--host/include/uhd/rfnoc/blocks/ddc_2x64.yml55
-rw-r--r--host/include/uhd/rfnoc/blocks/duc_1x64.yml37
-rw-r--r--host/include/uhd/rfnoc/blocks/duc_2x64.yml55
-rw-r--r--host/include/uhd/rfnoc/blocks/fft_1x64.yml33
-rw-r--r--host/include/uhd/rfnoc/blocks/null_src_sink.yml29
-rw-r--r--host/include/uhd/rfnoc/blocks/radio.yml17
-rw-r--r--host/include/uhd/rfnoc/blocks/radio_1x64.yml36
-rw-r--r--host/include/uhd/rfnoc/blocks/radio_2x64.yml56
11 files changed, 199 insertions, 278 deletions
diff --git a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml
index ddb7eed28..1e5bc8452 100644
--- a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml
@@ -5,70 +5,56 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xF1F00000
+parameters:
+ NUM_PORTS: 2
+ MEM_DATA_W: 64
+ MEM_ADDR_W: 30
+ FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
+ FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
+ MEM_CLK_RATE: "300e6"
+
clocks:
- name: rfnoc_chdr
freq: "[]"
- name: rfnoc_ctrl
freq: "[]"
+ - name: mem
+ freq: "[]"
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
- clk_domain: rfnoc_ctrl
+ clk_domain: mem
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-# The parameters section lists parameters that get added to the generated
-# Verilog for the module instantiation. Any parameter listed here may be set to
-# different value in the image builder YAML file.
-parameters:
- NUM_PORTS: 2
- MEM_DATA_W: 64
- MEM_ADDR_W: 30
- FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
- FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
- MEM_CLK_RATE: "300e6"
-
data:
fpga_iface: axis_chdr
- clk_domain: rfnoc_chdr
- mtu: 1024
+ clk_domain: mem
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port1:
- index: 1
+ in_1:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port1:
- index: 1
+ out_1:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
diff --git a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml
index 8fed9d6a2..9ef16c7c5 100644
--- a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml
+++ b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml
@@ -5,102 +5,76 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xF1F00000
+parameters:
+ NUM_PORTS: 4
+ MEM_DATA_W: 64
+ MEM_ADDR_W: 32
+ FIFO_ADDR_BASE: "{32'hC0000000, 32'h80000000, 32'h40000000, 32'h00000000}"
+ FIFO_ADDR_MASK: "{32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF}"
+ MEM_CLK_RATE: "300e6"
+
clocks:
- name: rfnoc_chdr
freq: "[]"
- name: rfnoc_ctrl
freq: "[]"
+ - name: mem
+ freq: "[]"
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
- clk_domain: rfnoc_ctrl
+ clk_domain: mem
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-# The parameters section lists parameters that get added to the generated
-# Verilog for the module instantiation. Any parameter listed here may be set to
-# different value in the image builder YAML file.
-parameters:
- NUM_PORTS: 4
- MEM_DATA_W: 64
- MEM_ADDR_W: 32
- FIFO_ADDR_BASE: "{32'hC0000000, 32'h80000000, 32'h40000000, 32'h00000000}"
- FIFO_ADDR_MASK: "{32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF}"
- MEM_CLK_RATE: "300e6"
-
data:
fpga_iface: axis_chdr
- clk_domain: rfnoc_chdr
- mtu: 1024
+ clk_domain: mem
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port1:
- index: 1
+ in_1:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port2:
- index: 0
+ in_2:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port3:
- index: 1
+ in_3:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port1:
- index: 1
+ out_1:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port2:
- index: 0
+ out_2:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
- port3:
- index: 1
+ out_3:
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
format: int32
mdata_sig: ~
diff --git a/host/include/uhd/rfnoc/blocks/ddc_1x64.yml b/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
index 2ea0af151..bfdbca04f 100644
--- a/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
@@ -5,6 +5,11 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xDDC00000
+parameters:
+ NUM_PORTS: 1
+ NUM_HB: 3
+ CIC_MAX_DECIM: 255
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -16,44 +21,36 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
clk_domain: ce
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-parameters:
- NUM_PORTS: 1
- NUM_HB: 3
- CIC_MAX_DECIM: 255
-
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_data
clk_domain: ce
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
+ num_ports: NUM_PORTS
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
+ num_ports: NUM_PORTS
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
-io_port:
-
registers:
properties:
diff --git a/host/include/uhd/rfnoc/blocks/ddc_2x64.yml b/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
index ae08ecece..2aa864b3a 100644
--- a/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
@@ -5,6 +5,11 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xDDC00000
+parameters:
+ NUM_PORTS: 2
+ NUM_HB: 3
+ CIC_MAX_DECIM: 255
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -16,60 +21,48 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
clk_domain: ce
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-parameters:
- NUM_PORTS: 2
- NUM_HB: 3
- CIC_MAX_DECIM: 255
-
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_data
clk_domain: ce
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ in_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ out_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
-io_port:
-
registers:
properties:
diff --git a/host/include/uhd/rfnoc/blocks/duc_1x64.yml b/host/include/uhd/rfnoc/blocks/duc_1x64.yml
index 963f576d2..adcdf1554 100644
--- a/host/include/uhd/rfnoc/blocks/duc_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/duc_1x64.yml
@@ -5,6 +5,11 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xD0C00000
+parameters:
+ NUM_PORTS: 1
+ NUM_HB: 3
+ CIC_MAX_INTERP: 255
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -16,44 +21,34 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
clk_domain: ce
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-parameters:
- NUM_PORTS: 1
- NUM_HB: 3
- CIC_MAX_INTERP: 255
-
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_data
clk_domain: ce
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
-io_port:
-
registers:
properties:
diff --git a/host/include/uhd/rfnoc/blocks/duc_2x64.yml b/host/include/uhd/rfnoc/blocks/duc_2x64.yml
index 6798ef412..7fb88dd22 100644
--- a/host/include/uhd/rfnoc/blocks/duc_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/duc_2x64.yml
@@ -5,6 +5,11 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0xD0C00000
+parameters:
+ NUM_PORTS: 2
+ NUM_HB: 3
+ CIC_MAX_INTERP: 255
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -16,60 +21,48 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
clk_domain: ce
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-parameters:
- NUM_PORTS: 2
- NUM_HB: 3
- CIC_MAX_INTERP: 255
-
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_data
clk_domain: ce
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ in_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ out_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 5
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
-io_port:
-
registers:
properties:
diff --git a/host/include/uhd/rfnoc/blocks/fft_1x64.yml b/host/include/uhd/rfnoc/blocks/fft_1x64.yml
index 488d9b7c4..1c3d2946b 100644
--- a/host/include/uhd/rfnoc/blocks/fft_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/fft_1x64.yml
@@ -8,6 +8,12 @@ noc_id: 0xFF700000
# FPGA repository
makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_fft/Makefile.srcs"
+parameters:
+ EN_MAGNITUDE_OUT: 0
+ EN_MAGNITUDE_APPROX_OUT: 1
+ EN_MAGNITUDE_SQ_OUT: 1
+ EN_FFT_SHIFT: 1
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -19,36 +25,31 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
clk_domain: ce
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
-# parameters:
-
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_pyld_ctxt
clk_domain: ce
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 32
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 32
format: int32
mdata_sig: ~
diff --git a/host/include/uhd/rfnoc/blocks/null_src_sink.yml b/host/include/uhd/rfnoc/blocks/null_src_sink.yml
index b285201b1..919e61ebe 100644
--- a/host/include/uhd/rfnoc/blocks/null_src_sink.yml
+++ b/host/include/uhd/rfnoc/blocks/null_src_sink.yml
@@ -17,50 +17,45 @@ clocks:
control:
sw_iface: nocscript
fpga_iface: ctrlport
- interface_direction: master_slave
+ interface_direction: slave
fifo_depth: 32
- clk_domain: rfnoc_ctrl
+ clk_domain: rfnoc_chdr
ctrlport:
- byte_mode: True
+ byte_mode: False
timed: False
has_status: False
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_pyld_ctxt
clk_domain: rfnoc_chdr
- mtu: 1024
inputs:
sink:
- index: 0
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 2
format: int32
mdata_sig: ~
loop:
- index: 1
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 2
format: int32
mdata_sig: ~
outputs:
source:
- index: 0
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 2
format: int32
mdata_sig: ~
loop:
- index: 1
item_width: 32
nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 2
format: int32
mdata_sig: ~
diff --git a/host/include/uhd/rfnoc/blocks/radio.yml b/host/include/uhd/rfnoc/blocks/radio.yml
index 903ac1ecf..1da887c86 100644
--- a/host/include/uhd/rfnoc/blocks/radio.yml
+++ b/host/include/uhd/rfnoc/blocks/radio.yml
@@ -7,6 +7,7 @@ noc_id: 0x12AD1000
parameters:
NUM_PORTS: 2
+ NIPC: 1
clocks:
- name: rfnoc_chdr
@@ -23,9 +24,9 @@ control:
fifo_depth: 32
clk_domain: radio
ctrlport:
- byte_mode: False
- timed: False
- has_status: False
+ byte_mode: True
+ timed: True
+ has_status: True
data:
fpga_iface: axis_data
@@ -34,8 +35,8 @@ data:
in:
num_ports: NUM_PORTS
item_width: 32
- nipc: 2
- info_fifo_depth: 16
+ nipc: NIPC
+ info_fifo_depth: 32
payload_fifo_depth: MTU
format: int32
mdata_sig: ~
@@ -43,8 +44,8 @@ data:
out:
num_ports: NUM_PORTS
item_width: 32
- nipc: 2
- info_fifo_depth: 16
+ nipc: NIPC
+ info_fifo_depth: 32
payload_fifo_depth: MTU
format: int32
mdata_sig: ~
@@ -60,7 +61,7 @@ io_ports:
type: time_keeper
drive: listener
x300_radio:
- type: x300_radio
+ type: radio_1x32
drive: slave
registers:
diff --git a/host/include/uhd/rfnoc/blocks/radio_1x64.yml b/host/include/uhd/rfnoc/blocks/radio_1x64.yml
index 7fc9b7890..e5baf02d8 100644
--- a/host/include/uhd/rfnoc/blocks/radio_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/radio_1x64.yml
@@ -5,6 +5,9 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0x12AD1000
+parameters:
+ NUM_PORTS: 1
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -18,38 +21,29 @@ control:
fpga_iface: ctrlport
interface_direction: master_slave
fifo_depth: 32
- clk_domain: rfnoc_ctrl
+ clk_domain: radio
ctrlport:
byte_mode: True
- timed: False
- has_status: False
-
-# The parameters section lists parameters that get added to the generated
-# Verilog for the module instantiation. Any parameter listed here may be set to
-# different value in the image builder YAML file.
-parameters:
- NUM_PORTS: 1
+ timed: True
+ has_status: True
data:
- fpga_iface: axis_chdr
+ fpga_iface: axis_data
clk_domain: radio
- mtu: 1024
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
diff --git a/host/include/uhd/rfnoc/blocks/radio_2x64.yml b/host/include/uhd/rfnoc/blocks/radio_2x64.yml
index 4e7838392..0a3f6590d 100644
--- a/host/include/uhd/rfnoc/blocks/radio_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/radio_2x64.yml
@@ -5,6 +5,9 @@ rfnoc_version: 1.0
chdr_width: 64
noc_id: 0x12AD1000
+parameters:
+ NUM_PORTS: 2
+
clocks:
- name: rfnoc_chdr
freq: "[]"
@@ -18,54 +21,43 @@ control:
fpga_iface: ctrlport
interface_direction: master_slave
fifo_depth: 32
- clk_domain: rfnoc_ctrl
+ clk_domain: radio
ctrlport:
byte_mode: True
- timed: False
- has_status: False
-
-# The parameters section lists parameters that get added to the generated
-# Verilog for the module instantiation. Any parameter listed here may be set to
-# different value in the image builder YAML file.
-parameters:
- NUM_PORTS: 2
+ timed: True
+ has_status: True
data:
- fpga_iface: axis_chdr
- clk_domain: rfnoc_chdr
- mtu: 1024
+ fpga_iface: axis_data
+ clk_domain: radio
inputs:
- port0:
- index: 0
+ in_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ in_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
outputs:
- port0:
- index: 0
+ out_0:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
- port1:
- index: 1
+ out_1:
item_width: 32
- nipc: 2
- context_fifo_depth: 1
- payload_fifo_depth: 1
+ nipc: 1
+ info_fifo_depth: 32
+ payload_fifo_depth: MTU
format: int32
mdata_sig: ~
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 11:43:06 +0000