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-rw-r--r--usrp2/coregen/Makefile.srcs2
-rw-r--r--usrp2/coregen/coregen.cgp6
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.gise30
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.ncf0
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.ngc3
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.v3839
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.veo47
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.xco84
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk.xise72
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt12
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt46
-rw-r--r--usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl68
-rw-r--r--usrp2/extramfifo/ext_fifo.v115
-rwxr-xr-x[-rw-r--r--]usrp2/extramfifo/ext_fifo_tb.sh0
-rw-r--r--usrp2/extramfifo/ext_fifo_tb.v103
-rw-r--r--usrp2/extramfifo/nobl_fifo.v41
-rw-r--r--usrp2/top/u2plus/Makefile2
-rwxr-xr-xusrp2/top/u2plus/u2plus.ucf8
-rw-r--r--usrp2/top/u2plus/u2plus.v83
-rw-r--r--usrp2/top/u2plus/u2plus_core.v37
20 files changed, 4498 insertions, 100 deletions
diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs
index a59696d15..f163877a9 100644
--- a/usrp2/coregen/Makefile.srcs
+++ b/usrp2/coregen/Makefile.srcs
@@ -16,6 +16,8 @@ fifo_xlnx_16x19_2clk.v \
fifo_xlnx_16x19_2clk.xco \
fifo_xlnx_16x40_2clk.v \
fifo_xlnx_16x40_2clk.xco \
+fifo_xlnx_32x36_2clk.v \
+fifo_xlnx_32x36_2clk.xco \
fifo_xlnx_512x36_2clk_36to18.v \
fifo_xlnx_512x36_2clk_36to18.xco \
fifo_xlnx_512x36_2clk_18to36.v \
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp
index 4c9201aff..dd85a7f50 100644
--- a/usrp2/coregen/coregen.cgp
+++ b/usrp2/coregen/coregen.cgp
@@ -1,4 +1,4 @@
-# Date: Mon Jul 26 21:55:33 2010
+# Date: Fri Oct 15 07:50:19 2010
SET addpads = false
SET asysymbol = false
@@ -13,10 +13,10 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg456
SET removerpms = false
-SET simulationfiles = Behavioral
+SET simulationfiles = Structural
SET speedgrade = -5
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = /tmp/
-# CRC: 394da717
+# CRC: 983b9b45
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
new file mode 100644
index 000000000..70ee54054
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_32x36_2clk.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_32x36_2clk.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
new file mode 100644
index 000000000..d1ed419a7
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$56140<,[o}e~g`n;"2*726&;$9,)<>;.vnt*Ydo&lbjbQwloz\77~4>V8h`f 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\ No newline at end of file
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.v b/usrp2/coregen/fifo_xlnx_32x36_2clk.v
new file mode 100644
index 000000000..68a8caaf6
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.v
@@ -0,0 +1,3839 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.63c
+// \ \ Application: netgen
+// / / Filename: fifo_xlnx_32x36_2clk.v
+// /___/ /\ Timestamp: Fri Oct 15 00:50:08 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v
+// Device : 3s2000fg456-5
+// Input file : /tmp/_cg/fifo_xlnx_32x36_2clk.ngc
+// Output file : /tmp/_cg/fifo_xlnx_32x36_2clk.v
+// # of Modules : 1
+// Design Name : fifo_xlnx_32x36_2clk
+// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module fifo_xlnx_32x36_2clk (
+ rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input rd_en;
+ output almost_full;
+ output prog_full;
+ input wr_en;
+ output full;
+ output empty;
+ input wr_clk;
+ input rst;
+ input rd_clk;
+ output [35 : 0] dout;
+ input [35 : 0] din;
+
+ // synthesis translate_off
+
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ;
+ wire \BU2/N16 ;
+ wire \BU2/N14 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ;
+ wire \BU2/U0/grf.rf/mem/dout_i_not0001 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ;
+ wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
+ wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ;
+ wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ;
+ wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
+ wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
+ wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ;
+ wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ;
+ wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ;
+ wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ;
+ wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ;
+ wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
+ wire \BU2/N1 ;
+ wire NLW_VCC_P_UNCONNECTED;
+ wire NLW_GND_G_UNCONNECTED;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ;
+ wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ;
+ wire [35 : 0] din_2;
+ wire [35 : 0] dout_3;
+ wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ;
+ wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
+ wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ;
+ wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ;
+ wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ;
+ wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ;
+ wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
+ wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
+ wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
+ wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
+ wire [0 : 0] \BU2/rd_data_count ;
+ assign
+ dout[35] = dout_3[35],
+ dout[34] = dout_3[34],
+ dout[33] = dout_3[33],
+ dout[32] = dout_3[32],
+ dout[31] = dout_3[31],
+ dout[30] = dout_3[30],
+ dout[29] = dout_3[29],
+ dout[28] = dout_3[28],
+ dout[27] = dout_3[27],
+ dout[26] = dout_3[26],
+ dout[25] = dout_3[25],
+ dout[24] = dout_3[24],
+ dout[23] = dout_3[23],
+ dout[22] = dout_3[22],
+ dout[21] = dout_3[21],
+ dout[20] = dout_3[20],
+ dout[19] = dout_3[19],
+ dout[18] = dout_3[18],
+ dout[17] = dout_3[17],
+ dout[16] = dout_3[16],
+ dout[15] = dout_3[15],
+ dout[14] = dout_3[14],
+ dout[13] = dout_3[13],
+ dout[12] = dout_3[12],
+ dout[11] = dout_3[11],
+ dout[10] = dout_3[10],
+ dout[9] = dout_3[9],
+ dout[8] = dout_3[8],
+ dout[7] = dout_3[7],
+ dout[6] = dout_3[6],
+ dout[5] = dout_3[5],
+ dout[4] = dout_3[4],
+ dout[3] = dout_3[3],
+ dout[2] = dout_3[2],
+ dout[1] = dout_3[1],
+ dout[0] = dout_3[0],
+ din_2[35] = din[35],
+ din_2[34] = din[34],
+ din_2[33] = din[33],
+ din_2[32] = din[32],
+ din_2[31] = din[31],
+ din_2[30] = din[30],
+ din_2[29] = din[29],
+ din_2[28] = din[28],
+ din_2[27] = din[27],
+ din_2[26] = din[26],
+ din_2[25] = din[25],
+ din_2[24] = din[24],
+ din_2[23] = din[23],
+ din_2[22] = din[22],
+ din_2[21] = din[21],
+ din_2[20] = din[20],
+ din_2[19] = din[19],
+ din_2[18] = din[18],
+ din_2[17] = din[17],
+ din_2[16] = din[16],
+ din_2[15] = din[15],
+ din_2[14] = din[14],
+ din_2[13] = din[13],
+ din_2[12] = din[12],
+ din_2[11] = din[11],
+ din_2[10] = din[10],
+ din_2[9] = din[9],
+ din_2[8] = din[8],
+ din_2[7] = din[7],
+ din_2[6] = din[6],
+ din_2[5] = din[5],
+ din_2[4] = din[4],
+ din_2[3] = din[3],
+ din_2[2] = din[2],
+ din_2[1] = din[1],
+ din_2[0] = din[0];
+ VCC VCC_0 (
+ .P(NLW_VCC_P_UNCONNECTED)
+ );
+ GND GND_1 (
+ .G(NLW_GND_G_UNCONNECTED)
+ );
+ LUT3_L #(
+ .INIT ( 8'h90 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ),
+ .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h8241 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 )
+ );
+ LUT3_L #(
+ .INIT ( 8'h7F ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 )
+ );
+ LUT3_L #(
+ .INIT ( 8'h7F ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 )
+ );
+ LUT2_L #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .LO(\BU2/N16 )
+ );
+ LUT2_L #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .LO(\BU2/N14 )
+ );
+ INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 (
+ .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
+ );
+ INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 (
+ .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 )
+ );
+ LUT4 #(
+ .INIT ( 16'h2333 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6AAA ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6AAA ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
+ );
+ LUT3 #(
+ .INIT ( 8'h08 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 )
+ );
+ LUT3 #(
+ .INIT ( 8'h10 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I2(wr_en),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 )
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9000 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 )
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2])
+ );
+ LUT2 #(
+ .INIT ( 4'h9 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h5450 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 (
+ .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 )
+ );
+ LUT4 #(
+ .INIT ( 16'h5450 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 (
+ .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ),
+ .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+ .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+ .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 (
+ .I0(wr_en),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 )
+ );
+ LUT4 #(
+ .INIT ( 16'hECA0 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h9009 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8421 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8241 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 )
+ );
+ LUT4 #(
+ .INIT ( 16'h2333 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA6 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA6 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8])
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ),
+ .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ),
+ .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9])
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/N16 ),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/N14 ),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 )
+ );
+ LUT3 #(
+ .INIT ( 8'hA2 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(rd_en),
+ .O(\BU2/U0/grf.rf/mem/dout_i_not0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'hD ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+ .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8E8A ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(rd_en),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
+ );
+ LUT4 #(
+ .INIT ( 16'h6996 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
+ );
+ LUT4 #(
+ .INIT ( 16'h40FF ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 (
+ .I0(rd_en),
+ .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0])
+ );
+ LUT3 #(
+ .INIT ( 8'h6A ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
+ );
+ LUT3 #(
+ .INIT ( 8'h6A ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
+ );
+ LUT3 #(
+ .INIT ( 8'h96 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'h96 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
+ );
+ LUT3 #(
+ .INIT ( 8'hF2 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+ .I1(rd_en),
+ .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1])
+ );
+ LUT3 #(
+ .INIT ( 8'h08 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]),
+ .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 (
+ .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 (
+ .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h6 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 (
+ .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+ .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_comb1 (
+ .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ),
+ .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+ .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_comb1 (
+ .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ),
+ .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+ .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(almost_full)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(full)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]),
+ .Q(dout_3[0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]),
+ .Q(dout_3[1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]),
+ .Q(dout_3[2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]),
+ .Q(dout_3[3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]),
+ .Q(dout_3[4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_5 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]),
+ .Q(dout_3[5])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_6 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]),
+ .Q(dout_3[6])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_7 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]),
+ .Q(dout_3[7])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_8 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]),
+ .Q(dout_3[8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_9 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]),
+ .Q(dout_3[9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_10 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]),
+ .Q(dout_3[10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_11 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]),
+ .Q(dout_3[11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_12 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]),
+ .Q(dout_3[12])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_13 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]),
+ .Q(dout_3[13])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_14 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]),
+ .Q(dout_3[14])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_15 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]),
+ .Q(dout_3[15])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_16 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]),
+ .Q(dout_3[16])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_17 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]),
+ .Q(dout_3[17])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_18 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]),
+ .Q(dout_3[18])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_19 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]),
+ .Q(dout_3[19])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_20 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]),
+ .Q(dout_3[20])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_21 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]),
+ .Q(dout_3[21])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_22 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]),
+ .Q(dout_3[22])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_23 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]),
+ .Q(dout_3[23])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_24 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]),
+ .Q(dout_3[24])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_25 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]),
+ .Q(dout_3[25])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_26 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]),
+ .Q(dout_3[26])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_27 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]),
+ .Q(dout_3[27])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_28 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]),
+ .Q(dout_3[28])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_29 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]),
+ .Q(dout_3[29])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_30 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]),
+ .Q(dout_3[30])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_31 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]),
+ .Q(dout_3[31])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_32 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]),
+ .Q(dout_3[32])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_33 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]),
+ .Q(dout_3[33])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_34 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]),
+ .Q(dout_3[34])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/dout_i_35 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]),
+ .Q(dout_3[35])
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[35]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[35]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[34]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[34]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[33]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[32]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[33]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[32]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[31]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[31]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[30]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[29]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[29]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[30]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[28]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[28]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[27]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[27]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[26]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[25]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[26]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[24]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[24]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[25]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[23]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[22]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[23]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[22]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[21]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[21]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[20]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[19]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[19]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[20]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[18]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[18]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[17]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[17]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[16]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[15]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[16]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[15]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[14]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[14]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[13]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[12]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[12]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[13]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[11]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[11]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[10]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[10]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[9]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[8]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[9]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[8]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[7]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[7]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[6]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[5]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[5]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[6]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[4]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[4]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[3]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[3]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[2]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[1]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[2]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[1]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[0]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 )
+ );
+ RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 (
+ .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+ .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+ .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+ .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+ .D(din_2[0]),
+ .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+ .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+ .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+ .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+ .WCLK(wr_clk),
+ .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+ .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ),
+ .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]),
+ .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
+ .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .Q(prog_full)
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]),
+ .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> (
+ .CI(\BU2/N1 ),
+ .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+ .S(\BU2/rd_data_count [0]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3])
+ );
+ MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+ .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+ .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4])
+ );
+ XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+ .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4])
+ );
+ XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> (
+ .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]),
+ .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]),
+ .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(empty)
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
+ .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 (
+ .C(rd_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 (
+ .C(wr_clk),
+ .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+ .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+ .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 (
+ .C(rd_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d1 (
+ .C(wr_clk),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 )
+ );
+ FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg (
+ .C(rd_clk),
+ .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 )
+ );
+ FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg (
+ .C(wr_clk),
+ .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+ .D(\BU2/rd_data_count [0]),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d2 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+ .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+ .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/rstblk/rst_d3 (
+ .C(wr_clk),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+ .PRE(rst),
+ .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 )
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \BU2/U0/grf.rf/rstblk/RST_FULL_GEN (
+ .C(wr_clk),
+ .CLR(rst),
+ .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ),
+ .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i (
+ .C(rd_clk),
+ .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
+ .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+ .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 )
+ );
+ VCC \BU2/XST_VCC (
+ .P(\BU2/N1 )
+ );
+ GND \BU2/XST_GND (
+ .G(\BU2/rd_data_count [0])
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
new file mode 100644
index 000000000..eb98a2b70
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
@@ -0,0 +1,47 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_32x36_2clk YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [35 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [35 : 0]
+ .full(full),
+ .almost_full(almost_full),
+ .empty(empty),
+ .prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
new file mode 100644
index 000000000..1cf4c8ba5
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Fri Oct 15 07:50:15 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_32x36_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=24
+CSET full_threshold_negate_value=23
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=32
+CSET output_data_width=36
+CSET output_depth=32
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 8e84ee7f
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
new file mode 100644
index 000000000..0c3544a33
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_xlnx_32x36_2clk.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="fifo_xlnx_32x36_2clk.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ <association xil_pn:name="PostMapSimulation"/>
+ <association xil_pn:name="PostRouteSimulation"/>
+ <association xil_pn:name="PostTranslateSimulation"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_32x36_2clk.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-15T00:50:17" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8449944117490A53CFE9CD2127BE2AA" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
new file mode 100644
index 000000000..b8c69a9f7
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_32x36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_32x36_2clk.gise
+fifo_xlnx_32x36_2clk.ngc
+fifo_xlnx_32x36_2clk.v
+fifo_xlnx_32x36_2clk.veo
+fifo_xlnx_32x36_2clk.xco
+fifo_xlnx_32x36_2clk.xise
+fifo_xlnx_32x36_2clk_flist.txt
+fifo_xlnx_32x36_2clk_readme.txt
+fifo_xlnx_32x36_2clk_xmdf.tcl
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
new file mode 100644
index 000000000..8ab5679fd
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
@@ -0,0 +1,46 @@
+The following files were generated for 'fifo_xlnx_32x36_2clk' in directory
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+ Please see the core data sheet.
+
+fifo_xlnx_32x36_2clk.gise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_32x36_2clk.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_32x36_2clk.v:
+ Unisim Verilog file containing the information required to simulate
+ the module.
+
+fifo_xlnx_32x36_2clk.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_32x36_2clk.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_32x36_2clk.xise:
+ ISE Project Navigator support file. This is a generated file and should
+ not be edited directly.
+
+fifo_xlnx_32x36_2clk_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_32x36_2clk_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+fifo_xlnx_32x36_2clk_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..ec9426357
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_32x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_32x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk
+}
+# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index 2af59a75d..2a8d57448 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -18,7 +18,7 @@
//`define NO_EXT_FIFO
module ext_fifo
- #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
+ #(parameter INT_WIDTH=36,EXT_WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
(
input int_clk,
input ext_clk,
@@ -44,34 +44,29 @@ module ext_fifo
wire [EXT_WIDTH-1:0] write_data;
wire [EXT_WIDTH-1:0] read_data;
- wire full1, empty1;
- wire almost_full2, full2, empty2;
+ wire full1, empty1;
+ wire almost_full2, full2, empty2;
wire [INT_WIDTH-1:0] data_to_fifo;
wire [INT_WIDTH-1:0] data_from_fifo;
wire [FIFO_DEPTH-1:0] capacity;
-
+ wire space_avail;
+ wire data_avail;
+
+ // These next 2 lines here purely because ICARUS is crap at handling generate statements.
+ // Empirically this has been determined to make simulations work.
+ wire read_input_fifo = space_avail & ~empty1;
+ wire write_output_fifo = data_avail;
- // FIFO buffers data from UDP engine into external FIFO clock domain.
- fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
- .rst(rst),
- .wr_clk(int_clk),
- .rd_clk(ext_clk),
- .din(datain), // Bus [35 : 0]
- .wr_en(src_rdy_i),
- .rd_en(space_avail&~empty1),
- .dout(write_data), // Bus [17 : 0]
- .full(full1),
- .empty(empty1));
-
- assign dst_rdy_o = ~full1;
+ assign src_rdy_o = ~empty2;
+ assign dst_rdy_o = ~full1;
`ifdef NO_EXT_FIFO
- assign space_avail = ~full2;
- assign data_avail = ~empty1;
- assign read_data = write_data;
+ assign space_avail = ~full2;
+ assign data_avail = ~empty1;
+ assign read_data = write_data;
`else
- // External FIFO running at ext clock rate and 18 bit width.
+ // External FIFO running at ext clock rate and 18 or 36 bit width.
nobl_fifo #(.WIDTH(EXT_WIDTH),.RAM_DEPTH(RAM_DEPTH),.FIFO_DEPTH(FIFO_DEPTH))
nobl_fifo_i1
(
@@ -95,22 +90,67 @@ module ext_fifo
.capacity(capacity)
);
`endif // !`ifdef NO_EXT_FIFO
+
-
- // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
- fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
- .rst(rst),
- .wr_clk(ext_clk),
- .rd_clk(int_clk),
- .din(read_data), // Bus [17 : 0]
- .wr_en(data_avail),
- .rd_en(dst_rdy_i),
- .dout(dataout), // Bus [35 : 0]
- .full(full2),
- .prog_full(almost_full2),
- .empty(empty2));
- assign src_rdy_o = ~empty2;
+ generate
+ if (EXT_WIDTH == 18 && INT_WIDTH == 36) begin: fifo_g1
+ // FIFO buffers data from UDP engine into external FIFO clock domain.
+ fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
+ .rst(rst),
+ .wr_clk(int_clk),
+ .rd_clk(ext_clk),
+ .din(datain), // Bus [35 : 0]
+ .wr_en(src_rdy_i),
+ .rd_en(read_input_fifo),
+ .dout(write_data), // Bus [17 : 0]
+ .full(full1),
+ .empty(empty1));
+
+ // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+ fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
+ .rst(rst),
+ .wr_clk(ext_clk),
+ .rd_clk(int_clk),
+ .din(read_data), // Bus [17 : 0]
+ .wr_en(write_output_fifo),
+ .rd_en(dst_rdy_i),
+ .dout(dataout), // Bus [35 : 0]
+ .full(full2),
+ .prog_full(almost_full2),
+ .empty(empty2));
+ end // block: fifo_g1
+ else if (EXT_WIDTH == 36 && INT_WIDTH == 36) begin: fifo_g1
+ // FIFO buffers data from UDP engine into external FIFO clock domain.
+ fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i1 (
+ .rst(rst),
+ .wr_clk(int_clk),
+ .rd_clk(ext_clk),
+ .din(datain), // Bus [35 : 0]
+ .wr_en(src_rdy_i),
+ .rd_en(read_input_fifo),
+ .dout(write_data), // Bus [35 : 0]
+ .full(full1),
+ .empty(empty1));
+
+ // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
+ fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 (
+ .rst(rst),
+ .wr_clk(ext_clk),
+ .rd_clk(int_clk),
+ .din(read_data), // Bus [35 : 0]
+ .wr_en(write_output_fifo),
+ .rd_en(dst_rdy_i),
+ .dout(dataout), // Bus [35 : 0]
+ .full(full2),
+ .empty(empty2),
+ .prog_full(almost_full2));
+
+ end
+ endgenerate
+
+
+
always @ (posedge int_clk)
debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
@@ -118,6 +158,7 @@ module ext_fifo
debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
always@ (posedge ext_clk)
-// debug2[31:0] <= {write_data[15:0],read_data[15:0]};
- debug2[31:0] <= 0;
+ // debug2[31:0] <= {write_data[15:0],read_data[15:0]};
+ debug2[31:0] <= 0;
+
endmodule // ext_fifo
diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh
index dcfede37a..dcfede37a 100644..100755
--- a/usrp2/extramfifo/ext_fifo_tb.sh
+++ b/usrp2/extramfifo/ext_fifo_tb.sh
diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v
index 0eda89769..5f4e28719 100644
--- a/usrp2/extramfifo/ext_fifo_tb.v
+++ b/usrp2/extramfifo/ext_fifo_tb.v
@@ -1,18 +1,31 @@
`timescale 1ns / 1ps
-`define INT_WIDTH 36
-`define EXT_WIDTH 18
-`define RAM_DEPTH 19
-`define FIFO_DEPTH 8
-`define DUMP_VCD_FULL
-
-module ext_fifo_tb();
+//`define USRP2
+`define USRP2PLUS
+`ifdef USRP2
+ `define INT_WIDTH 36
+ `define EXT_WIDTH 18
+ `define RAM_DEPTH 19
+ `define FIFO_DEPTH 8
+ `define DUMP_VCD_FULL
+ `define INT_CLK_PERIOD 5
+ `define EXT_CLK_PERIOD 4
+`elsif USRP2PLUS
+ `define INT_WIDTH 36
+ `define EXT_WIDTH 36
+ `define RAM_DEPTH 18
+ `define FIFO_DEPTH 8
+ `define DUMP_VCD_FULL
+ `define INT_CLK_PERIOD 5
+ `define EXT_CLK_PERIOD 5
+`endif // `ifdef USRP2
+
+module ext_fifo_tb();
+
reg int_clk;
reg ext_clk;
reg rst;
-
-
wire [`EXT_WIDTH-1:0] RAM_D_pi;
wire [`EXT_WIDTH-1:0] RAM_D_po;
@@ -33,7 +46,6 @@ module ext_fifo_tb();
reg dst_rdy_i;
integer ether_frame;
-
// Clocks
// Int clock is 100MHz
// Ext clock is 125MHz
@@ -47,10 +59,10 @@ module ext_fifo_tb();
end
always
- #5 int_clk <= ~int_clk;
+ #(`INT_CLK_PERIOD/2) int_clk <= ~int_clk;
always
- #4 ext_clk <= ~ext_clk;
+ #(`EXT_CLK_PERIOD/2) ext_clk <= ~ext_clk;
initial
begin
@@ -270,7 +282,7 @@ module ext_fifo_tb();
//
generate
- for (i=0;i<18;i=i+1)
+ for (i=0;i<`EXT_WIDTH;i=i+1)
begin : gen_RAM_D_IO
IOBUF #(
@@ -309,28 +321,53 @@ module ext_fifo_tb();
assign #2 RAM_A_ext = RAM_A;
-
- idt71v65603s150 idt71v65603s150_i1
- (
- .A(RAM_A_ext[17:0]),
- .adv_ld_(RAM_LDn_ext), // advance (high) / load (low)
- .bw1_(1'b0),
- .bw2_(1'b0),
- .bw3_(1'b1),
- .bw4_(1'b1), // byte write enables (low)
- .ce1_(RAM_CE1n_ext),
- .ce2(1'b1),
- .ce2_(1'b0), // chip enables
- .cen_(RAM_CENn_ext), // clock enable (low)
- .clk(ext_clk), // clock
- .IO({RAM_D[16:9],RAM_D[7:0]}),
- .IOP({RAM_D[17],RAM_D[8]}), // data bus
- .lbo_(1'b0), // linear burst order (low)
- .oe_(RAM_OEn_ext), // output enable (low)
- .r_w_(RAM_WEn_ext)
- ); // read (high) / write (low)
+ generate
+ if (`EXT_WIDTH==18) begin: ram_tb_g1
+ idt71v65603s150 idt71v65603s150_i1
+ (
+ .A(RAM_A_ext[17:0]),
+ .adv_ld_(RAM_LDn_ext), // advance (high) / load (low)
+ .bw1_(1'b0),
+ .bw2_(1'b0),
+ .bw3_(1'b1),
+ .bw4_(1'b1), // byte write enables (low)
+ .ce1_(RAM_CE1n_ext),
+ .ce2(1'b1),
+ .ce2_(1'b0), // chip enables
+ .cen_(RAM_CENn_ext), // clock enable (low)
+ .clk(ext_clk), // clock
+ .IO({RAM_D[16:9],RAM_D[7:0]}),
+ .IOP({RAM_D[17],RAM_D[8]}), // data bus
+ .lbo_(1'b0), // linear burst order (low)
+ .oe_(RAM_OEn_ext), // output enable (low)
+ .r_w_(RAM_WEn_ext)
+ ); // read (high) / write (low)
+ end // block: ram_tb_g1
+ else if (`EXT_WIDTH==36) begin: ram_tb_g1
+ idt71v65603s150 idt71v65603s150_i1
+ (
+ .A(RAM_A_ext[17:0]),
+ .adv_ld_(RAM_LDn_ext), // advance (high) / load (low)
+ .bw1_(1'b0),
+ .bw2_(1'b0),
+ .bw3_(1'b0),
+ .bw4_(1'b0), // byte write enables (low)
+ .ce1_(RAM_CE1n_ext),
+ .ce2(1'b1),
+ .ce2_(1'b0), // chip enables
+ .cen_(RAM_CENn_ext), // clock enable (low)
+ .clk(ext_clk), // clock
+ .IO(RAM_D[31:0]),
+ .IOP(RAM_D[35:32]), // data bus
+ .lbo_(1'b0), // linear burst order (low)
+ .oe_(RAM_OEn_ext), // output enable (low)
+ .r_w_(RAM_WEn_ext)
+ ); // read (high) / write (low)
+ end // block: ram_tb_g1
+ endgenerate
+
/* -----\/----- EXCLUDED -----\/-----
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v
index 4c009d980..0b63768fc 100644
--- a/usrp2/extramfifo/nobl_fifo.v
+++ b/usrp2/extramfifo/nobl_fifo.v
@@ -70,26 +70,27 @@ module nobl_fifo
// Simple NoBL SRAM interface, 4 cycle read latency.
// Read/Write arbitration via temprary application of empty/full flags.
//
- nobl_if nobl_if_i1
- (
- .clk(clk),
- .rst(rst),
- .RAM_D_pi(RAM_D_pi),
- .RAM_D_po(RAM_D_po),
- .RAM_D_poe(RAM_D_poe),
- .RAM_A(RAM_A),
- .RAM_WEn(RAM_WEn),
- .RAM_CENn(RAM_CENn),
- .RAM_LDn(RAM_LDn),
- .RAM_OEn(RAM_OEn),
- .RAM_CE1n(RAM_CE1n),
- .address(address),
- .data_out(write_data),
- .data_in(read_data),
- .data_in_valid(data_avail),
- .write(write),
- .enable(enable)
- );
+ nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))
+ nobl_if_i1
+ (
+ .clk(clk),
+ .rst(rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .address(address),
+ .data_out(write_data),
+ .data_in(read_data),
+ .data_in_valid(data_avail),
+ .write(write),
+ .enable(enable)
+ );
diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile
index 23eb8908e..c38bd3ec1 100644
--- a/usrp2/top/u2plus/Makefile
+++ b/usrp2/top/u2plus/Makefile
@@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
##################################################
# Project Properties
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index aee9e57bf..3717b3d91 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -414,3 +414,11 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
+
+NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+
+
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 90dbe9d55..55b5bd8f4 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -216,7 +216,49 @@ module u2plus
BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
-
+
+ wire RAM_CLK_buf;
+ wire clk100_ext;
+ wire clk100_ext_buf;
+
+ DCM DCM_INST1 (.CLKFB(RAM_CLK_buf),
+ .CLKIN(clk_fpga),
+ .DSSEN(1'b0),
+ .PSCLK(1'b0),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .RST(1'b0),
+ .CLK0(clk100_ext) );
+ defparam DCM_INST1.CLK_FEEDBACK = "1X";
+ defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
+ defparam DCM_INST1.CLKFX_DIVIDE = 1;
+ defparam DCM_INST1.CLKFX_MULTIPLY = 4;
+ defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_INST1.CLKIN_PERIOD = 10.000;
+ defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED";
+ defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_INST1.FACTORY_JF = 16'h8080;
+ defparam DCM_INST1.PHASE_SHIFT = -64;
+ defparam DCM_INST1.STARTUP_WAIT = "FALSE";
+
+ IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK),
+ .O(RAM_CLK_buf));
+
+ BUFG clk100_ext_buf_i1 (.I(clk100_ext),
+ .O(clk100_ext_buf));
+
+ OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+ .C0(clk100_ext_buf),
+ .C1(~clk100_ext_buf),
+ .CE(1'b1),
+ .D0(1'b1),
+ .D1(1'b0),
+ .R(1'b0),
+ .S(1'b0));
+
// I2C -- Don't use external transistors for open drain, the FPGA implements this
IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
@@ -299,6 +341,36 @@ module u2plus
.S(0) // Synchronous preset input
);
*/
+
+
+ //
+ // Instantiate IO for Bidirectional bus to SRAM
+ //
+ wire [35:0] RAM_D_pi;
+ wire [35:0] RAM_D_po;
+ wire RAM_D_poe;
+
+ genvar i;
+
+ generate
+ for (i=0;i<36;i=i+1)
+ begin : gen_RAM_D_IO
+
+ IOBUF #(
+ .DRIVE(12),
+ .IOSTANDARD("LVCMOS25"),
+ .SLEW("FAST")
+ )
+ RAM_D_i (
+ .O(RAM_D_pi[i]),
+ .I(RAM_D_po[i]),
+ .IO(RAM_D[i]),
+ .T(RAM_D_poe)
+ );
+ end // block: gen_RAM_D_IO
+ endgenerate
+
+
wire [15:0] dac_a_int, dac_b_int;
// DAC A and B are swapped in schematic to facilitate clean layout
@@ -377,11 +449,12 @@ module u2plus
.sen_rx_dac (SEN_RX_DAC),
.io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]),
- .RAM_D (RAM_D),
+ .RAM_D_po (RAM_D_po),
+ .RAM_D_pi (RAM_D_pi),
+ .RAM_D_poe (RAM_D_poe),
.RAM_A (RAM_A),
.RAM_CE1n (RAM_CE1n),
.RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
.RAM_WEn (RAM_WEn),
.RAM_OEn (RAM_OEn),
.RAM_LDn (RAM_LDn),
@@ -398,6 +471,8 @@ module u2plus
);
assign RAM_ZZ = 1;
- assign RAM_BWn = 4'b1111;
+ // Byte Writes are qualified by the global write enable
+ // Always do 36bit operations to extram.
+ assign RAM_BWn = 4'b0000;
endmodule // u2plus
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 4378436a6..9b177390a 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -110,11 +110,12 @@ module u2plus_core
inout [15:0] io_rx,
// External RAM
- inout [35:0] RAM_D,
+ input [35:0] RAM_D_pi,
+ output [35:0] RAM_D_po,
+ output RAM_D_poe,
output [20:0] RAM_A,
output RAM_CE1n,
output RAM_CENn,
- output RAM_CLK,
output RAM_WEn,
output RAM_OEn,
output RAM_LDn,
@@ -606,11 +607,41 @@ module u2plus_core
wire tx_src_rdy, tx_dst_rdy;
wire [31:0] debug_vt;
+/* -----\/----- EXCLUDED -----\/-----
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
-
+ -----/\----- EXCLUDED -----/\----- */
+ // External and internal clock run at 100MHz for USRP2+ because ext RAM is 36bits wide
+ // and provides ample bandwidth.
+ assign RAM_A[20:18] = 3'b0;
+
+ ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18))
+ ext_fifo_i1
+ (
+ .int_clk(dsp_clk),
+ .ext_clk(dsp_clk),
+ .rst(dsp_rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A[17:0]),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
+ .src_rdy_i(rd1_ready_o), // WRITE
+ .dst_rdy_o(rd1_ready_i), // not FULL
+ .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
+ .src_rdy_o(tx_src_rdy), // not EMPTY
+ .dst_rdy_i(tx_dst_rdy),
+ .debug(debug_extfifo),
+ .debug2(debug_extfifo2)
+ );
+
vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
.REPORT_ERROR(1), .PROT_ENG_FLAGS(1))
vita_tx_chain
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 20:20:21 +0000