376 files changed, 4156 insertions, 4484 deletions

diff --git a/firmware/README b/firmware/README
index a010493c8..251486955 100644
--- a/firmware/README
+++ b/firmware/README
@@ -1,4 +1,6 @@
-This is a placeholder for the firmware code (microblaze and 8051).
+########################################################################
+# Firmware for USRP devices
+########################################################################
 
-The layout should have a common library of source and header files.
-Each usrp-like will have its own device-specific libs and apps.
+fx2 - firmware for USRP1
+zpu - firmware for USRP2 and N Series
diff --git a/firmware/microblaze/.gitignore b/firmware/microblaze/.gitignore
deleted file mode 100644
index e867fe87c..000000000
--- a/firmware/microblaze/.gitignore
+++ /dev/null
@@ -1,46 +0,0 @@
-/*-stamp
-/*.a
-/*.bin
-/*.dump
-/*.log
-/*.rom
-/.deps
-/*.guess
-/*.sub
-/Makefile
-/Makefile.in
-/aclocal.m4
-/autom4te.cache
-/blink_leds
-/blink_leds2
-/build
-/compile
-/config.h
-/config.h.in
-/config.log
-/config.status
-/configure
-/depcomp
-/eth_test
-/gen_eth_packets
-/ibs_rx_test
-/ibs_tx_test
-/install-sh
-/libtool
-/ltmain.sh
-/missing
-/py-compile
-/rcv_eth_packets
-/run_tests.sh
-/stamp-h1
-/test1
-/test_phy_comm
-/timer_test
-/buf_ram_test
-/buf_ram_zero
-/hello
-/configure.lineno
-/configure.guess
-/configure.sub
-*.deps
-*.o
diff --git a/firmware/microblaze/COPYING b/firmware/microblaze/COPYING
deleted file mode 100644
index 94a9ed024..000000000
--- a/firmware/microblaze/COPYING
+++ /dev/null
@@ -1,674 +0,0 @@
-                    GNU GENERAL PUBLIC LICENSE
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-combined work, and to convey the resulting work.  The terms of this
-License will continue to apply to the part which is the covered work,
-but the special requirements of the GNU Affero General Public License,
-section 13, concerning interaction through a network will apply to the
-combination as such.
-
-  14. Revised Versions of this License.
-
-  The Free Software Foundation may publish revised and/or new versions of
-the GNU General Public License from time to time.  Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-  Each version is given a distinguishing version number.  If the
-Program specifies that a certain numbered version of the GNU General
-Public License "or any later version" applies to it, you have the
-option of following the terms and conditions either of that numbered
-version or of any later version published by the Free Software
-Foundation.  If the Program does not specify a version number of the
-GNU General Public License, you may choose any version ever published
-by the Free Software Foundation.
-
-  If the Program specifies that a proxy can decide which future
-versions of the GNU General Public License can be used, that proxy's
-public statement of acceptance of a version permanently authorizes you
-to choose that version for the Program.
-
-  Later license versions may give you additional or different
-permissions.  However, no additional obligations are imposed on any
-author or copyright holder as a result of your choosing to follow a
-later version.
-
-  15. Disclaimer of Warranty.
-
-  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
-APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
-HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
-OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
-IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
-ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
-  16. Limitation of Liability.
-
-  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
-THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
-GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
-USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
-DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
-PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
-EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGES.
-
-  17. Interpretation of Sections 15 and 16.
-
-  If the disclaimer of warranty and limitation of liability provided
-above cannot be given local legal effect according to their terms,
-reviewing courts shall apply local law that most closely approximates
-an absolute waiver of all civil liability in connection with the
-Program, unless a warranty or assumption of liability accompanies a
-copy of the Program in return for a fee.
-
-                     END OF TERMS AND CONDITIONS
-
-            How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-state the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software: you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation, either version 3 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-Also add information on how to contact you by electronic and paper mail.
-
-  If the program does terminal interaction, make it output a short
-notice like this when it starts in an interactive mode:
-
-    <program>  Copyright (C) <year>  <name of author>
-    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
-  You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
-<http://www.gnu.org/licenses/>.
-
-  The GNU General Public License does not permit incorporating your program
-into proprietary programs.  If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.  But first, please read
-<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/firmware/microblaze/ChangeLog b/firmware/microblaze/ChangeLog
deleted file mode 100644
index 8b1378917..000000000
--- a/firmware/microblaze/ChangeLog
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/firmware/microblaze/INSTALL b/firmware/microblaze/INSTALL
deleted file mode 100644
index 5458714e1..000000000
--- a/firmware/microblaze/INSTALL
+++ /dev/null
@@ -1,234 +0,0 @@
-Installation Instructions
-*************************
-
-Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005,
-2006 Free Software Foundation, Inc.
-
-This file is free documentation; the Free Software Foundation gives
-unlimited permission to copy, distribute and modify it.
-
-Basic Installation
-==================
-
-Briefly, the shell commands `./configure; make; make install' should
-configure, build, and install this package.  The following
-more-detailed instructions are generic; see the `README' file for
-instructions specific to this package.
-
-   The `configure' shell script attempts to guess correct values for
-various system-dependent variables used during compilation.  It uses
-those values to create a `Makefile' in each directory of the package.
-It may also create one or more `.h' files containing system-dependent
-definitions.  Finally, it creates a shell script `config.status' that
-you can run in the future to recreate the current configuration, and a
-file `config.log' containing compiler output (useful mainly for
-debugging `configure').
-
-   It can also use an optional file (typically called `config.cache'
-and enabled with `--cache-file=config.cache' or simply `-C') that saves
-the results of its tests to speed up reconfiguring.  Caching is
-disabled by default to prevent problems with accidental use of stale
-cache files.
-
-   If you need to do unusual things to compile the package, please try
-to figure out how `configure' could check whether to do them, and mail
-diffs or instructions to the address given in the `README' so they can
-be considered for the next release.  If you are using the cache, and at
-some point `config.cache' contains results you don't want to keep, you
-may remove or edit it.
-
-   The file `configure.ac' (or `configure.in') is used to create
-`configure' by a program called `autoconf'.  You need `configure.ac' if
-you want to change it or regenerate `configure' using a newer version
-of `autoconf'.
-
-The simplest way to compile this package is:
-
-  1. `cd' to the directory containing the package's source code and type
-     `./configure' to configure the package for your system.
-
-     Running `configure' might take a while.  While running, it prints
-     some messages telling which features it is checking for.
-
-  2. Type `make' to compile the package.
-
-  3. Optionally, type `make check' to run any self-tests that come with
-     the package.
-
-  4. Type `make install' to install the programs and any data files and
-     documentation.
-
-  5. You can remove the program binaries and object files from the
-     source code directory by typing `make clean'.  To also remove the
-     files that `configure' created (so you can compile the package for
-     a different kind of computer), type `make distclean'.  There is
-     also a `make maintainer-clean' target, but that is intended mainly
-     for the package's developers.  If you use it, you may have to get
-     all sorts of other programs in order to regenerate files that came
-     with the distribution.
-
-Compilers and Options
-=====================
-
-Some systems require unusual options for compilation or linking that the
-`configure' script does not know about.  Run `./configure --help' for
-details on some of the pertinent environment variables.
-
-   You can give `configure' initial values for configuration parameters
-by setting variables in the command line or in the environment.  Here
-is an example:
-
-     ./configure CC=c99 CFLAGS=-g LIBS=-lposix
-
-   *Note Defining Variables::, for more details.
-
-Compiling For Multiple Architectures
-====================================
-
-You can compile the package for more than one kind of computer at the
-same time, by placing the object files for each architecture in their
-own directory.  To do this, you can use GNU `make'.  `cd' to the
-directory where you want the object files and executables to go and run
-the `configure' script.  `configure' automatically checks for the
-source code in the directory that `configure' is in and in `..'.
-
-   With a non-GNU `make', it is safer to compile the package for one
-architecture at a time in the source code directory.  After you have
-installed the package for one architecture, use `make distclean' before
-reconfiguring for another architecture.
-
-Installation Names
-==================
-
-By default, `make install' installs the package's commands under
-`/usr/local/bin', include files under `/usr/local/include', etc.  You
-can specify an installation prefix other than `/usr/local' by giving
-`configure' the option `--prefix=PREFIX'.
-
-   You can specify separate installation prefixes for
-architecture-specific files and architecture-independent files.  If you
-pass the option `--exec-prefix=PREFIX' to `configure', the package uses
-PREFIX as the prefix for installing programs and libraries.
-Documentation and other data files still use the regular prefix.
-
-   In addition, if you use an unusual directory layout you can give
-options like `--bindir=DIR' to specify different values for particular
-kinds of files.  Run `configure --help' for a list of the directories
-you can set and what kinds of files go in them.
-
-   If the package supports it, you can cause programs to be installed
-with an extra prefix or suffix on their names by giving `configure' the
-option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
-
-Optional Features
-=================
-
-Some packages pay attention to `--enable-FEATURE' options to
-`configure', where FEATURE indicates an optional part of the package.
-They may also pay attention to `--with-PACKAGE' options, where PACKAGE
-is something like `gnu-as' or `x' (for the X Window System).  The
-`README' should mention any `--enable-' and `--with-' options that the
-package recognizes.
-
-   For packages that use the X Window System, `configure' can usually
-find the X include and library files automatically, but if it doesn't,
-you can use the `configure' options `--x-includes=DIR' and
-`--x-libraries=DIR' to specify their locations.
-
-Specifying the System Type
-==========================
-
-There may be some features `configure' cannot figure out automatically,
-but needs to determine by the type of machine the package will run on.
-Usually, assuming the package is built to be run on the _same_
-architectures, `configure' can figure that out, but if it prints a
-message saying it cannot guess the machine type, give it the
-`--build=TYPE' option.  TYPE can either be a short name for the system
-type, such as `sun4', or a canonical name which has the form:
-
-     CPU-COMPANY-SYSTEM
-
-where SYSTEM can have one of these forms:
-
-     OS KERNEL-OS
-
-   See the file `config.sub' for the possible values of each field.  If
-`config.sub' isn't included in this package, then this package doesn't
-need to know the machine type.
-
-   If you are _building_ compiler tools for cross-compiling, you should
-use the option `--target=TYPE' to select the type of system they will
-produce code for.
-
-   If you want to _use_ a cross compiler, that generates code for a
-platform different from the build platform, you should specify the
-"host" platform (i.e., that on which the generated programs will
-eventually be run) with `--host=TYPE'.
-
-Sharing Defaults
-================
-
-If you want to set default values for `configure' scripts to share, you
-can create a site shell script called `config.site' that gives default
-values for variables like `CC', `cache_file', and `prefix'.
-`configure' looks for `PREFIX/share/config.site' if it exists, then
-`PREFIX/etc/config.site' if it exists.  Or, you can set the
-`CONFIG_SITE' environment variable to the location of the site script.
-A warning: not all `configure' scripts look for a site script.
-
-Defining Variables
-==================
-
-Variables not defined in a site shell script can be set in the
-environment passed to `configure'.  However, some packages may run
-configure again during the build, and the customized values of these
-variables may be lost.  In order to avoid this problem, you should set
-them in the `configure' command line, using `VAR=value'.  For example:
-
-     ./configure CC=/usr/local2/bin/gcc
-
-causes the specified `gcc' to be used as the C compiler (unless it is
-overridden in the site shell script).
-
-Unfortunately, this technique does not work for `CONFIG_SHELL' due to
-an Autoconf bug.  Until the bug is fixed you can use this workaround:
-
-     CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash
-
-`configure' Invocation
-======================
-
-`configure' recognizes the following options to control how it operates.
-
-`--help'
-`-h'
-     Print a summary of the options to `configure', and exit.
-
-`--version'
-`-V'
-     Print the version of Autoconf used to generate the `configure'
-     script, and exit.
-
-`--cache-file=FILE'
-     Enable the cache: use and save the results of the tests in FILE,
-     traditionally `config.cache'.  FILE defaults to `/dev/null' to
-     disable caching.
-
-`--config-cache'
-`-C'
-     Alias for `--cache-file=config.cache'.
-
-`--quiet'
-`--silent'
-`-q'
-     Do not print messages saying which checks are being made.  To
-     suppress all normal output, redirect it to `/dev/null' (any error
-     messages will still be shown).
-
-`--srcdir=DIR'
-     Look for the package's source code in directory DIR.  Usually
-     `configure' can determine that directory automatically.
-
-`configure' also accepts some other, not widely useful, options.  Run
-`configure --help' for more details.
-
diff --git a/firmware/microblaze/Makefile.am b/firmware/microblaze/Makefile.am
deleted file mode 100644
index 52fa649c2..000000000
--- a/firmware/microblaze/Makefile.am
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# Copyright 2007,2008 Free Software Foundation, Inc.
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(top_srcdir)/Makefile.common
-
-EXTRA_DIST = \
-	u2_flash_tool
-
-SUBDIRS = \
-	usrp2 \
-	usrp2p \
-	usrp2p/bootloader
-
diff --git a/firmware/microblaze/Makefile.common b/firmware/microblaze/Makefile.common
deleted file mode 100644
index 4e726edab..000000000
--- a/firmware/microblaze/Makefile.common
+++ /dev/null
@@ -1,88 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# Copyright 2007 Free Software Foundation, Inc.
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(top_srcdir)/lib/Makefile.inc
-
-########################################################################
-# lwIP header include dirs
-########################################################################
-LWIPDIR = $(top_srcdir)/lwip/lwip-1.3.1
-
-LWIP_INCLUDES = \
-	-I$(top_srcdir)/lwip \
-	-I$(top_srcdir)/lwip_port \
-	-I$(LWIPDIR)/src/include \
-	-I$(LWIPDIR)/src/include/ipv4
-
-########################################################################
-# misc flags for the mb-gcc compiler
-########################################################################
-MBGCC_CFLAGS = \
-	--std=gnu99 -Wall -Werror-implicit-function-declaration \
-	-mxl-soft-div -msoft-float -mxl-soft-mul -mxl-barrel-shift
-
-########################################################################
-# define for the hal io (FIXME move?)
-########################################################################
-#HAL_IO = -DHAL_IO_USES_DBOARD_PINS 
-HAL_IO = -DHAL_IO_USES_UART 
-
-########################################################################
-# common cflags and ldflags
-########################################################################
-COMMON_CFLAGS = \
-	-I$(top_srcdir)/../../host/lib/usrp \
-	-I$(top_srcdir)/lib \
-	$(MBGCC_CFLAGS) \
-	$(LWIP_INCLUDES) \
-	$(HAL_IO)
-
-COMMON_LFLAGS = \
-	-Wl,-Map -Wl,$(@:.elf=.map)
-
-########################################################################
-# Common stuff for building top level microblaze images
-########################################################################
-#we use COMMON_IHX_ARGS to relocate the reset and interrupt vectors to
-#just below the start of code. upon creating the BIN, any leading padding
-#is thrown out, so the .bin file is valid for uploading to USRP2P. this 
-#does not affect USRP2 because the USRP2 already starts at 0x0000, and
-#because the relocate_args are not defined for USRP2's Makefile.am.
-.elf.bin:
-	$(MB_OBJCOPY) -O binary $(RELOCATE_ARGS) $< $@
-
-.elf.dump:
-	$(MB_OBJDUMP) -DSC $< > $@
-
-.bin.rom:
-	$(HEXDUMP) -v -e'1/1 "%.2X\n"' $< > $@
-
-.elf.ihx:
-	$(MB_OBJCOPY) -O ihex $(RELOCATE_ARGS) $< $@
-
-_generated_from_elf = \
-	$(noinst_PROGRAMS:.elf=.map) \
-	$(noinst_PROGRAMS:.elf=.bin) \
-	$(noinst_PROGRAMS:.elf=.dump) \
-	$(noinst_PROGRAMS:.elf=.rom) \
-	$(noinst_PROGRAMS:.elf=.ihx)
-
-noinst_DATA = $(_generated_from_elf)
-
-MOSTLYCLEANFILES = $(_generated_from_elf)
diff --git a/firmware/microblaze/NEWS b/firmware/microblaze/NEWS
deleted file mode 100644
index e69de29bb..000000000
--- a/firmware/microblaze/NEWS
+++ /dev/null
diff --git a/firmware/microblaze/README b/firmware/microblaze/README
deleted file mode 100644
index 1479ffe1f..000000000
--- a/firmware/microblaze/README
+++ /dev/null
@@ -1,3 +0,0 @@
-./bootstrap
-./configure --host=mb
-make
diff --git a/firmware/microblaze/apps/cruft/Makefile.am b/firmware/microblaze/apps/cruft/Makefile.am
deleted file mode 100644
index a4f79935b..000000000
--- a/firmware/microblaze/apps/cruft/Makefile.am
+++ /dev/null
@@ -1,82 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# Copyright 2007,2008 Free Software Foundation, Inc.
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(top_srcdir)/Makefile.common
-
-LDADD = $(top_srcdir)/lib/libu2fw.a
-
-AM_CFLAGS += -I$(top_srcdir)/../../host/lib/usrp
-
-noinst_PROGRAMS = txrx_uhd.elf
-
-#	blink_leds \
-#	blink_leds2 \
-#	buf_ram_test \
-#	burn_dbsrx_eeprom \
-#	can_i_sub \
-#	echo \
-#	hello \
-#	read_dbids \
-#	set_hw_rev \
-#	test1 \
-#	test_db_spi \
-#	test_i2c \
-#	test_sd \
-#	test_ram \
-#	test_phy_comm \
-#	test_lsadc \
-#	test_lsdac \
-#	timer_test \
-#	txrx \
-#	burnrev30 \
-#	burnrev31 \
-#	burnrev40 \
-#	sd_gentest \
-#	sd_bounce
-#
-
-#nononono =  \
-#	eth_serdes \
-#	gen_eth_packets \
-#	rcv_eth_packets \
-#	tx_standalone \
-#	factory_test \
-#	serdes_txrx \
-#	mimo_tx \
-#	mimo_tx_slave \
-#	ibs_rx_test \
-#	ibs_tx_test
-
-# tx_drop_SOURCES = tx_drop.c app_common.c
-# tx_drop_rate_limited_SOURCES = tx_drop_rate_limited.c app_common.c
-# tx_drop2_SOURCES = tx_drop2.c app_common.c
-txrx_uhd_elf_SOURCES = txrx_uhd.c
-# app_common_v2.c
-#factory_test_SOURCES = factory_test.c app_common_v2.c
-#eth_serdes_SOURCES = eth_serdes.c app_passthru_v2.c
-#serdes_txrx_SOURCES = serdes_txrx.c app_common_v2.c
-#mimo_tx_SOURCES = mimo_tx.c mimo_app_common_v2.c
-#mimo_tx_slave_SOURCES = mimo_tx_slave.c app_common_v2.c
-
-#noinst_HEADERS = \
-#        app_common_v2.h \
-#        app_passthru_v2.h \
-#        mimo_app_common_v2.h
-#
-
diff --git a/firmware/microblaze/bootstrap b/firmware/microblaze/bootstrap
deleted file mode 100755
index 26987b0ec..000000000
--- a/firmware/microblaze/bootstrap
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/sh
-#
-# Copyright 2010 Ettus Research LLC
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-rm -rf *.cache
-rm -rf libusrp2/.deps
-rm -rf libusrp2p/.deps
-
-aclocal
-autoconf
-libtoolize --automake
-automake --add-missing --gnu --warnings=all
diff --git a/firmware/microblaze/configure.ac b/firmware/microblaze/configure.ac
deleted file mode 100644
index f6986f2dd..000000000
--- a/firmware/microblaze/configure.ac
+++ /dev/null
@@ -1,54 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-##################################################
-## Setup Autotools
-##################################################
-AC_PREREQ(2.60)
-AC_INIT
-AM_INIT_AUTOMAKE(uhd-mb, 0)
-
-##################################################
-## Setup Compiler
-##################################################
-dnl Fix 2.64 cross compile detection for AVR and RTEMS
-dnl by not trying to compile fopen.
-m4_if(m4_defn([m4_PACKAGE_VERSION]), [2.64],
-  [m4_foreach([_GCC_LANG], [C, C++, Fortran, Fortran 77],
-     [m4_define([_AC_LANG_IO_PROGRAM(]_GCC_LANG[)], m4_defn([AC_LANG_PROGRAM(]_GCC_LANG[)]))])]) 
-
-AC_PROG_CC([mb-gcc])
-AM_PROG_CC_C_O
-LT_INIT
-
-##################################################
-## Setup Tools
-##################################################
-AC_PATH_PROG([MB_OBJCOPY], [mb-objcopy])
-AC_PATH_PROG([MB_OBJDUMP], [mb-objdump])
-AC_PATH_PROG([HEXDUMP],    [hexdump])
-
-##################################################
-## Create Files
-##################################################
-AC_CONFIG_FILES([ \
-    Makefile \
-    usrp2p/bootloader/Makefile \
-    usrp2/Makefile \
-    usrp2p/Makefile \
-])
-AC_OUTPUT
diff --git a/firmware/microblaze/lib/Makefile.inc b/firmware/microblaze/lib/Makefile.inc
deleted file mode 100644
index 38c630df4..000000000
--- a/firmware/microblaze/lib/Makefile.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# Copyright 2007 Free Software Foundation, Inc.
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-COMMON_SRCS = \
-	$(top_srcdir)/lib/u2_init.c \
-	$(top_srcdir)/lib/abort.c \
-	$(top_srcdir)/lib/ad9510.c \
-	$(top_srcdir)/lib/bsm12.c \
-	$(top_srcdir)/lib/buffer_pool.c \
-	$(top_srcdir)/lib/clocks.c \
-	$(top_srcdir)/lib/dbsm.c \
-	$(top_srcdir)/lib/eeprom.c \
-	$(top_srcdir)/lib/eth_addrs.c \
-	$(top_srcdir)/lib/eth_mac.c \
-	$(top_srcdir)/lib/_exit.c \
-	$(top_srcdir)/lib/exit.c \
-	$(top_srcdir)/lib/hal_io.c \
-	$(top_srcdir)/lib/hal_uart.c \
-	$(top_srcdir)/lib/i2c.c \
-	$(top_srcdir)/lib/i2c_async.c \
-	$(top_srcdir)/lib/mdelay.c \
-	$(top_srcdir)/lib/memcpy_wa.c \
-	$(top_srcdir)/lib/memset_wa.c \
-	$(top_srcdir)/lib/nonstdio.c \
-	$(top_srcdir)/lib/pic.c \
-	$(top_srcdir)/lib/print_mac_addr.c \
-	$(top_srcdir)/lib/print_rmon_regs.c \
-	$(top_srcdir)/lib/print_buffer.c \
-	$(top_srcdir)/lib/printf.c \
-	$(top_srcdir)/lib/ihex.c \
-	$(top_srcdir)/lib/spi.c \
-	$(top_srcdir)/lib/net_common.c \
-	$(top_srcdir)/lib/arp_cache.c \
-	$(top_srcdir)/lib/banal.c
diff --git a/firmware/microblaze/lib/bsm12.c b/firmware/microblaze/lib/bsm12.c
deleted file mode 100644
index 3f17fe42d..000000000
--- a/firmware/microblaze/lib/bsm12.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2009 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * buffer state machine: 1 input to two outputs
- *
- * Typically used to read packets from the ethernet and then after inspecting,
- * handle the packet in firmware or pass it on to 1 of the 2 buffer destinations.
- */
-
-#ifdef HAVE_CONFIG_H
-#include <config.h>
-#endif
-
-#include "bsm12.h"
-#include "memory_map.h"
-#include "buffer_pool.h"
-#include <stdbool.h>
-#include "nonstdio.h"
-#include <stdlib.h>
-
-typedef enum {
-  BS_EMPTY,
-  BS_FILLING,
-  BS_FULL,
-  BS_EMPTYING,
-} buffer_state_t;
-
-static buffer_state_t buffer_state[NBUFFERS];
-static uint32_t last_send_ctrl[NBUFFERS];
-static int8_t  buffer_target[NBUFFERS];	    // -1, 0 or 1.
-static uint8_t buffer_dst[NBUFFERS];	    // 0 or 1. Valid only when BF_EMPTYING
-
-#define ST_IDLE (-1)
-
-void
-bsm12_init(bsm12_t *sm, int buf0,
-	   const buf_cmd_args_t *recv,
-	   const buf_cmd_args_t *send0,
-	   const buf_cmd_args_t *send1,
-	   bsm12_inspector_t inspect)
-{
-  if (buf0 & 0x3)	// precondition: buf0 % 4 == 0
-    abort();
-
-  sm->buf0 = buf0;
-  sm->running = false;
-  sm->recv_args = *recv;
-  sm->send_args[0] = *send0;
-  sm->send_args[1] = *send1;
-
-  sm->rx_state = ST_IDLE;
-  sm->tx_state[0] = ST_IDLE;
-  sm->tx_state[1] = ST_IDLE;
-
-  sm->inspect = inspect;
-
-  sm->bps_error = BPS_ERROR(buf0 + 0) | BPS_ERROR(buf0 + 1) | BPS_ERROR(buf0 + 2);
-  sm->bps_done  = BPS_DONE(buf0 + 0)  | BPS_DONE(buf0 + 1)  | BPS_DONE(buf0 + 2);
-  sm->bps_error_or_done = sm->bps_error | sm->bps_done;
-
-  // How much to adjust the last_line register.
-  // It's 1 for everything but the ethernet.
-  sm->last_line_adj = recv->port == PORT_ETH ? 3 : 1;
-
-  buffer_state[sm->buf0 + 0] = BS_EMPTY;
-  buffer_state[sm->buf0 + 1] = BS_EMPTY;
-  buffer_state[sm->buf0 + 2] = BS_EMPTY;
-
-  buffer_target[sm->buf0 + 0] = -1;
-  buffer_target[sm->buf0 + 1] = -1;
-  buffer_target[sm->buf0 + 2] = -1;
-
-  for (int i = 0; i < NBUFFERS; i++)
-    sm->next_buf[i] = buf0;
-
-  sm->next_buf[buf0 + 0] = buf0 + 1;
-  sm->next_buf[buf0 + 1] = buf0 + 2;
-  sm->next_buf[buf0 + 2] = buf0 + 0;
-
-  for (int i = 0; i < 3; i++){
-    sm->precomputed_receive_to_buf_ctrl_word[i] =
-      (BPC_READ
-       | BPC_BUFFER(sm->buf0 + i)
-       | BPC_PORT(sm->recv_args.port)
-       | BPC_STEP(1)
-       | BPC_FIRST_LINE(sm->recv_args.first_line)
-       | BPC_LAST_LINE(sm->recv_args.last_line));
-    
-    for (int j = 0; j < 2; j++){
-      sm->precomputed_send_from_buf_ctrl_word[i][j] =
-	(BPC_WRITE
-	 | BPC_BUFFER(sm->buf0 + i)
-	 | BPC_PORT(sm->send_args[j].port)
-	 | BPC_STEP(1)
-	 | BPC_FIRST_LINE(sm->send_args[j].first_line)
-	 | BPC_LAST_LINE(0));		// last line filled in at runtime
-    }
-  }
-}
-
-static inline void
-bsm12_receive_to_buf(bsm12_t *sm, int bufno)
-{
-  buffer_pool_ctrl->ctrl = sm->precomputed_receive_to_buf_ctrl_word[bufno & 0x3];
-}
-
-static inline void
-bsm12_send_from_buf(bsm12_t *sm, int bufno, int dst_idx)
-{
-  dst_idx &= 0x1;
-
-  uint32_t t = 
-    (sm->precomputed_send_from_buf_ctrl_word[bufno & 0x3][dst_idx]
-     | BPC_LAST_LINE(buffer_pool_status->last_line[bufno] - sm->last_line_adj));
-
-  buffer_pool_ctrl->ctrl = t;
-  last_send_ctrl[bufno] = t;
-  buffer_dst[bufno] = dst_idx;
-}
-
-static inline void
-bsm12_resend_from_buf(bsm12_t *sm, int bufno)
-{
-  buffer_pool_ctrl->ctrl = last_send_ctrl[bufno];
-}
-
-void
-bsm12_start(bsm12_t *sm)
-{
-  sm->running = true;
-
-  buffer_state[sm->buf0 + 0] = BS_EMPTY;
-  buffer_state[sm->buf0 + 1] = BS_EMPTY;
-  buffer_state[sm->buf0 + 2] = BS_EMPTY;
-
-  buffer_target[sm->buf0 + 0] = -1;
-  buffer_target[sm->buf0 + 1] = -1;
-  buffer_target[sm->buf0 + 2] = -1;
-
-  bp_clear_buf(sm->buf0 + 0);
-  bp_clear_buf(sm->buf0 + 1);
-  bp_clear_buf(sm->buf0 + 2);
-
-  sm->rx_state = 0;
-  sm->tx_state[0] = ST_IDLE;
-  sm->tx_state[1] = ST_IDLE;
-  bsm12_receive_to_buf(sm, sm->buf0);
-  buffer_state[sm->buf0] = BS_FILLING;
-}
-
-void
-bsm12_stop(bsm12_t *sm)
-{
-  sm->running = false;
-  bp_clear_buf(sm->buf0 + 0);
-  bp_clear_buf(sm->buf0 + 1);
-  bp_clear_buf(sm->buf0 + 2);
-  buffer_state[sm->buf0 + 0] = BS_EMPTY;
-  buffer_state[sm->buf0 + 1] = BS_EMPTY;
-  buffer_state[sm->buf0 + 2] = BS_EMPTY;
-}
-
-static void bsm12_process_helper(bsm12_t *sm, int buf_this);
-static void bsm12_error_helper(bsm12_t *sm, int buf_this);
-
-void
-bsm12_process_status(bsm12_t *sm, uint32_t status)
-{
-  // anything for us?
-  if ((status & sm->bps_error_or_done) == 0 || !sm->running)
-    return;
-
-  if (status & sm->bps_error){
-    // Most likely an ethernet Rx error.  We just restart the transfer.
-    if (status & (BPS_ERROR(sm->buf0 + 0)))
-      bsm12_error_helper(sm, sm->buf0 + 0);
-
-    if (status & (BPS_ERROR(sm->buf0 + 1)))
-      bsm12_error_helper(sm, sm->buf0 + 1);
-
-    if (status & (BPS_ERROR(sm->buf0 + 2)))
-      bsm12_error_helper(sm, sm->buf0 + 2);
-  }
-
-  if (status & BPS_DONE(sm->buf0 + 0))
-    bsm12_process_helper(sm, sm->buf0 + 0);
-
-  if (status & BPS_DONE(sm->buf0 + 1))
-    bsm12_process_helper(sm, sm->buf0 + 1);
-
-  if (status & BPS_DONE(sm->buf0 + 2))
-    bsm12_process_helper(sm, sm->buf0 + 2);
-}
-
-static void 
-bsm12_process_helper(bsm12_t *sm, int buf_this)
-{
-  bp_clear_buf(buf_this);
-
-  if (buffer_state[buf_this] == BS_FILLING){
-
-    buffer_state[buf_this] = BS_FULL;
-    buffer_target[buf_this] = -1;
-
-    //
-    // where does this packet go?
-    //
-    int dst = sm->inspect(sm, buf_this);
-    if (dst == -1){
-      //
-      // f/w handled the packet; refill the buffer
-      //
-      bsm12_receive_to_buf(sm, buf_this);
-      buffer_state[buf_this] = BS_FILLING;
-      buffer_target[buf_this] = -1;
-      sm->rx_state = buf_this & 0x3;
-    }
-    else {	// goes to dst 0 or 1
-      //
-      // If the next buffer is empty, start a receive on it
-      //
-      int t = sm->next_buf[buf_this];
-      if (buffer_state[t] == BS_EMPTY){
-	bsm12_receive_to_buf(sm, t);
-	buffer_state[t] = BS_FILLING;
-	buffer_target[t] = -1;
-	sm->rx_state = t & 0x3;
-      }
-      else
-	sm->rx_state = ST_IDLE;
-
-      //
-      // If the destination is idle, start the xfer, othewise remember it
-      //
-      if (sm->tx_state[dst] == ST_IDLE){
-	bsm12_send_from_buf(sm, buf_this, dst);
-	sm->tx_state[dst] = buf_this & 0x3;
-	buffer_state[buf_this] = BS_EMPTYING;
-	buffer_target[buf_this] = -1;
-      }
-      else {
-	buffer_target[buf_this] = dst;
-      }
-    }
-  }
-
-  else {    // BS_EMPTYING
-
-    buffer_state[buf_this] = BS_EMPTY;
-    buffer_target[buf_this] = -1;
-
-    if (sm->rx_state == ST_IDLE){	// fire off another receive
-      sm->rx_state = buf_this & 0x3;
-      bsm12_receive_to_buf(sm, buf_this);
-      buffer_state[buf_this] = BS_FILLING;
-      buffer_target[buf_this] = -1;
-    }
-
-    int dst = buffer_dst[buf_this];	// the dst we were emptying into
-    // is the next buffer full and for us?
-    int t = sm->next_buf[buf_this];
-    if (buffer_target[t] == dst){		// yes,
-      bsm12_send_from_buf(sm, t, dst);		// send it
-      buffer_state[t] = BS_EMPTYING;
-      buffer_target[t] = -1;
-      sm->tx_state[dst] = t & 0x3;
-    }
-    // how about the one after that?
-    else if (buffer_target[t=sm->next_buf[t]] == dst){	// yes,
-      bsm12_send_from_buf(sm, t, dst);			// send it
-      buffer_state[t] = BS_EMPTYING;
-      buffer_target[t] = -1;
-      sm->tx_state[dst] = t & 0x3;
-    }
-    else {
-      sm->tx_state[dst] = ST_IDLE;
-    }
-  }
-}
-
-static void
-bsm12_error_helper(bsm12_t *sm, int buf_this)
-{
-  bp_clear_buf(buf_this);		  // clears ERROR flag
-
-  if (buffer_state[buf_this] == BS_FILLING){
-    bsm12_receive_to_buf(sm, buf_this);	  // restart the xfer
-  }
-  else { // buffer was emptying
-    bsm12_resend_from_buf(sm, buf_this);  // restart the xfer
-  }
-}
-
-
-void
-bsm12_handle_tx_underrun(bsm12_t *sm)
-{
-}
-
-void
-bsm12_handle_rx_overrun(bsm12_t *sm)
-{
-}
diff --git a/firmware/microblaze/lib/bsm12.h b/firmware/microblaze/lib/bsm12.h
deleted file mode 100644
index b8e576b79..000000000
--- a/firmware/microblaze/lib/bsm12.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2009 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef INCLUDED_BSM12_H
-#define INCLUDED_BSM12_H
-
-#include "dbsm.h"
-#include "memory_map.h"
-
-/*!
- * buffer state machine: 1 input to two outputs
- *
- * Typically used to read packets from the ethernet and then after inspecting,
- * handle the packet in firmware or pass it on to 1 of the 2 buffer destinations.
- */
-
-struct _bsm12;
-typedef struct _bsm12 bsm12_t;
-
-/*!
- * Pointer to function that does packet inspection.
- *
- * \param sm		the state machine
- * \param buf_this	the index of the buffer to inspect and/or pass on
- *
- * Returns -1, 0 or 1.  If it returns -1, it means that the s/w
- * handled that packet, and that it should NOT be passed on to one of
- * the buffer endpoints.  0 indicates the first endpoint, 1 the second endpoint.
- */
-typedef int (*bsm12_inspector_t)(bsm12_t *sm, int buf_this);
-
-
-/*!
- * buffer state machine: 1 input to two outputs
- */
-struct _bsm12
-{
-  uint8_t	  buf0;	 // This machine uses buf0, buf0+1 and buf0+2.  buf0 % 4 == 0.
-  uint8_t	  running;
-  int8_t	  rx_state;	// -1, 0, 1, 2  which buffer we're receiving into
-  int8_t	  tx_state[2];	// -1, 0, 1, 2  which buffer we're sending from
-  buf_cmd_args_t  recv_args;
-  buf_cmd_args_t  send_args[2];
-  bsm12_inspector_t inspect;
-  int		  last_line_adj;
-  uint32_t	  bps_error;
-  uint32_t	  bps_done;
-  uint32_t	  bps_error_or_done;
-  uint8_t	  next_buf[NBUFFERS];
-  uint32_t	  precomputed_receive_to_buf_ctrl_word[3];
-  uint32_t	  precomputed_send_from_buf_ctrl_word[4][2];  // really only 3, not 4 
-                                                              //   (easier addr comp)
-};
-
-void bsm12_init(bsm12_t *sm, int buf0,
-		const buf_cmd_args_t *recv,
-		const buf_cmd_args_t *send0,
-		const buf_cmd_args_t *send1,
-		bsm12_inspector_t inspect);
-
-void bsm12_start(bsm12_t *sm);
-void bsm12_stop(bsm12_t *sm);
-void bsm12_process_status(bsm12_t *sm, uint32_t status);
-void bsm12_handle_tx_underrun(bsm12_t *sm);
-void bsm12_handle_rx_overrun(bsm12_t *sm);
-
-
-#endif /* INCLUDED_BSM12_H */
diff --git a/firmware/microblaze/lib/buffer_pool.c b/firmware/microblaze/lib/buffer_pool.c
deleted file mode 100644
index 77e7c5213..000000000
--- a/firmware/microblaze/lib/buffer_pool.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2007 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "memory_map.h"
-#include "buffer_pool.h"
-#include "hal_io.h" 
-
-void
-bp_init(void)
-{
-  int i;
-  bp_disable_port(PORT_SERDES);
-  bp_disable_port(PORT_DSP);
-  bp_disable_port(PORT_ETH);
-  bp_disable_port(PORT_RAM);
-
-  for (i = 0; i < NBUFFERS; i++)
-    bp_clear_buf(i);
-}
-
-#ifndef INLINE_BUFFER_POOL
-
-void
-bp_clear_buf(int bufnum)
-{
-  buffer_pool_ctrl->ctrl = BPC_BUFFER(bufnum) | BPC_PORT_NIL | BPC_CLR;
-}
-
-void
-bp_disable_port(int portnum) 
-{
-  // disable buffer connections to this port
-  buffer_pool_ctrl->ctrl = BPC_BUFFER_NIL | BPC_PORT(portnum);
-}
-
-void
-bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll)
-{
-  buffer_pool_ctrl->ctrl = (BPC_READ
-			    | BPC_BUFFER(bufnum)
-			    | BPC_PORT(port)
-			    | BPC_STEP(step)
-			    | BPC_FIRST_LINE(fl)
-			    | BPC_LAST_LINE(ll));
-}
-
-void
-bp_send_from_buf(int bufnum, int port, int step, int fl, int ll)
-{
-  buffer_pool_ctrl->ctrl = (BPC_WRITE
-			    | BPC_BUFFER(bufnum)
-			    | BPC_PORT(port)
-			    | BPC_STEP(step)
-			    | BPC_FIRST_LINE(fl)
-			    | BPC_LAST_LINE(ll));
-}
-
-#endif
diff --git a/firmware/microblaze/lib/buffer_pool.h b/firmware/microblaze/lib/buffer_pool.h
deleted file mode 100644
index 145b20f8d..000000000
--- a/firmware/microblaze/lib/buffer_pool.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2007 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef INCLUDED_BUFFER_POOL_H
-#define INCLUDED_BUFFER_POOL_H
-
-#include "memory_map.h"
-
-// Buffer Pool Management
-
-
-// define to have common buffer operations inlined
-#define INLINE_BUFFER_POOL 1
-
-void bp_init(void);
-
-#ifndef INLINE_BUFFER_POOL
-
-void bp_clear_buf(int bufnum);
-void bp_disable_port(int portnum);
-void bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll);
-void bp_send_from_buf(int bufnum, int port, int step, int fl, int ll);
-
-#else
-
-static inline void
-bp_clear_buf(int bufnum)
-{
-  buffer_pool_ctrl->ctrl = BPC_BUFFER(bufnum) | BPC_PORT_NIL | BPC_CLR;
-}
-
-static inline void
-bp_disable_port(int portnum) 
-{
-  // disable buffer connections to this port
-  buffer_pool_ctrl->ctrl = BPC_BUFFER_NIL | BPC_PORT(portnum);
-}
-
-static inline void
-bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll)
-{
-  buffer_pool_ctrl->ctrl = (BPC_READ
-			    | BPC_BUFFER(bufnum)
-			    | BPC_PORT(port)
-			    | BPC_STEP(step)
-			    | BPC_FIRST_LINE(fl)
-			    | BPC_LAST_LINE(ll));
-}
-
-static inline void
-bp_send_from_buf(int bufnum, int port, int step, int fl, int ll)
-{
-  buffer_pool_ctrl->ctrl = (BPC_WRITE
-			    | BPC_BUFFER(bufnum)
-			    | BPC_PORT(port)
-			    | BPC_STEP(step)
-			    | BPC_FIRST_LINE(fl)
-			    | BPC_LAST_LINE(ll));
-}
-#endif
-#endif
diff --git a/firmware/microblaze/lib/dbsm.c b/firmware/microblaze/lib/dbsm.c
deleted file mode 100644
index cee343eaa..000000000
--- a/firmware/microblaze/lib/dbsm.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2007,2008 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * Double Buffering State Machine
- */
-
-#include "dbsm.h"
-#include "memory_map.h"
-#include "buffer_pool.h"
-#include <stdbool.h>
-#include "nonstdio.h"
-#include <stdlib.h>
-
-typedef enum {
-  BS_EMPTY,
-  BS_FILLING,
-  BS_FULL,
-  BS_EMPTYING,
-} buffer_state_t;
-
-static buffer_state_t buffer_state[NBUFFERS];
-
-bool
-dbsm_nop_inspector(dbsm_t *sm, int buf_this)
-{
-  return false;
-}
-
-void
-dbsm_init(dbsm_t *sm, int buf0,
-	  const buf_cmd_args_t *recv, const buf_cmd_args_t *send,
-	  inspector_t inspect)
-{
-  if (buf0 & 0x1)	// must be even
-    abort();
-
-  sm->buf0 = buf0;
-  sm->running = false;
-  sm->recv_args = *recv;
-  sm->send_args = *send;
-
-  sm->rx_idle = true;
-  sm->tx_idle = true;
-
-  sm->inspect = inspect;
-
-  // How much to adjust the last_line register.
-  // It's 1 for everything but the ethernet.
-  //sm->last_line_adj = recv->port == PORT_ETH ? 3 : 1;
-  sm->last_line_adj = 1;
-
-  buffer_state[sm->buf0] = BS_EMPTY;
-  buffer_state[sm->buf0 ^ 1] = BS_EMPTY;
-
-  sm->precomputed_receive_to_buf_ctrl_word[0] =
-    (BPC_READ
-     | BPC_BUFFER(sm->buf0)
-     | BPC_PORT(sm->recv_args.port)
-     | BPC_STEP(1)
-     | BPC_FIRST_LINE(sm->recv_args.first_line)
-     | BPC_LAST_LINE(sm->recv_args.last_line));
-    
-  sm->precomputed_receive_to_buf_ctrl_word[1] =
-    (BPC_READ
-     | BPC_BUFFER(sm->buf0 ^ 1)
-     | BPC_PORT(sm->recv_args.port)
-     | BPC_STEP(1)
-     | BPC_FIRST_LINE(sm->recv_args.first_line)
-     | BPC_LAST_LINE(sm->recv_args.last_line));
-    
-  sm->precomputed_send_from_buf_ctrl_word[0] =
-    (BPC_WRITE
-     | BPC_BUFFER(sm->buf0)
-     | BPC_PORT(sm->send_args.port)
-     | BPC_STEP(1)
-     | BPC_FIRST_LINE(sm->send_args.first_line)
-     | BPC_LAST_LINE(0));		// last line filled in at runtime
-    
-  sm->precomputed_send_from_buf_ctrl_word[1] =
-    (BPC_WRITE
-     | BPC_BUFFER(sm->buf0 ^ 1)
-     | BPC_PORT(sm->send_args.port)
-     | BPC_STEP(1)
-     | BPC_FIRST_LINE(sm->send_args.first_line)
-     | BPC_LAST_LINE(0));		// last line filled in at runtime
-    
-}
-
-static inline void
-dbsm_receive_to_buf(dbsm_t *sm, int bufno)
-{
-  buffer_pool_ctrl->ctrl = sm->precomputed_receive_to_buf_ctrl_word[bufno & 1];
-}
-
-static inline void
-dbsm_send_from_buf(dbsm_t *sm, int bufno)
-{
-  buffer_pool_ctrl->ctrl =
-    (sm->precomputed_send_from_buf_ctrl_word[bufno & 1]
-     | BPC_LAST_LINE(buffer_pool_status->last_line[bufno] - sm->last_line_adj));
-}
-
-void
-dbsm_start(dbsm_t *sm)
-{
-  // printf("dbsm_start: buf0 = %d, recv_port = %d\n", sm->buf0, sm->recv_args.port);
-
-  sm->running = true;
-
-  buffer_state[sm->buf0] = BS_EMPTY;
-  buffer_state[sm->buf0 ^ 1] = BS_EMPTY;
-
-  bp_clear_buf(sm->buf0);
-  bp_clear_buf(sm->buf0 ^ 1);
-
-  sm->tx_idle = true;
-  sm->rx_idle = false;
-  dbsm_receive_to_buf(sm, sm->buf0);
-  buffer_state[sm->buf0] = BS_FILLING;
-
-}
-
-
-void
-dbsm_stop(dbsm_t *sm)
-{
-  sm->running = false;
-  bp_clear_buf(sm->buf0);
-  bp_clear_buf(sm->buf0 ^ 1);
-  buffer_state[sm->buf0] = BS_EMPTY;
-  buffer_state[sm->buf0 ^ 1] = BS_EMPTY;
-}
-
-static void dbsm_process_helper(dbsm_t *sm, int buf_this);
-static void dbsm_error_helper(dbsm_t *sm, int buf_this);
-
-void
-dbsm_process_status(dbsm_t *sm, uint32_t status)
-{
-  if (!sm->running)
-    return;
-
-  if (status & (BPS_ERROR(sm->buf0) | BPS_ERROR(sm->buf0 ^ 1))){
-    putchar('E');
-    // Most likely an ethernet Rx error.  We just restart the transfer.
-    if (status & (BPS_ERROR(sm->buf0)))
-      dbsm_error_helper(sm, sm->buf0);
-      //dbsm_process_helper(sm, sm->buf0); //forward errors
-
-    if (status & (BPS_ERROR(sm->buf0 ^ 1)))
-      dbsm_error_helper(sm, sm->buf0 ^ 1);
-      //dbsm_process_helper(sm, sm->buf0 ^ 1); //forward errors
-  }
-
-  if (status & BPS_DONE(sm->buf0))
-    dbsm_process_helper(sm, sm->buf0);
-
-  if (status & BPS_DONE(sm->buf0 ^ 1))
-    dbsm_process_helper(sm, sm->buf0 ^ 1);
-}
-
-static void
-dbsm_process_helper(dbsm_t *sm, int buf_this)
-{
-  int buf_other = buf_this ^ 1;
-
-  bp_clear_buf(buf_this);
-
-  if (buffer_state[buf_this] == BS_FILLING){
-    buffer_state[buf_this] = BS_FULL;
-    //
-    // does s/w handle this packet?
-    //
-    if (sm->inspect(sm, buf_this)){
-      // s/w handled the packet; refill the buffer
-      dbsm_receive_to_buf(sm, buf_this);
-      buffer_state[buf_this] = BS_FILLING;
-    }
-
-    else {	// s/w didn't handle this; pass it on
-
-      if(buffer_state[buf_other] == BS_EMPTY){
-	dbsm_receive_to_buf(sm, buf_other);
-	buffer_state[buf_other] = BS_FILLING;
-      }
-      else
-	sm->rx_idle = true;
-
-      if (sm->tx_idle){
-	sm->tx_idle = false;
-	dbsm_send_from_buf(sm, buf_this);
-	buffer_state[buf_this] = BS_EMPTYING;
-      }
-    }
-  }
-  else {  // buffer was emptying
-    buffer_state[buf_this] = BS_EMPTY;
-    if (sm->rx_idle){
-      sm->rx_idle = false;
-      dbsm_receive_to_buf(sm, buf_this);
-      buffer_state[buf_this] = BS_FILLING;
-    }
-    if (buffer_state[buf_other] == BS_FULL){
-      dbsm_send_from_buf(sm, buf_other);
-      buffer_state[buf_other] = BS_EMPTYING;
-    }
-    else
-      sm->tx_idle = true;
-  }
-}
-
-static void
-dbsm_error_helper(dbsm_t *sm, int buf_this)
-{
-  bp_clear_buf(buf_this);		// clears ERROR flag
-
-  if (buffer_state[buf_this] == BS_FILLING){
-    dbsm_receive_to_buf(sm, buf_this);	  // restart the xfer
-  }
-  else { // buffer was emptying
-    dbsm_send_from_buf(sm, buf_this);	  // restart the xfer
-  }
-}
-
-/*
- * Handle DSP Tx underrun
- */
-void
-dbsm_handle_tx_underrun(dbsm_t *sm)
-{
-  // clear the DSP Tx state machine
-  sr_tx_ctrl->clear_state = 1;
-
-  // If there's a buffer that's empyting, clear it & flush xfer
-
-  if (buffer_state[sm->buf0] == BS_EMPTYING){
-    bp_clear_buf(sm->buf0);
-    sr_tx_ctrl->clear_state = 1;	// flush partial packet
-    // drop frame in progress on ground.  Pretend it finished
-    dbsm_process_helper(sm, sm->buf0);
-  }
-  else if (buffer_state[sm->buf0 ^ 1] == BS_EMPTYING){
-    bp_clear_buf(sm->buf0 ^ 1);
-    sr_tx_ctrl->clear_state = 1;	// flush partial packet
-    // drop frame in progress on ground.  Pretend it finished
-    dbsm_process_helper(sm, sm->buf0 ^ 1);
-  }
-}
-
-/*
- * Handle DSP Rx overrun
- */
-void
-dbsm_handle_rx_overrun(dbsm_t *sm)
-{
-  sr_rx_ctrl->clear_overrun = 1;
-
-  // If there's a buffer that's filling, clear it.
-  // Any restart will be the job of the caller.
-  
-  if (buffer_state[sm->buf0] == BS_FILLING)
-    bp_clear_buf(sm->buf0);
-
-  if (buffer_state[sm->buf0 ^1] == BS_FILLING)
-    bp_clear_buf(sm->buf0 ^ 1);
-}
-
-void 
-dbsm_wait_for_opening(dbsm_t *sm)
-{
-  if (buffer_state[sm->buf0] == BS_EMPTYING){
-    // wait for xfer to complete
-    int mask = BPS_DONE(sm->buf0) | BPS_ERROR(sm->buf0) | BPS_IDLE(sm->buf0);
-    while ((buffer_pool_status->status & mask) == 0)
-      ;
-  }
-  else if (buffer_state[sm->buf0 ^ 1] == BS_EMPTYING){
-    // wait for xfer to complete
-    int mask = BPS_DONE(sm->buf0 ^ 1) | BPS_ERROR(sm->buf0 ^ 1) | BPS_IDLE(sm->buf0 ^ 1);
-    while ((buffer_pool_status->status & mask) == 0)
-      ;
-  }
-}
diff --git a/firmware/microblaze/lib/dbsm.h b/firmware/microblaze/lib/dbsm.h
deleted file mode 100644
index cb7e12fc3..000000000
--- a/firmware/microblaze/lib/dbsm.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2007 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef INCLUDED_DBSM_H
-#define INCLUDED_DBSM_H
-
-/*
- * Double Buffering State Machine
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-struct _dbsm;
-typedef struct _dbsm dbsm_t;
-
-/*
- * pointer to function that does packet inspection.
- *
- * If one of these returns true, it means that the s/w
- * handled that packet, and that it should NOT be passed
- * on to the normal destination port.
- */
-typedef bool (*inspector_t)(dbsm_t *sm, int buf_this);
-
-bool dbsm_nop_inspector(dbsm_t *sm, int buf_this);	// returns false
-
-
-typedef struct
-{
-  uint16_t	port;
-  uint16_t	first_line;
-  uint16_t	last_line;
-} buf_cmd_args_t;
-
-/*!
- * double buffer state machine
- */
-struct _dbsm
-{
-  uint8_t	  buf0;	     // Must be even. This machine uses buf0 and buf0+1
-  uint8_t	  running;
-  uint8_t	  rx_idle;
-  uint8_t	  tx_idle;
-  buf_cmd_args_t  recv_args;
-  buf_cmd_args_t  send_args;
-  inspector_t	  inspect;
-  uint32_t	  precomputed_receive_to_buf_ctrl_word[2];
-  uint32_t	  precomputed_send_from_buf_ctrl_word[2];
-  int		  last_line_adj;
-};
-
-void dbsm_init(dbsm_t *sm, int buf0,
-	       const buf_cmd_args_t *recv, const buf_cmd_args_t *send,
-	       inspector_t inspect);
-
-void dbsm_start(dbsm_t *sm);
-void dbsm_stop(dbsm_t *sm);
-void dbsm_process_status(dbsm_t *sm, uint32_t status);
-void dbsm_handle_tx_underrun(dbsm_t *sm);
-void dbsm_handle_rx_overrun(dbsm_t *sm);
-
-/*
- * The cpu calls this when it want to ensure that it can send a buffer
- * to the same destination being used by this state machine.
- *
- * If neither buffer is EMPTYING it returns immediately.  If a buffer
- * is EMPYTING, it waits for the h/w to transition to the DONE or
- * ERROR state.
- *
- * When this function returns, the caller queues it's buffer and busy
- * waits for it to complete.
- */
-void dbsm_wait_for_opening(dbsm_t *sm);
-
-#endif /* INCLUDED_DBSM_H */
diff --git a/firmware/microblaze/lib/net/.gitignore b/firmware/microblaze/lib/net/.gitignore
deleted file mode 100644
index 282522db0..000000000
--- a/firmware/microblaze/lib/net/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/firmware/microblaze/lib/usrp2_bytesex.h b/firmware/microblaze/lib/usrp2_bytesex.h
deleted file mode 100644
index 2b74f2a0b..000000000
--- a/firmware/microblaze/lib/usrp2_bytesex.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2007 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef INCLUDED_USRP2_BYTESEX_H
-#define INCLUDED_USRP2_BYTESEX_H
-
-// The USRP2 speaks big-endian...
-// Use the standard include files or provide substitutions for
-// htons and friends
-
-#if defined(HAVE_ARPA_INET_H)
-#include <arpa/inet.h>
-#elif defined(HAVE_NETINET_IN_H)
-#include <netinet/in.h>
-#else
-#include <stdint.h>
-
-#ifdef WORDS_BIGENDIAN  // nothing to do...
-
-static inline uint32_t htonl(uint32_t x){ return x; }
-static inline uint16_t htons(uint16_t x){ return x; }
-static inline uint32_t ntohl(uint32_t x){ return x; }
-static inline uint16_t ntohs(uint16_t x){ return x; }
-
-#else
-
-#ifdef HAVE_BYTESWAP_H
-#include <byteswap.h>
-#else
-
-static inline uint16_t
-bswap_16 (uint16_t x)
-{
-  return ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8));
-}
-
-static inline uint32_t
-bswap_32 (uint32_t x)
-{
-  return ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >>  8) \
-        | (((x) & 0x0000ff00) <<  8) | (((x) & 0x000000ff) << 24));
-}
-#endif
-
-static inline uint32_t htonl(uint32_t x){ return bswap_32(x); }
-static inline uint16_t htons(uint16_t x){ return bswap_16(x); }
-static inline uint32_t ntohl(uint32_t x){ return bswap_32(x); }
-static inline uint16_t ntohs(uint16_t x){ return bswap_16(x); }
-
-#endif
-#endif
-#endif /* INCLUDED_USRP2_BYTESEX_H */
diff --git a/firmware/microblaze/lib/wb16550.h b/firmware/microblaze/lib/wb16550.h
deleted file mode 100644
index 7522f4438..000000000
--- a/firmware/microblaze/lib/wb16550.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* -*- c -*- */
-/*
- * Copyright 2007 Free Software Foundation, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-// Wishbone National Semiconductor 16550A compatible UART 
-
-#ifndef INCLUDED_WB16550_H
-#define INCLUDED_WB16550_H
-
-#include <stdint.h>
-
-typedef struct {
-  volatile uint8_t data;     // 0 r/w: r: rx fifo, w: tx fifo (if DLAB: LSB of divisor)
-  volatile uint8_t ier;      // 1 r/w: Interrupt Enable Register (if DLAB: MSB of divisor)
-  volatile uint8_t iir_fcr;  // 2 r/w: r: Interrupt ID Register,
-                             //        w: Fifo Control Register
-  volatile uint8_t lcr;      // 3 r/w: Line Control Register
-  volatile uint8_t mcr;      // 4 w:   Modem Control Register
-  volatile uint8_t lsr;      // 5 r:   Line Status Register
-  volatile uint8_t msr;      // 6 r:   Modem Status Register
-
-} wb16550_reg_t;
-
-#define UART_IER_RDI		0x01  // Enable received data interrupt
-#define UART_IER_THRI		0x02  // Enable transmitter holding reg empty int.
-#define	UART_IER_RLSI		0x04  // Enable receiver line status interrupt
-#define UART_IER_MSI		0x08  // Enable modem status interrupt
-
-#define	UART_IIR_NO_INT		0x01  // No interrupts pending
-#define UART_IIR_ID_MASK	0x06  // Mask for interrupt ID
-#define	UART_IIR_MSI		0x00  // Modem status interrupt
-#define	UART_IIR_THRI		0x02  // Tx holding register empty int
-#define	UART_IIR_RDI		0x04  // Rx data available int
-#define UART_IIR_RLSI		0x06  // Receiver line status int
-
-#define	UART_FCR_ENABLE_FIFO	0x01  // ignore, always enabled
-#define UART_FCR_CLEAR_RCVR	0x02  // Clear the RCVR FIFO
-#define UART_FCR_CLEAR_XMIT	0x04  // Clear the XMIT FIFO
-#define UART_FCR_TRIGGER_MASK	0xC0  // Mask for FIFO trigger range
-#define	UART_FCR_TRIGGER_1	0x00  // Rx fifo trigger level:  1 byte
-#define	UART_FCR_TRIGGER_4	0x40  // Rx fifo trigger level:  4 bytes
-#define	UART_FCR_TRIGGER_8	0x80  // Rx fifo trigger level:  8 bytes
-#define	UART_FCR_TRIGGER_14	0xC0  // Rx fifo trigger level: 14 bytes
-
-#define UART_LCR_DLAB		0x80  // Divisor latch access bit 
-#define UART_LCR_SBC		0x40  // Set break control 
-#define UART_LCR_SPAR		0x20  // Stick parity
-#define UART_LCR_EPAR		0x10  // Even parity select 
-#define UART_LCR_PARITY		0x08  // Parity Enable 
-#define UART_LCR_STOP		0x04  // Stop bits: 0=1 bit, 1=2 bits 
-#define UART_LCR_WLEN5		0x00  // Wordlength: 5 bits 
-#define UART_LCR_WLEN6		0x01  // Wordlength: 6 bits 
-#define UART_LCR_WLEN7		0x02  // Wordlength: 7 bits 
-#define UART_LCR_WLEN8		0x03  // Wordlength: 8 bits 
-
-#define UART_MCR_LOOP		0x10  // Enable loopback test mode 
-#define UART_MCR_OUT2n		0x08  // Out2 complement (loopback mode)
-#define UART_MCR_OUT1n		0x04  // Out1 complement (loopback mode)
-#define UART_MCR_RTSn		0x02  // RTS complement 
-#define UART_MCR_DTRn		0x01  // DTR complement 
-
-#define UART_LSR_TEMT		0x40  // Transmitter empty 
-#define UART_LSR_THRE		0x20  // Transmit-hold-register empty 
-#define UART_LSR_BI		0x10  // Break interrupt indicator 
-#define UART_LSR_FE		0x08  // Frame error indicator 
-#define UART_LSR_PE		0x04  // Parity error indicator 
-#define UART_LSR_OE		0x02  // Overrun error indicator 
-#define UART_LSR_DR		0x01  // Receiver data ready 
-#define UART_LSR_BRK_ERROR_BITS	0x1E  // BI, FE, PE, OE bits 
-#define UART_LSR_ERROR		0x80  // At least 1 PE, FE or BI are in the fifo
-
-#define UART_MSR_DCD		0x80  // Data Carrier Detect 
-#define UART_MSR_RI		0x40  // Ring Indicator 
-#define UART_MSR_DSR		0x20  // Data Set Ready 
-#define UART_MSR_CTS		0x10  // Clear to Send 
-#define UART_MSR_DDCD		0x08  // Delta DCD 
-#define UART_MSR_TERI		0x04  // Trailing edge ring indicator 
-#define UART_MSR_DDSR		0x02  // Delta DSR 
-#define UART_MSR_DCTS		0x01  // Delta CTS 
-#define UART_MSR_ANY_DELTA	0x0F  // Any of the delta bits! 
-
-
-#endif  // INCLUDED_WB16550_H 
diff --git a/firmware/microblaze/u2_flash_tool b/firmware/microblaze/u2_flash_tool
deleted file mode 100755
index 2b66a4ac0..000000000
--- a/firmware/microblaze/u2_flash_tool
+++ /dev/null
@@ -1,116 +0,0 @@
-#!/usr/bin/env python
-
-import sys
-from optparse import OptionParser
-
-SECTOR_SIZE = 512                 # bytes
-MAX_FILE_SIZE =  1 * (2**20)      # maximum number of bytes we'll burn to a slot
-
-FPGA_OFFSET = 0                   # offset in flash to fpga image
-FIRMWARE_OFFSET = 1 * (2**20)     # offset in flash to firmware image
-
-def read_file_data(filename):
-    f = open(filename, "rb")
-    file_data = f.read(MAX_FILE_SIZE)
-    t = len(file_data) % SECTOR_SIZE
-    if t != 0:
-        file_data += (SECTOR_SIZE - t)*chr(0)  # pad to an even sector size w/ zeros
-    return file_data
-
-
-def write_flash(offset, filename, devname):
-    file_data = read_file_data(filename)
-    dev = open(devname, "wb")
-    dev.seek(offset, 0)                 # seek to absolute byte offset
-    dev.write(file_data)
-    dev.flush()
-    dev.close()
-    return True
-
-
-def verify_flash(offset, filename, devname):
-    file_data = read_file_data(filename)
-    dev = open(devname, "rb")
-    dev.seek(offset, 0)                 # seek to absolute byte offset
-    dev_data = dev.read(len(file_data))
-    if len(dev_data) != len(file_data):
-        sys.stderr.write("short read on device %s\n" % (devname,))
-        return False
-
-    if file_data == dev_data:
-        return True
-
-    # doesn't match
-    nwrong = 0
-    for i in range(len(file_data)):
-        if dev_data[i] != file_data[i]:
-            sys.stderr.write("mismatch at offset %7d.  Expected 0x%02x, got 0x%02x\n" % (
-                i, ord(file_data[i]), ord(dev_data[i])))
-            nwrong += 1
-            if nwrong > 16:
-                sys.stderr.write("> 16 errors, stopping comparison\n")
-                break
-    return False
-
-def read_flash(offset, filename, devname):
-    dev = open(devname, "rb")
-    dev.seek(offset, 0)                 # seek to absolute byte offset
-    dev_data = dev.read(MAX_FILE_SIZE)
-    dev.close()
-    open(filename, "wb").write(dev_data)
-
-    
-def main():
-    parser = OptionParser(usage="%prog: [options] filename")
-    parser.add_option("-w", "--write", action="store_const", const="write", dest="mode",
-                      help="write FILE to TARGET slot")
-    parser.add_option("-v", "--verify",  action="store_const", const="verify", dest="mode",
-                      help="verify FILE against TARGET slot")
-    parser.add_option("-r", "--read",  action="store_const", const="read", dest="mode",
-                      help="read TARGET slot, write to FILE")
-    parser.add_option("-t", "--target", type="choice", choices=("fpga", "s/w"), default="s/w",
-                      help="select TARGET slot from: fpga, s/w [default=%default]")
-    parser.add_option("", "--dev", default=None,
-                      help="specify flash device file, e.g., /dev/sdb.  Be careful!")
-    parser.set_defaults(target="s/w", mode=None)
-
-    (options, args) = parser.parse_args()
-    if len(args) != 1:
-        parser.print_help()
-        raise SystemExit
-
-    filename = args[0]
-
-    if options.mode is None:
-        sys.stderr.write("specify mode with -w, -v or -r\n")
-        parser.print_help()
-        raise SystemExit
-
-    if options.dev is None:
-        sys.stderr.write("specify the device file with --dev\n")
-        parser.print_help()
-        raise SystemExit
-
-    offset = { "fpga" : FPGA_OFFSET, "s/w" : FIRMWARE_OFFSET }[options.target]
-    
-    if options.mode == "write":
-        r = (write_flash(offset, filename, options.dev)
-             and verify_flash(offset, filename, options.dev))
-    elif options.mode == "verify":
-        r = verify_flash(offset, filename, options.dev)
-    elif options.mode == "read":
-        r = read_flash(offset, filename, options.dev)
-    else:
-        raise NotImplemented
-
-    if not r:
-        raise SystemExit, 1
-
-
-if __name__ == "__main__":
-    main()
-
-    
-
-
-    
diff --git a/firmware/microblaze/usrp2/.gitignore b/firmware/microblaze/usrp2/.gitignore
deleted file mode 100644
index 18f715618..000000000
--- a/firmware/microblaze/usrp2/.gitignore
+++ /dev/null
@@ -1,9 +0,0 @@
-/Makefile
-/Makefile.in
-/*.a
-/*.bin
-/*.dump
-/*.ihx
-/*.elf
-/*.rom
-/*.map
diff --git a/firmware/microblaze/usrp2p/.gitignore b/firmware/microblaze/usrp2p/.gitignore
deleted file mode 100644
index 18f715618..000000000
--- a/firmware/microblaze/usrp2p/.gitignore
+++ /dev/null
@@ -1,9 +0,0 @@
-/Makefile
-/Makefile.in
-/*.a
-/*.bin
-/*.dump
-/*.ihx
-/*.elf
-/*.rom
-/*.map
diff --git a/firmware/microblaze/usrp2p/Makefile.am b/firmware/microblaze/usrp2p/Makefile.am
deleted file mode 100644
index 40766b406..000000000
--- a/firmware/microblaze/usrp2p/Makefile.am
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(top_srcdir)/Makefile.common
-
-AM_CFLAGS = \
-	$(COMMON_CFLAGS) \
-	-DUSRP2P
-
-AM_LDFLAGS = \
-	$(COMMON_LFLAGS) \
-	-Wl,-defsym -Wl,_TEXT_START_ADDR=0x8050 \
-	-Wl,-defsym -Wl,_STACK_SIZE=3072
-
-LDADD = libusrp2p.a
-
-#all of this here is to relocate the hardware vectors to somewhere normal.
-RELOCATE_ARGS = \
-	--change-section-address .vectors.sw_exception+0x8000 \
-	--change-section-address .vectors.hw_exception+0x8000 \
-	--change-section-address .vectors.interrupt+0x8000 \
-	--change-section-address .vectors.reset+0x8000
-
-#	$(MB_OBJCOPY) -O ihex $< $@
-# the below would work if objcopy weren't written by apes
-#	$(MB_OBJCOPY) -O ihex -w --change-section-address .vectors*+0x8000 $< $@
-# using the below will throw away the interrupt vectors when they get relocated below 0x0000.
-#	$(MB_OBJCOPY) -O ihex --change-addresses -0x8000 $< $@
-
-########################################################################
-# USRP2P specific library and programs
-########################################################################
-noinst_LIBRARIES = libusrp2p.a
-
-libusrp2p_a_SOURCES = \
-	$(COMMON_SRCS) \
-	spif.c \
-	spi_flash.c \
-	spi_flash_read.c \
-	bootloader_utils.c \
-	ethernet.c \
-	xilinx_s3_icap.c \
-  udp_fw_update.c
-
-noinst_PROGRAMS = \
-	usrp2p_txrx_uhd.elf \
-  usrp2p_blinkenlights.elf \
-  usrp2p_uart_flash_loader.elf
-
-usrp2p_txrx_uhd_elf_SOURCES = \
-	$(top_srcdir)/apps/txrx_uhd.c
-
-usrp2p_blinkenlights_elf_SOURCES = \
-  $(top_srcdir)/apps/blinkenlights.c
-
-usrp2p_uart_flash_loader_elf_SOURCES = \
-  $(top_srcdir)/apps/uart_flash_loader.c
diff --git a/firmware/microblaze/usrp2p/bootloader/.gitignore b/firmware/microblaze/usrp2p/bootloader/.gitignore
deleted file mode 100644
index 17b0f82f3..000000000
--- a/firmware/microblaze/usrp2p/bootloader/.gitignore
+++ /dev/null
@@ -1,11 +0,0 @@
-/*.ihx
-/*.rmi
-/*_rom
-/*.elf
-/*.bin
-/*.dump
-/*.log
-/*.rom
-/*.map
-/Makefile
-/Makefile.in
diff --git a/firmware/microblaze/usrp2p/bootloader/Makefile.am b/firmware/microblaze/usrp2p/bootloader/Makefile.am
deleted file mode 100644
index 1fc5daf9c..000000000
--- a/firmware/microblaze/usrp2p/bootloader/Makefile.am
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# Copyright 2007,2008,2009 Free Software Foundation, Inc.
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-include $(top_srcdir)/Makefile.common
-
-ROM_LINKER_SCRIPT = u2p2-rom.ld
-
-# loads into 8K boot ram located at 0x0000_0000
-AM_CFLAGS = $(COMMON_CFLAGS) -I$(top_srcdir)/usrp2p
-AM_LDFLAGS = -Wl,-T,$(ROM_LINKER_SCRIPT) $(COMMON_LFLAGS) -Wl,-defsym -Wl,_STACK_SIZE=1024
-
-EXTRA_DIST = $(ROM_LINKER_SCRIPT)
-
-LDADD = $(top_srcdir)/usrp2p/libusrp2p.a
-
-noinst_PROGRAMS = \
-	init_bootloader.elf
-
-init_bootloader_elf_SOURCES = init_bootloader.c
-
-.bin.rmi:
-	$(top_srcdir)/bin/bin_to_ram_macro_init.py $< $@
-
-_generated_from_elf += \
-	$(noinst_PROGRAMS:.elf=.rmi)
diff --git a/firmware/microblaze/usrp2p/bootloader_utils.c b/firmware/microblaze/usrp2p/bootloader_utils.c
deleted file mode 100644
index fadd225bb..000000000
--- a/firmware/microblaze/usrp2p/bootloader_utils.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* -*- c++ -*- */
-/*
- * Copyright 2010 Ettus Research LLC
- *
- */
-
-//contains routines for loading programs from Flash. depends on Flash libraries.
-//also contains routines for reading / writing EEPROM flags for the bootloader
-#include <stdbool.h>
-#include <string.h>
-#include <bootloader_utils.h>
-#include <spi_flash.h>
-
-int is_valid_fpga_image(uint32_t addr) {
-	uint8_t imgbuf[64];
-	spi_flash_read(addr, 64, imgbuf);
-	//we're just looking for leading 0xFF padding, followed by the sync bytes 0xAA 0x99
-	int i = 0;
-	for(i; i<63; i++) {
-		if(imgbuf[i] == 0xFF) continue;
-		if(imgbuf[i] == 0xAA && imgbuf[i+1] == 0x99) return 1;
-	}
-	
-	return 0;
-}
-
-int is_valid_fw_image(uint32_t addr) {
-	static const uint8_t fwheader[] = {0xB0, 0x00, 0x00, 0x00, 0xB8, 0x08}; //just lookin for a jump to anywhere located at the reset vector
-	uint8_t buf[12];
-	spi_flash_read(addr, 6, buf);
-	return memcmp(buf, fwheader, 6) == 0;
-}
-
-void start_program(uint32_t addr)
-{
-	memcpy(0x00000000, addr+0x00000000, 36); //copy the whole vector table, with the reset vector, into boot RAM
-	typedef void (*fptr_t)(void);
-	(*(fptr_t) 0x00000000)();	// most likely no return
-}
diff --git a/firmware/zpu/.gitignore b/firmware/zpu/.gitignore
new file mode 100644
index 000000000..796b96d1c
--- /dev/null
+++ b/firmware/zpu/.gitignore
@@ -0,0 +1 @@
+/build
diff --git a/firmware/microblaze/AUTHORS b/firmware/zpu/AUTHORS
index c365261f8..c230624fb 100644
--- a/firmware/microblaze/AUTHORS
+++ b/firmware/zpu/AUTHORS
@@ -1,3 +1,4 @@
 Eric Blossom <eb@comsec.com>
 Matt Ettus <matt@ettus.com>
 Josh Blum <josh@ettus.com>
+Nick Foster <nick@ettus.com>
diff --git a/firmware/zpu/CMakeLists.txt b/firmware/zpu/CMakeLists.txt
new file mode 100644
index 000000000..6222cc2bf
--- /dev/null
+++ b/firmware/zpu/CMakeLists.txt
@@ -0,0 +1,118 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+# setup project and compiler
+########################################################################
+CMAKE_MINIMUM_REQUIRED(VERSION 2.6)
+SET(CMAKE_C_COMPILER zpu-elf-gcc)
+SET(CMAKE_C_COMPILER_WORKS TRUE)
+SET(CMAKE_C_COMPILER_FORCED TRUE)
+PROJECT(USRP_NXXX_FW C)
+
+########################################################################
+# lwIP header include dirs
+########################################################################
+SET(LWIPDIR ${CMAKE_SOURCE_DIR}/lwip/lwip-1.3.1)
+
+INCLUDE_DIRECTORIES(
+    ${CMAKE_SOURCE_DIR}/lwip
+    ${CMAKE_SOURCE_DIR}/lwip_port
+    ${LWIPDIR}/src/include
+    ${LWIPDIR}/src/include/ipv4
+)
+
+########################################################################
+# misc flags for the gcc compiler
+########################################################################
+SET(CMAKE_C_FLAGS -abel) #always needed compile time and link time
+ADD_DEFINITIONS(-Os --std=gnu99 -Wall -Werror-implicit-function-declaration -ffunction-sections)
+
+MACRO(ADD_LINKER_FLAGS flags)
+    SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${flags}")
+ENDMACRO(ADD_LINKER_FLAGS)
+
+ADD_LINKER_FLAGS("-Wl,--relax -Wl,--gc-sections")
+
+########################################################################
+# define for the hal io (FIXME move?)
+########################################################################
+#ADD_DEFINITIONS(-DHAL_IO_USES_DBOARD_PINS)
+ADD_DEFINITIONS(-DHAL_IO_USES_UART)
+
+########################################################################
+# common cflags and ldflags
+########################################################################
+INCLUDE_DIRECTORIES(
+    ${CMAKE_SOURCE_DIR}/../../host/lib/usrp
+    ${CMAKE_SOURCE_DIR}/lib
+)
+
+########################################################################
+# setup programs for output files
+########################################################################
+FIND_PROGRAM(LINKER zpu-elf-ld)
+FIND_PROGRAM(OBJCOPY zpu-elf-objcopy)
+FIND_PROGRAM(OBJDUMP zpu-elf-objdump)
+FIND_PROGRAM(HEXDUMP hexdump)
+
+########################################################################
+# helper functions to build output formats
+########################################################################
+MACRO(GEN_OUTPUTS target)
+    GET_FILENAME_COMPONENT(name ${target} NAME_WE)
+    #command to create a map from elf
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.map DEPENDS ${target}
+        COMMAND ${LINKER}
+        ARGS -Map ${name}.map ${target}
+    )
+    #command to create a bin from elf
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.bin DEPENDS ${target}
+        COMMAND ${OBJCOPY}
+        ARGS -O binary ${target} ${name}.bin
+    )
+    #command to create a ihx from elf
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.ihx DEPENDS ${target}
+        COMMAND ${OBJCOPY}
+        ARGS -O ihex ${target} ${name}.ihx
+    )
+    #command to create a dump from elf
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.dump DEPENDS ${target}
+        COMMAND ${OBJDUMP}
+        ARGS -DSC ${target} > ${name}.dump
+    )
+    #command to create a rom from bin
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.rom DEPENDS ${name}.bin
+        COMMAND ${HEXDUMP}
+        ARGS -v -e'1/1 \"%.2X\\n\"' ${name}.bin > ${name}.rom
+    )
+    #add a top level target for output files
+    ADD_CUSTOM_TARGET(
+        ${name}_outputs ALL DEPENDS ${name}.map ${name}.bin ${name}.ihx ${name}.dump ${name}.rom
+    )
+ENDMACRO(GEN_OUTPUTS)
+
+########################################################################
+# Add the subdirectories
+########################################################################
+ADD_SUBDIRECTORY(usrp2)
+ADD_SUBDIRECTORY(usrp2p)
diff --git a/firmware/zpu/README b/firmware/zpu/README
new file mode 100644
index 000000000..ba0aa11eb
--- /dev/null
+++ b/firmware/zpu/README
@@ -0,0 +1,16 @@
+########################################################################
+# ZPU firmware code for USRP2 and N Series
+########################################################################
+This code requires the gcc-zpu tool-chain which can be found here:
+
+http://opensource.zylin.com/zpudownload.html
+
+zpu-elf-gcc should be in your $PATH
+
+########################################################################
+# Run the following commands to build
+########################################################################
+mkdir build
+cd build
+cmake ../
+make
diff --git a/firmware/microblaze/apps/bitrot/tx_drop.c b/firmware/zpu/apps/bitrot/tx_drop.c
index 3a336e938..3a336e938 100644
--- a/firmware/microblaze/apps/bitrot/tx_drop.c
+++ b/firmware/zpu/apps/bitrot/tx_drop.c
diff --git a/firmware/microblaze/apps/bitrot/tx_drop2.c b/firmware/zpu/apps/bitrot/tx_drop2.c
index 3afd722e6..3afd722e6 100644
--- a/firmware/microblaze/apps/bitrot/tx_drop2.c
+++ b/firmware/zpu/apps/bitrot/tx_drop2.c
diff --git a/firmware/microblaze/apps/bitrot/tx_drop_rate_limited.c b/firmware/zpu/apps/bitrot/tx_drop_rate_limited.c
index 2b8db7f7d..2b8db7f7d 100644
--- a/firmware/microblaze/apps/bitrot/tx_drop_rate_limited.c
+++ b/firmware/zpu/apps/bitrot/tx_drop_rate_limited.c
diff --git a/firmware/microblaze/apps/blinkenlights.c b/firmware/zpu/apps/blinkenlights.c
index 4cebe5c9d..30cb33a7f 100644
--- a/firmware/microblaze/apps/blinkenlights.c
+++ b/firmware/zpu/apps/blinkenlights.c
@@ -12,9 +12,11 @@ int main(int argc, char *argv[]) {
 	uint32_t c = 0;
 	uint8_t i = 0;
 
+	output_regs->led_src = 0;
+
 	while(1) {
 		//delay(5000000);
-		for(c=0;c<5000000;c++) asm("NOP");
+		for(c=0;c<50000;c++) asm("NOP");
 		output_regs->leds = (i++ % 2) ? 0xFF : 0x00; //blink everything on that register
 	}
 
diff --git a/firmware/microblaze/apps/cruft/app_passthru_v2.c b/firmware/zpu/apps/cruft/app_passthru_v2.c
index 406c56b3b..406c56b3b 100644
--- a/firmware/microblaze/apps/cruft/app_passthru_v2.c
+++ b/firmware/zpu/apps/cruft/app_passthru_v2.c
diff --git a/firmware/microblaze/apps/cruft/app_passthru_v2.h b/firmware/zpu/apps/cruft/app_passthru_v2.h
index 3904c670f..3904c670f 100644
--- a/firmware/microblaze/apps/cruft/app_passthru_v2.h
+++ b/firmware/zpu/apps/cruft/app_passthru_v2.h
diff --git a/firmware/microblaze/apps/cruft/blink_leds.c b/firmware/zpu/apps/cruft/blink_leds.c
index 682ca8db2..682ca8db2 100644
--- a/firmware/microblaze/apps/cruft/blink_leds.c
+++ b/firmware/zpu/apps/cruft/blink_leds.c
diff --git a/firmware/microblaze/apps/cruft/blink_leds2.c b/firmware/zpu/apps/cruft/blink_leds2.c
index 13e78afb3..13e78afb3 100644
--- a/firmware/microblaze/apps/cruft/blink_leds2.c
+++ b/firmware/zpu/apps/cruft/blink_leds2.c
diff --git a/firmware/microblaze/apps/cruft/buf_ram_test.c b/firmware/zpu/apps/cruft/buf_ram_test.c
index 1aca2aec5..1aca2aec5 100644
--- a/firmware/microblaze/apps/cruft/buf_ram_test.c
+++ b/firmware/zpu/apps/cruft/buf_ram_test.c
diff --git a/firmware/microblaze/apps/cruft/burn_dbsrx_eeprom.c b/firmware/zpu/apps/cruft/burn_dbsrx_eeprom.c
index 116d4d8d0..116d4d8d0 100644
--- a/firmware/microblaze/apps/cruft/burn_dbsrx_eeprom.c
+++ b/firmware/zpu/apps/cruft/burn_dbsrx_eeprom.c
diff --git a/firmware/microblaze/apps/cruft/burnrev30.c b/firmware/zpu/apps/cruft/burnrev30.c
index 40fa53e34..40fa53e34 100644
--- a/firmware/microblaze/apps/cruft/burnrev30.c
+++ b/firmware/zpu/apps/cruft/burnrev30.c
diff --git a/firmware/microblaze/apps/cruft/burnrev31.c b/firmware/zpu/apps/cruft/burnrev31.c
index f6b08d187..f6b08d187 100644
--- a/firmware/microblaze/apps/cruft/burnrev31.c
+++ b/firmware/zpu/apps/cruft/burnrev31.c
diff --git a/firmware/microblaze/apps/cruft/can_i_sub.c b/firmware/zpu/apps/cruft/can_i_sub.c
index ed49791f0..ed49791f0 100644
--- a/firmware/microblaze/apps/cruft/can_i_sub.c
+++ b/firmware/zpu/apps/cruft/can_i_sub.c
diff --git a/firmware/microblaze/apps/cruft/double_buffer_fragment.c b/firmware/zpu/apps/cruft/double_buffer_fragment.c
index cfc061247..cfc061247 100644
--- a/firmware/microblaze/apps/cruft/double_buffer_fragment.c
+++ b/firmware/zpu/apps/cruft/double_buffer_fragment.c
diff --git a/firmware/microblaze/apps/cruft/echo.c b/firmware/zpu/apps/cruft/echo.c
index 89108ee80..89108ee80 100644
--- a/firmware/microblaze/apps/cruft/echo.c
+++ b/firmware/zpu/apps/cruft/echo.c
diff --git a/firmware/microblaze/apps/cruft/eth_serdes.c b/firmware/zpu/apps/cruft/eth_serdes.c
index 2d2ddc1ca..2d2ddc1ca 100644
--- a/firmware/microblaze/apps/cruft/eth_serdes.c
+++ b/firmware/zpu/apps/cruft/eth_serdes.c
diff --git a/firmware/microblaze/apps/cruft/factory_test.c b/firmware/zpu/apps/cruft/factory_test.c
index e1fbb0e40..e1fbb0e40 100644
--- a/firmware/microblaze/apps/cruft/factory_test.c
+++ b/firmware/zpu/apps/cruft/factory_test.c
diff --git a/firmware/microblaze/apps/cruft/gen_eth_packets.c b/firmware/zpu/apps/cruft/gen_eth_packets.c
index 4d521f6bf..4d521f6bf 100644
--- a/firmware/microblaze/apps/cruft/gen_eth_packets.c
+++ b/firmware/zpu/apps/cruft/gen_eth_packets.c
diff --git a/firmware/microblaze/apps/cruft/gen_pause_frames.c b/firmware/zpu/apps/cruft/gen_pause_frames.c
index 0f81dafff..0f81dafff 100644
--- a/firmware/microblaze/apps/cruft/gen_pause_frames.c
+++ b/firmware/zpu/apps/cruft/gen_pause_frames.c
diff --git a/firmware/microblaze/apps/cruft/hello.c b/firmware/zpu/apps/cruft/hello.c
index bce843093..bce843093 100644
--- a/firmware/microblaze/apps/cruft/hello.c
+++ b/firmware/zpu/apps/cruft/hello.c
diff --git a/firmware/microblaze/apps/cruft/ibs_rx_test.c b/firmware/zpu/apps/cruft/ibs_rx_test.c
index bdc04747e..bdc04747e 100644
--- a/firmware/microblaze/apps/cruft/ibs_rx_test.c
+++ b/firmware/zpu/apps/cruft/ibs_rx_test.c
diff --git a/firmware/microblaze/apps/cruft/ibs_tx_test.c b/firmware/zpu/apps/cruft/ibs_tx_test.c
index ff9446d92..ff9446d92 100644
--- a/firmware/microblaze/apps/cruft/ibs_tx_test.c
+++ b/firmware/zpu/apps/cruft/ibs_tx_test.c
diff --git a/firmware/microblaze/apps/cruft/mimo_app_common_v2.c b/firmware/zpu/apps/cruft/mimo_app_common_v2.c
index 5dbecb0d0..5dbecb0d0 100644
--- a/firmware/microblaze/apps/cruft/mimo_app_common_v2.c
+++ b/firmware/zpu/apps/cruft/mimo_app_common_v2.c
diff --git a/firmware/microblaze/apps/cruft/mimo_app_common_v2.h b/firmware/zpu/apps/cruft/mimo_app_common_v2.h
index 1e62ced37..1e62ced37 100644
--- a/firmware/microblaze/apps/cruft/mimo_app_common_v2.h
+++ b/firmware/zpu/apps/cruft/mimo_app_common_v2.h
diff --git a/firmware/microblaze/apps/cruft/mimo_tx.c b/firmware/zpu/apps/cruft/mimo_tx.c
index e0f8aa6fa..e0f8aa6fa 100644
--- a/firmware/microblaze/apps/cruft/mimo_tx.c
+++ b/firmware/zpu/apps/cruft/mimo_tx.c
diff --git a/firmware/microblaze/apps/cruft/mimo_tx_slave.c b/firmware/zpu/apps/cruft/mimo_tx_slave.c
index cdf9c03c2..cdf9c03c2 100644
--- a/firmware/microblaze/apps/cruft/mimo_tx_slave.c
+++ b/firmware/zpu/apps/cruft/mimo_tx_slave.c
diff --git a/firmware/microblaze/apps/cruft/rcv_eth_packets.c b/firmware/zpu/apps/cruft/rcv_eth_packets.c
index 03fc94354..03fc94354 100644
--- a/firmware/microblaze/apps/cruft/rcv_eth_packets.c
+++ b/firmware/zpu/apps/cruft/rcv_eth_packets.c
diff --git a/firmware/microblaze/apps/cruft/read_dbids.c b/firmware/zpu/apps/cruft/read_dbids.c
index 24c6d9ab4..24c6d9ab4 100644
--- a/firmware/microblaze/apps/cruft/read_dbids.c
+++ b/firmware/zpu/apps/cruft/read_dbids.c
diff --git a/firmware/microblaze/apps/cruft/sd_bounce.c b/firmware/zpu/apps/cruft/sd_bounce.c
index c1b48f170..c1b48f170 100644
--- a/firmware/microblaze/apps/cruft/sd_bounce.c
+++ b/firmware/zpu/apps/cruft/sd_bounce.c
diff --git a/firmware/microblaze/apps/cruft/sd_gentest.c b/firmware/zpu/apps/cruft/sd_gentest.c
index 35e912615..35e912615 100644
--- a/firmware/microblaze/apps/cruft/sd_gentest.c
+++ b/firmware/zpu/apps/cruft/sd_gentest.c
diff --git a/firmware/microblaze/apps/cruft/serdes_to_dsp.c b/firmware/zpu/apps/cruft/serdes_to_dsp.c
index 4994e0a69..4994e0a69 100644
--- a/firmware/microblaze/apps/cruft/serdes_to_dsp.c
+++ b/firmware/zpu/apps/cruft/serdes_to_dsp.c
diff --git a/firmware/microblaze/apps/cruft/serdes_txrx.c b/firmware/zpu/apps/cruft/serdes_txrx.c
index 2c47c9628..2c47c9628 100644
--- a/firmware/microblaze/apps/cruft/serdes_txrx.c
+++ b/firmware/zpu/apps/cruft/serdes_txrx.c
diff --git a/firmware/microblaze/apps/cruft/set_hw_rev.c b/firmware/zpu/apps/cruft/set_hw_rev.c
index d4ac8ff81..d4ac8ff81 100644
--- a/firmware/microblaze/apps/cruft/set_hw_rev.c
+++ b/firmware/zpu/apps/cruft/set_hw_rev.c
diff --git a/firmware/microblaze/apps/cruft/test1.c b/firmware/zpu/apps/cruft/test1.c
index c3cc3be56..c3cc3be56 100644
--- a/firmware/microblaze/apps/cruft/test1.c
+++ b/firmware/zpu/apps/cruft/test1.c
diff --git a/firmware/microblaze/apps/cruft/test_db_spi.c b/firmware/zpu/apps/cruft/test_db_spi.c
index f4fa98ef1..f4fa98ef1 100644
--- a/firmware/microblaze/apps/cruft/test_db_spi.c
+++ b/firmware/zpu/apps/cruft/test_db_spi.c
diff --git a/firmware/microblaze/apps/cruft/test_i2c.c b/firmware/zpu/apps/cruft/test_i2c.c
index f349ead88..f349ead88 100644
--- a/firmware/microblaze/apps/cruft/test_i2c.c
+++ b/firmware/zpu/apps/cruft/test_i2c.c
diff --git a/firmware/microblaze/apps/cruft/test_lsadc.c b/firmware/zpu/apps/cruft/test_lsadc.c
index 5fda29cd7..5fda29cd7 100644
--- a/firmware/microblaze/apps/cruft/test_lsadc.c
+++ b/firmware/zpu/apps/cruft/test_lsadc.c
diff --git a/firmware/microblaze/apps/cruft/test_lsdac.c b/firmware/zpu/apps/cruft/test_lsdac.c
index 8c1bf333b..8c1bf333b 100644
--- a/firmware/microblaze/apps/cruft/test_lsdac.c
+++ b/firmware/zpu/apps/cruft/test_lsdac.c
diff --git a/firmware/microblaze/apps/cruft/test_phy_comm.c b/firmware/zpu/apps/cruft/test_phy_comm.c
index d312ca4cc..d312ca4cc 100644
--- a/firmware/microblaze/apps/cruft/test_phy_comm.c
+++ b/firmware/zpu/apps/cruft/test_phy_comm.c
diff --git a/firmware/microblaze/apps/cruft/test_ram.c b/firmware/zpu/apps/cruft/test_ram.c
index 77ee693f6..77ee693f6 100644
--- a/firmware/microblaze/apps/cruft/test_ram.c
+++ b/firmware/zpu/apps/cruft/test_ram.c
diff --git a/firmware/microblaze/apps/cruft/test_sd.c b/firmware/zpu/apps/cruft/test_sd.c
index 494432d7f..494432d7f 100644
--- a/firmware/microblaze/apps/cruft/test_sd.c
+++ b/firmware/zpu/apps/cruft/test_sd.c
diff --git a/firmware/microblaze/apps/cruft/timer_test.c b/firmware/zpu/apps/cruft/timer_test.c
index 44e80b5f1..44e80b5f1 100644
--- a/firmware/microblaze/apps/cruft/timer_test.c
+++ b/firmware/zpu/apps/cruft/timer_test.c
diff --git a/firmware/microblaze/apps/cruft/tx_standalone.c b/firmware/zpu/apps/cruft/tx_standalone.c
index 1645fa8ba..1645fa8ba 100644
--- a/firmware/microblaze/apps/cruft/tx_standalone.c
+++ b/firmware/zpu/apps/cruft/tx_standalone.c
diff --git a/firmware/microblaze/apps/flash_test.c b/firmware/zpu/apps/flash_test.c
index 5b4569030..5b4569030 100644
--- a/firmware/microblaze/apps/flash_test.c
+++ b/firmware/zpu/apps/flash_test.c
diff --git a/firmware/microblaze/apps/hardware_testbed.c b/firmware/zpu/apps/hardware_testbed.c
index e68e68ff7..e68e68ff7 100644
--- a/firmware/microblaze/apps/hardware_testbed.c
+++ b/firmware/zpu/apps/hardware_testbed.c
diff --git a/firmware/microblaze/apps/txrx_uhd.c b/firmware/zpu/apps/txrx_uhd.c
index 9c1873e1c..b16d177d7 100644
--- a/firmware/microblaze/apps/txrx_uhd.c
+++ b/firmware/zpu/apps/txrx_uhd.c
@@ -28,12 +28,10 @@
 #include "memory_map.h"
 #include "spi.h"
 #include "hal_io.h"
-#include "buffer_pool.h"
 #include "pic.h"
 #include <stdbool.h>
 #include "ethernet.h"
 #include "nonstdio.h"
-#include "dbsm.h"
 #include <net/padded_eth_hdr.h>
 #include <net_common.h>
 #include "memcpy_wa.h"
@@ -42,87 +40,12 @@
 #include <string.h>
 #include "clocks.h"
 #include "usrp2/fw_common.h"
-#include <i2c_async.h>
 #include <i2c.h>
 #include <ethertype.h>
 #include <arp_cache.h>
 #include "udp_fw_update.h"
-
-/*
- * Full duplex Tx and Rx between ethernet and DSP pipelines
- *
- * Buffer 1 is used by the cpu to send frames to the host.
- * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
- * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx  eth flow
- */
-//#define CPU_RX_BUF	0	// eth -> cpu
-
-#define	DSP_RX_BUF_0	2	// dsp rx -> eth (double buffer)
-#define	DSP_RX_BUF_1	3	// dsp rx -> eth
-#define	DSP_TX_BUF_0	4	// eth -> dsp tx (double buffer)
-#define	DSP_TX_BUF_1	5	// eth -> dsp tx
-
-/*
- * ================================================================
- *   configure DSP TX double buffering state machine (eth -> dsp)
- * ================================================================
- */
-
-// DSP Tx reads ethernet header words
-#define DSP_TX_FIRST_LINE ((sizeof(padded_eth_hdr_t) + sizeof(struct ip_hdr) + sizeof(struct udp_hdr))/sizeof(uint32_t))
-
-// Receive from ethernet
-buf_cmd_args_t dsp_tx_recv_args = {
-  PORT_ETH,
-  0,
-  BP_LAST_LINE
-};
-
-// send to DSP Tx
-buf_cmd_args_t dsp_tx_send_args = {
-  PORT_DSP,
-  DSP_TX_FIRST_LINE,	// starts just past transport header
-  0			// filled in from last_line register
-};
-
-dbsm_t dsp_tx_sm;	// the state machine
-
-/*
- * ================================================================
- *   configure DSP RX double buffering state machine (dsp -> eth)
- * ================================================================
- */
-
-static const uint32_t rx_ctrl_word = 1 << 16;
-
-// DSP Rx writes ethernet header words
-#define DSP_RX_FIRST_LINE sizeof(rx_ctrl_word)/sizeof(uint32_t)
-
-static bool dbsm_rx_inspector(dbsm_t *sm, int buf_this){
-    size_t num_lines = buffer_pool_status->last_line[buf_this]-DSP_RX_FIRST_LINE;
-    ((uint32_t*)buffer_ram(buf_this))[0] = (num_lines*sizeof(uint32_t)) | (1 << 16);
-    return false;
-}
-
-// receive from DSP
-buf_cmd_args_t dsp_rx_recv_args = {
-  PORT_DSP,
-  DSP_RX_FIRST_LINE,
-  BP_LAST_LINE
-};
-
-// send to ETH
-buf_cmd_args_t dsp_rx_send_args = {
-  PORT_ETH,
-  0,		// starts with ethernet header in line 0
-  0,		// filled in from list_line register
-};
-
-dbsm_t dsp_rx_sm;	// the state machine
-
-
-// The mac address of the host we're sending to.
-eth_mac_addr_t host_mac_addr;
+#include "pkt_ctrl.h"
+#include "banal.h"
 
 static void setup_network(void);
 
@@ -130,26 +53,28 @@ static void setup_network(void);
 // the fast-path setup global variables
 // ----------------------------------------------------------------
 static eth_mac_addr_t fp_mac_addr_src, fp_mac_addr_dst;
-static struct socket_address fp_socket_src, fp_socket_dst;
-
-// ----------------------------------------------------------------
-void start_rx_streaming_cmd(void);
-void stop_rx_cmd(void);
+extern struct socket_address fp_socket_src, fp_socket_dst;
 
-static void print_ip_addr(const void *t){
-    uint8_t *p = (uint8_t *)t;
-    printf("%d.%d.%d.%d", p[0], p[1], p[2], p[3]);
+static void handle_udp_err0_packet(
+    struct socket_address src, struct socket_address dst,
+    unsigned char *payload, int payload_len
+){
+    sr_udp_sm->err0_port = (((uint32_t)dst.port) << 16) | src.port;
+    printf("Storing for async error path:\n");
+    printf("  source udp port: %d\n", dst.port);
+    printf("  destination udp port: %d\n", src.port);
+    newline();
 }
 
-void handle_udp_data_packet(
+static void handle_udp_data_packet(
     struct socket_address src, struct socket_address dst,
     unsigned char *payload, int payload_len
 ){
-    //its a tiny payload, load the fast-path variables
     fp_mac_addr_src = *ethernet_mac_addr();
     arp_cache_lookup_mac(&src.addr, &fp_mac_addr_dst);
     fp_socket_src = dst;
     fp_socket_dst = src;
+    sr_udp_sm->dsp0_port = (((uint32_t)dst.port) << 16) | src.port;
     printf("Storing for fast path:\n");
     printf("  source mac addr: ");
     print_mac_addr(fp_mac_addr_src.addr); newline();
@@ -163,45 +88,15 @@ void handle_udp_data_packet(
     printf("  destination udp port: %d\n", fp_socket_dst.port);
     newline();
 
-    //setup network and vrt
+    //setup network
     setup_network();
 
-    // kick off the state machine
-    dbsm_start(&dsp_rx_sm);
-
 }
 
 #define OTW_GPIO_BANK_TO_NUM(bank) \
     (((bank) == USRP2_DIR_RX)? (GPIO_RX_BANK) : (GPIO_TX_BANK))
 
-//setup the output data
-static usrp2_ctrl_data_t ctrl_data_out;
-static struct socket_address i2c_src;
-static struct socket_address spi_src;
-
-static volatile bool i2c_done = false;
-void i2c_read_done_callback(void) {
-  //printf("I2C read done callback\n");
-  i2c_async_data_ready(ctrl_data_out.data.i2c_args.data);
-  i2c_done = true;
-  i2c_register_callback(0);
-}
-
-void i2c_write_done_callback(void) {
-  //printf("I2C write done callback\n");
-  i2c_done = true;
-  i2c_register_callback(0);
-}
-
-static volatile bool spi_done = false;
-static volatile uint32_t spi_readback_data;
-void get_spi_readback_data(void) {
-  ctrl_data_out.data.spi_args.data = spi_get_data();
-  spi_done = true;
-  spi_register_callback(0);
-}
-
-void handle_udp_ctrl_packet(
+static void handle_udp_ctrl_packet(
     struct socket_address src, struct socket_address dst,
     unsigned char *payload, int payload_len
 ){
@@ -226,6 +121,7 @@ void handle_udp_ctrl_packet(
     }
 
     //setup the output data
+    usrp2_ctrl_data_t ctrl_data_out;
     ctrl_data_out.proto_ver = USRP2_FW_COMPAT_NUM;
     ctrl_data_out.id=USRP2_CTRL_ID_HUH_WHAT;
     ctrl_data_out.seq=ctrl_data_in->seq;
@@ -239,7 +135,6 @@ void handle_udp_ctrl_packet(
     case USRP2_CTRL_ID_WAZZUP_BRO:
         ctrl_data_out.id = USRP2_CTRL_ID_WAZZUP_DUDE;
         memcpy(&ctrl_data_out.data.ip_addr, get_ip_addr(), sizeof(struct ip_addr));
-        send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
         break;
 
     /*******************************************************************
@@ -247,21 +142,19 @@ void handle_udp_ctrl_packet(
      ******************************************************************/
     case USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO:{
             //transact
-            bool success = spi_async_transact(
-                //(ctrl_data_in->data.spi_args.readback == 0)? SPI_TXONLY : SPI_TXRX,
+            uint32_t result = spi_transact(
+                (ctrl_data_in->data.spi_args.readback == 0)? SPI_TXONLY : SPI_TXRX,
                 ctrl_data_in->data.spi_args.dev,      //which device
                 ctrl_data_in->data.spi_args.data,     //32 bit data
                 ctrl_data_in->data.spi_args.num_bits, //length in bits
-                (ctrl_data_in->data.spi_args.mosi_edge == USRP2_CLK_EDGE_RISE)? SPIF_PUSH_FALL : SPIF_PUSH_RISE | //flags
-                (ctrl_data_in->data.spi_args.miso_edge == USRP2_CLK_EDGE_RISE)? SPIF_LATCH_RISE : SPIF_LATCH_FALL,
-                get_spi_readback_data //callback
+                (ctrl_data_in->data.spi_args.mosi_edge == USRP2_CLK_EDGE_RISE)? SPIF_PUSH_FALL : SPIF_PUSH_RISE |
+                (ctrl_data_in->data.spi_args.miso_edge == USRP2_CLK_EDGE_RISE)? SPIF_LATCH_RISE : SPIF_LATCH_FALL
             );
 
             //load output
+            ctrl_data_out.data.spi_args.data = result;
             ctrl_data_out.id = USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE;
-            spi_src = src;
         }
-//        send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
         break;
 
     /*******************************************************************
@@ -269,13 +162,11 @@ void handle_udp_ctrl_packet(
      ******************************************************************/
     case USRP2_CTRL_ID_DO_AN_I2C_READ_FOR_ME_BRO:{
             uint8_t num_bytes = ctrl_data_in->data.i2c_args.bytes;
-            i2c_register_callback(i2c_read_done_callback);
-            i2c_async_read(
+            i2c_read(
                 ctrl_data_in->data.i2c_args.addr,
+                ctrl_data_out.data.i2c_args.data,
                 num_bytes
             );
-            i2c_src = src;
-//            i2c_dst = dst;
             ctrl_data_out.id = USRP2_CTRL_ID_HERES_THE_I2C_DATA_DUDE;
             ctrl_data_out.data.i2c_args.bytes = num_bytes;
         }
@@ -283,14 +174,11 @@ void handle_udp_ctrl_packet(
 
     case USRP2_CTRL_ID_WRITE_THESE_I2C_VALUES_BRO:{
             uint8_t num_bytes = ctrl_data_in->data.i2c_args.bytes;
-            i2c_register_callback(i2c_read_done_callback);
-            i2c_async_write(
+            i2c_write(
                 ctrl_data_in->data.i2c_args.addr,
                 ctrl_data_in->data.i2c_args.data,
                 num_bytes
             );
-            i2c_src = src;
-//            i2c_dst = dst;
             ctrl_data_out.id = USRP2_CTRL_ID_COOL_IM_DONE_I2C_WRITE_DUDE;
             ctrl_data_out.data.i2c_args.bytes = num_bytes;
         }
@@ -322,7 +210,6 @@ void handle_udp_ctrl_packet(
 
         }
         ctrl_data_out.id = USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE;
-        send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
         break;
 
     case USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO:
@@ -345,7 +232,6 @@ void handle_udp_ctrl_packet(
 
         }
         ctrl_data_out.id = USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE;
-        send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
         break;
 
     case USRP2_CTRL_ID_SO_LIKE_CAN_YOU_READ_THIS_UART_BRO:{
@@ -372,32 +258,11 @@ void handle_udp_ctrl_packet(
 
     default:
         ctrl_data_out.id = USRP2_CTRL_ID_HUH_WHAT;
-        send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
     }
-    
+    send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out));
 }
 
-/*
- * Called when an ethernet packet is received.
- * Return true if we handled it here, otherwise
- * it'll be passed on to the DSP Tx pipe
- */
-static bool
-eth_pkt_inspector(dbsm_t *sm, int bufno)
-{
-  //point me to the ethernet frame
-  uint32_t *buff = (uint32_t *)buffer_ram(bufno);
-
-  //treat this as fast-path data?
-  // We have to do this operation as fast as possible.
-  // Therefore, we do not check all the headers,
-  // just check that the udp port matches
-  // and that the vrt header is non zero.
-  // In the future, a hardware state machine will do this...
-  if ( //warning! magic numbers approaching....
-      (((buff + ((2 + 14 + 20)/sizeof(uint32_t)))[0] & 0xffff) == USRP2_UDP_DATA_PORT) &&
-      ((buff + ((2 + 14 + 20 + 8)/sizeof(uint32_t)))[1] != USRP2_INVALID_VRT_HEADER)
-  ) return false;
+static void handle_inp_packet(uint32_t *buff, size_t num_lines){
 
   //test if its an ip recovery packet
   typedef struct{
@@ -411,42 +276,30 @@ eth_pkt_inspector(dbsm_t *sm, int bufno)
   if (recovery_packet->eth_hdr.ethertype == 0xbeee && strncmp(recovery_packet->code, "addr", 4) == 0){
       printf("Got ip recovery packet: "); print_ip_addr(&recovery_packet->data.ip_addr); newline();
       set_ip_addr(&recovery_packet->data.ip_addr);
-      return true;
+      return;
   }
 
   //pass it to the slow-path handler
-  size_t len = buffer_pool_status->last_line[bufno] - 3;
-  handle_eth_packet(buff, len);
-  return true;
+  handle_eth_packet(buff, num_lines);
 }
 
-//------------------------------------------------------------------
 
-/*
- * 1's complement sum for IP and UDP headers
- *
- * init chksum to zero to start.
- */
-static unsigned int
-CHKSUM(unsigned int x, unsigned int *chksum)
-{
-  *chksum += x;
-  *chksum = (*chksum & 0xffff) + (*chksum>>16);
-  *chksum = (*chksum & 0xffff) + (*chksum>>16);
-  return x;
-}
+//------------------------------------------------------------------
 
 /*
  * Called when eth phy state changes (w/ interrupts disabled)
  */
-volatile bool link_is_up = false;	// eth handler sets this
-void
-link_changed_callback(int speed)
-{
-  link_is_up = speed != 0;
-  hal_set_leds(link_is_up ? LED_RJ45 : 0x0, LED_RJ45);
-  printf("\neth link changed: speed = %d\n", speed);
-  if (link_is_up) send_gratuitous_arp();
+void link_changed_callback(int speed){
+    printf("\neth link changed: speed = %d\n", speed);
+    if (speed != 0){
+        hal_set_leds(LED_RJ45, LED_RJ45);
+        pkt_ctrl_set_routing_mode(PKT_CTRL_ROUTING_MODE_MASTER);
+        send_gratuitous_arp();
+    }
+    else{
+        hal_set_leds(0x0, LED_RJ45);
+        pkt_ctrl_set_routing_mode(PKT_CTRL_ROUTING_MODE_SLAVE);
+    }
 }
 
 static void setup_network(void){
@@ -477,21 +330,12 @@ static void setup_network(void){
   sr_udp_sm->ip_hdr.checksum = UDP_SM_INS_IP_HDR_CHKSUM | (chksum & 0xffff);
 
   //setup the udp header machine
-  sr_udp_sm->udp_hdr.src_port = fp_socket_src.port;
-  sr_udp_sm->udp_hdr.dst_port = fp_socket_dst.port;
+  sr_udp_sm->udp_hdr.src_port = UDP_SM_INS_UDP_SRC_PORT;
+  sr_udp_sm->udp_hdr.dst_port = UDP_SM_INS_UDP_DST_PORT;
   sr_udp_sm->udp_hdr.length = UDP_SM_INS_UDP_LEN;
   sr_udp_sm->udp_hdr.checksum = UDP_SM_LAST_WORD;		// zero UDP checksum
 }
 
-inline static void
-buffer_irq_handler(unsigned irq)
-{
-  uint32_t  status = buffer_pool_status->status;
-
-  dbsm_process_status(&dsp_tx_sm, status);
-  dbsm_process_status(&dsp_rx_sm, status);
-}
-
 int
 main(void)
 {
@@ -515,72 +359,43 @@ main(void)
   printf("Firmware compatibility number: %d\n", USRP2_FW_COMPAT_NUM);
 
   //1) register the addresses into the network stack
-  register_mac_addr(ethernet_mac_addr());
-  register_ip_addr(get_ip_addr());
-  
+  register_addrs(ethernet_mac_addr(), get_ip_addr());
+  pkt_ctrl_program_inspector(get_ip_addr(), USRP2_UDP_DATA_PORT);
+
   //2) register callbacks for udp ports we service
+  init_udp_listeners();
   register_udp_listener(USRP2_UDP_CTRL_PORT, handle_udp_ctrl_packet);
   register_udp_listener(USRP2_UDP_DATA_PORT, handle_udp_data_packet);
+  register_udp_listener(USRP2_UDP_ERR0_PORT, handle_udp_err0_packet);
   register_udp_listener(USRP2_UDP_UPDATE_PORT, handle_udp_fw_update_packet);
 
-  //3) setup ethernet hardware to bring the link up
+  //3) set the routing mode to slave and send a garp
+  pkt_ctrl_set_routing_mode(PKT_CTRL_ROUTING_MODE_SLAVE);
+  send_gratuitous_arp();
+
+  //4) setup ethernet hardware to bring the link up
   ethernet_register_link_changed_callback(link_changed_callback);
   ethernet_init();
 
-  // initialize double buffering state machine for ethernet -> DSP Tx
-
-  dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
-	    &dsp_tx_recv_args, &dsp_tx_send_args,
-	    eth_pkt_inspector);
-
-
-  // initialize double buffering state machine for DSP RX -> Ethernet
-
-    dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
-	      &dsp_rx_recv_args, &dsp_rx_send_args,
-	      dbsm_rx_inspector);
-
-  sr_tx_ctrl->clear_state = 1;
-  bp_clear_buf(DSP_TX_BUF_0);
-  bp_clear_buf(DSP_TX_BUF_1);
+  while(true){
 
-  // kick off the state machine
-  dbsm_start(&dsp_tx_sm);
-
-  //int which = 0;
-
-  while(1){
-    // hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
-    // which ^= 0x8000;
-
-    buffer_irq_handler(0);
-
-    if(i2c_done) {
-      i2c_done = false;
-      send_udp_pkt(USRP2_UDP_CTRL_PORT, i2c_src, &ctrl_data_out, sizeof(ctrl_data_out));
-      //printf("Sending UDP packet from main loop for I2C...\n");
-    }
-
-    if(spi_done) {
-      spi_done = false;
-      send_udp_pkt(USRP2_UDP_CTRL_PORT, spi_src, &ctrl_data_out, sizeof(ctrl_data_out));
+    size_t num_lines;
+    void *buff = pkt_ctrl_claim_incoming_buffer(&num_lines);
+    if (buff != NULL){
+        handle_inp_packet((uint32_t *)buff, num_lines);
+        pkt_ctrl_release_incoming_buffer();
     }
 
+    pic_interrupt_handler();
     int pending = pic_regs->pending;		// poll for under or overrun
 
     if (pending & PIC_UNDERRUN_INT){
-      //dbsm_handle_tx_underrun(&dsp_tx_sm);
       pic_regs->pending = PIC_UNDERRUN_INT;	// clear interrupt
       putchar('U');
     }
 
     if (pending & PIC_OVERRUN_INT){
-      //dbsm_handle_rx_overrun(&dsp_rx_sm);
       pic_regs->pending = PIC_OVERRUN_INT;	// clear pending interrupt
-
-      // FIXME Figure out how to handle this robustly.
-      // Any buffers that are emptying should be allowed to drain...
-
       putchar('O');
     }
   }
diff --git a/firmware/microblaze/apps/uart_flash_loader.c b/firmware/zpu/apps/uart_flash_loader.c
index d67b84677..4ec89284a 100644
--- a/firmware/microblaze/apps/uart_flash_loader.c
+++ b/firmware/zpu/apps/uart_flash_loader.c
@@ -139,8 +139,8 @@ void delay(uint32_t t) {
 }
 
 int main(int argc, char *argv[]) {
-	uint8_t buf[32];
-	int i = 0;
+	//uint8_t buf[32];
+	//int i = 0;
 
   hal_disable_ints();	// In case we got here via jmp 0x0
 
diff --git a/firmware/microblaze/bin/bin_to_mif.py b/firmware/zpu/bin/bin_to_mif.py
index cefce4e92..cefce4e92 100755
--- a/firmware/microblaze/bin/bin_to_mif.py
+++ b/firmware/zpu/bin/bin_to_mif.py
diff --git a/firmware/microblaze/bin/bin_to_ram_macro_init.py b/firmware/zpu/bin/bin_to_ram_macro_init.py
index 65cf2dbdf..65cf2dbdf 100755
--- a/firmware/microblaze/bin/bin_to_ram_macro_init.py
+++ b/firmware/zpu/bin/bin_to_ram_macro_init.py
diff --git a/firmware/microblaze/bin/elf_to_sbf b/firmware/zpu/bin/elf_to_sbf
index d1be10c0d..d1be10c0d 100755
--- a/firmware/microblaze/bin/elf_to_sbf
+++ b/firmware/zpu/bin/elf_to_sbf
diff --git a/firmware/microblaze/bin/sbf.py b/firmware/zpu/bin/sbf.py
index 8e2c868a5..8e2c868a5 100644
--- a/firmware/microblaze/bin/sbf.py
+++ b/firmware/zpu/bin/sbf.py
diff --git a/firmware/microblaze/bin/serial_loader b/firmware/zpu/bin/serial_loader
index 9bd5aada7..9bd5aada7 100755
--- a/firmware/microblaze/bin/serial_loader
+++ b/firmware/zpu/bin/serial_loader
diff --git a/firmware/microblaze/bin/uart_ihex_flash_loader.py b/firmware/zpu/bin/uart_ihex_flash_loader.py
index 5a3300f34..5a3300f34 100755
--- a/firmware/microblaze/bin/uart_ihex_flash_loader.py
+++ b/firmware/zpu/bin/uart_ihex_flash_loader.py
diff --git a/firmware/microblaze/bin/uart_ihex_ram_loader.py b/firmware/zpu/bin/uart_ihex_ram_loader.py
index c90fbe1d8..c90fbe1d8 100755
--- a/firmware/microblaze/bin/uart_ihex_ram_loader.py
+++ b/firmware/zpu/bin/uart_ihex_ram_loader.py
diff --git a/firmware/microblaze/divisors.py b/firmware/zpu/divisors.py
index d31bd4dad..d31bd4dad 100755
--- a/firmware/microblaze/divisors.py
+++ b/firmware/zpu/divisors.py
diff --git a/firmware/zpu/lib/CMakeLists.txt b/firmware/zpu/lib/CMakeLists.txt
new file mode 100644
index 000000000..193d63cfa
--- /dev/null
+++ b/firmware/zpu/lib/CMakeLists.txt
@@ -0,0 +1,47 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+SET(COMMON_SRCS
+    ${CMAKE_SOURCE_DIR}/lib/u2_init.c
+    ${CMAKE_SOURCE_DIR}/lib/abort.c
+    ${CMAKE_SOURCE_DIR}/lib/ad9510.c
+    ${CMAKE_SOURCE_DIR}/lib/clocks.c
+    ${CMAKE_SOURCE_DIR}/lib/eeprom.c
+    ${CMAKE_SOURCE_DIR}/lib/eth_addrs.c
+    ${CMAKE_SOURCE_DIR}/lib/eth_mac.c
+    ${CMAKE_SOURCE_DIR}/lib/_exit.c
+    ${CMAKE_SOURCE_DIR}/lib/exit.c
+    ${CMAKE_SOURCE_DIR}/lib/hal_io.c
+    ${CMAKE_SOURCE_DIR}/lib/hal_uart.c
+    ${CMAKE_SOURCE_DIR}/lib/i2c.c
+    ${CMAKE_SOURCE_DIR}/lib/mdelay.c
+    ${CMAKE_SOURCE_DIR}/lib/memcpy_wa.c
+    ${CMAKE_SOURCE_DIR}/lib/memset_wa.c
+    ${CMAKE_SOURCE_DIR}/lib/nonstdio.c
+    ${CMAKE_SOURCE_DIR}/lib/pic.c
+    ${CMAKE_SOURCE_DIR}/lib/pkt_ctrl.c
+    ${CMAKE_SOURCE_DIR}/lib/print_addrs.c
+    ${CMAKE_SOURCE_DIR}/lib/print_rmon_regs.c
+    ${CMAKE_SOURCE_DIR}/lib/print_buffer.c
+    ${CMAKE_SOURCE_DIR}/lib/printf.c
+    ${CMAKE_SOURCE_DIR}/lib/ihex.c
+    ${CMAKE_SOURCE_DIR}/lib/spi.c
+    ${CMAKE_SOURCE_DIR}/lib/net_common.c
+    ${CMAKE_SOURCE_DIR}/lib/arp_cache.c
+    ${CMAKE_SOURCE_DIR}/lib/banal.c
+)
diff --git a/firmware/microblaze/lib/_exit.c b/firmware/zpu/lib/_exit.c
index 9b40ab2ee..9b40ab2ee 100644
--- a/firmware/microblaze/lib/_exit.c
+++ b/firmware/zpu/lib/_exit.c
diff --git a/firmware/microblaze/lib/abort.c b/firmware/zpu/lib/abort.c
index d1d709392..d1d709392 100644
--- a/firmware/microblaze/lib/abort.c
+++ b/firmware/zpu/lib/abort.c
diff --git a/firmware/microblaze/lib/ad9510.c b/firmware/zpu/lib/ad9510.c
index 4d3acb65d..4d3acb65d 100644
--- a/firmware/microblaze/lib/ad9510.c
+++ b/firmware/zpu/lib/ad9510.c
diff --git a/firmware/microblaze/lib/ad9510.h b/firmware/zpu/lib/ad9510.h
index a395e5223..a395e5223 100644
--- a/firmware/microblaze/lib/ad9510.h
+++ b/firmware/zpu/lib/ad9510.h
diff --git a/firmware/microblaze/lib/arp_cache.c b/firmware/zpu/lib/arp_cache.c
index 9c586fa6b..9c586fa6b 100644
--- a/firmware/microblaze/lib/arp_cache.c
+++ b/firmware/zpu/lib/arp_cache.c
diff --git a/firmware/microblaze/lib/arp_cache.h b/firmware/zpu/lib/arp_cache.h
index 8e84a1f94..8e84a1f94 100644
--- a/firmware/microblaze/lib/arp_cache.h
+++ b/firmware/zpu/lib/arp_cache.h
diff --git a/firmware/microblaze/lib/banal.c b/firmware/zpu/lib/banal.c
index 42937957f..42937957f 100644
--- a/firmware/microblaze/lib/banal.c
+++ b/firmware/zpu/lib/banal.c
diff --git a/firmware/microblaze/lib/banal.h b/firmware/zpu/lib/banal.h
index 7b3c71a20..eb7ed509a 100644
--- a/firmware/microblaze/lib/banal.h
+++ b/firmware/zpu/lib/banal.h
@@ -19,24 +19,8 @@
 #define INCLUDED_BANAL_H
 
 #include <stdint.h>
-#include <lwip/ip_addr.h>
 
-/*
- * 1's complement sum for IP and UDP headers
- *
- * init chksum to zero to start.
- */
-static inline unsigned int
-CHKSUM(unsigned int x, unsigned int *chksum)
-{
-  *chksum += x;
-  *chksum = (*chksum & 0xffff) + (*chksum>>16);
-  *chksum = (*chksum & 0xffff) + (*chksum>>16);
-  return x;
-}
-
-unsigned int 
-chksum_buffer(unsigned short *buf, int nshorts, unsigned int initial_chksum);
+#define dimof(x) (sizeof(x)/sizeof(x[0]))
 
 //-------------- unsigned get_int 8, 16, 32, 64 --------------//
 
@@ -84,7 +68,4 @@ get_int64(const unsigned char *s)
   return get_uint64(s);
 }
 
-void
-print_ip(struct ip_addr ip);
-
 #endif /* INCLUDED_BANAL_H */
diff --git a/firmware/microblaze/lib/bootconfig.c b/firmware/zpu/lib/bootconfig.c
index 93adc05c2..93adc05c2 100644
--- a/firmware/microblaze/lib/bootconfig.c
+++ b/firmware/zpu/lib/bootconfig.c
diff --git a/firmware/microblaze/lib/clock_bits.h b/firmware/zpu/lib/clock_bits.h
index d2052e941..d2052e941 100644
--- a/firmware/microblaze/lib/clock_bits.h
+++ b/firmware/zpu/lib/clock_bits.h
diff --git a/firmware/microblaze/lib/clocks.c b/firmware/zpu/lib/clocks.c
index 2b352a385..2b352a385 100644
--- a/firmware/microblaze/lib/clocks.c
+++ b/firmware/zpu/lib/clocks.c
diff --git a/firmware/microblaze/lib/clocks.h b/firmware/zpu/lib/clocks.h
index 28d1d542f..28d1d542f 100644
--- a/firmware/microblaze/lib/clocks.h
+++ b/firmware/zpu/lib/clocks.h
diff --git a/firmware/microblaze/lib/compiler.h b/firmware/zpu/lib/compiler.h
index 4fa9b49f8..f677bdc3b 100644
--- a/firmware/microblaze/lib/compiler.h
+++ b/firmware/zpu/lib/compiler.h
@@ -1,6 +1,6 @@
 /* -*- c++ -*- */
 /*
- * Copyright 2009 Ettus Research LLC
+ * Copyright 2009, 2010 Ettus Research LLC
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,5 +21,6 @@
 // FIXME gcc specific.
 #define _AL4   __attribute__((aligned (4)))
 
+#define FORCE_INLINE inline __attribute__((always_inline))
 
 #endif /* INCLUDED_COMPILER_H */
diff --git a/firmware/microblaze/lib/eeprom.c b/firmware/zpu/lib/eeprom.c
index d4e170046..d4e170046 100644
--- a/firmware/microblaze/lib/eeprom.c
+++ b/firmware/zpu/lib/eeprom.c
diff --git a/firmware/microblaze/lib/eth_addrs.c b/firmware/zpu/lib/eth_addrs.c
index ff5d04f4d..ff5d04f4d 100644
--- a/firmware/microblaze/lib/eth_addrs.c
+++ b/firmware/zpu/lib/eth_addrs.c
diff --git a/firmware/microblaze/lib/eth_mac.c b/firmware/zpu/lib/eth_mac.c
index 034a4d494..581a5c69f 100644
--- a/firmware/microblaze/lib/eth_mac.c
+++ b/firmware/zpu/lib/eth_mac.c
@@ -28,6 +28,7 @@
 void
 eth_mac_set_addr(const eth_mac_addr_t *src)
 {
+  /* disable because MAC_SET_PASS_ALL is set below
   eth_mac->ucast_hi = 
     (((unsigned int)src->addr[0])<<8) + 
     ((unsigned int)src->addr[1]);
@@ -36,6 +37,7 @@ eth_mac_set_addr(const eth_mac_addr_t *src)
     (((unsigned int)src->addr[3])<<16) +
     (((unsigned int)src->addr[4])<<8) +
     (((unsigned int)src->addr[5]));
+*/
 }
 
 
@@ -45,7 +47,7 @@ eth_mac_init(const eth_mac_addr_t *src)
   eth_mac->miimoder = 25;	// divider from CPU clock (50MHz/25 = 2MHz)
 
   eth_mac_set_addr(src);
-  eth_mac->settings = MAC_SET_PAUSE_EN | MAC_SET_PASS_BCAST | MAC_SET_PASS_UCAST | MAC_SET_PAUSE_SEND_EN; 
+  eth_mac->settings = MAC_SET_PAUSE_EN | MAC_SET_PASS_BCAST | MAC_SET_PASS_UCAST | MAC_SET_PAUSE_SEND_EN | MAC_SET_PASS_ALL;
 
   eth_mac->pause_time = 38;
   eth_mac->pause_thresh = 1200;
diff --git a/firmware/microblaze/lib/eth_mac.h b/firmware/zpu/lib/eth_mac.h
index 73feec955..73feec955 100644
--- a/firmware/microblaze/lib/eth_mac.h
+++ b/firmware/zpu/lib/eth_mac.h
diff --git a/firmware/microblaze/lib/eth_mac_regs.h b/firmware/zpu/lib/eth_mac_regs.h
index d680f8de0..d680f8de0 100644
--- a/firmware/microblaze/lib/eth_mac_regs.h
+++ b/firmware/zpu/lib/eth_mac_regs.h
diff --git a/firmware/microblaze/lib/ethernet.h b/firmware/zpu/lib/ethernet.h
index 52b297349..52b297349 100644
--- a/firmware/microblaze/lib/ethernet.h
+++ b/firmware/zpu/lib/ethernet.h
diff --git a/firmware/microblaze/lib/ethertype.h b/firmware/zpu/lib/ethertype.h
index 11f4bafec..11f4bafec 100644
--- a/firmware/microblaze/lib/ethertype.h
+++ b/firmware/zpu/lib/ethertype.h
diff --git a/firmware/microblaze/lib/exit.c b/firmware/zpu/lib/exit.c
index 95a3bf4de..95a3bf4de 100644
--- a/firmware/microblaze/lib/exit.c
+++ b/firmware/zpu/lib/exit.c
diff --git a/firmware/microblaze/lib/gdbstub2.c b/firmware/zpu/lib/gdbstub2.c
index 4c63dfce2..4c63dfce2 100644
--- a/firmware/microblaze/lib/gdbstub2.c
+++ b/firmware/zpu/lib/gdbstub2.c
diff --git a/firmware/microblaze/lib/gdbstub2.h b/firmware/zpu/lib/gdbstub2.h
index 15cdde939..15cdde939 100644
--- a/firmware/microblaze/lib/gdbstub2.h
+++ b/firmware/zpu/lib/gdbstub2.h
diff --git a/firmware/microblaze/lib/hal_io.c b/firmware/zpu/lib/hal_io.c
index be4c570c7..be4c570c7 100644
--- a/firmware/microblaze/lib/hal_io.c
+++ b/firmware/zpu/lib/hal_io.c
diff --git a/firmware/microblaze/lib/hal_io.h b/firmware/zpu/lib/hal_io.h
index 950f8d591..574df7d3e 100644
--- a/firmware/microblaze/lib/hal_io.h
+++ b/firmware/zpu/lib/hal_io.h
@@ -70,13 +70,7 @@ hal_set_timeout(int delta_ticks)
 static inline int
 hal_disable_ints(void)
 {
-  int result, t0;
-
-  asm volatile("mfs   %0, rmsr       \n\
-		andni %1, %0, 0x2    \n\
-		mts   rmsr, %1"
-	       : "=r" (result), "=r" (t0));
-  return result;
+  return 0; /* NOP */
 }
 
 /*!
@@ -86,13 +80,7 @@ hal_disable_ints(void)
 static inline int
 hal_enable_ints(void)
 {
-  int result, t0;
-
-  asm volatile("mfs  %0, rmsr	      \n\
-		ori  %1, %0, 0x2      \n\
-		mts  rmsr, %1"
-	       : "=r" (result), "=r" (t0));
-  return result;
+  return 0; /* NOP */
 }
 
 /*!
@@ -102,13 +90,7 @@ hal_enable_ints(void)
 static inline void
 hal_restore_ints(int prev_state)
 {
-  int t0, t1;
-  asm volatile("andi  %0, %2, 0x2	\n\
-		mfs   %1, rmsr          \n\
-		andni %1, %1, 0x2	\n\
-		or    %1, %1, %0	\n\
-		mts   rmsr, %1"
-	       : "=r" (t0), "=r"(t1) : "r" (prev_state));
+    /* NOP */
 }
 
 #endif /* INCLUDED_HAL_IO_H */
diff --git a/firmware/microblaze/lib/hal_uart.c b/firmware/zpu/lib/hal_uart.c
index 7836240fe..f0921f4f0 100644
--- a/firmware/microblaze/lib/hal_uart.c
+++ b/firmware/zpu/lib/hal_uart.c
@@ -113,7 +113,7 @@ hal_uart_getc_timeout(hal_uart_name_t u)
 
 int hal_uart_rx_flush(hal_uart_name_t u)
 {
-  char x;
+  char x = 0;
   while(uart_regs[u].rxlevel) x = uart_regs[u].rxchar;
   return x;
 }
diff --git a/firmware/microblaze/lib/hal_uart.h b/firmware/zpu/lib/hal_uart.h
index 758c8cb5e..758c8cb5e 100644
--- a/firmware/microblaze/lib/hal_uart.h
+++ b/firmware/zpu/lib/hal_uart.h
diff --git a/firmware/microblaze/lib/i2c.c b/firmware/zpu/lib/i2c.c
index d230f462c..d230f462c 100644
--- a/firmware/microblaze/lib/i2c.c
+++ b/firmware/zpu/lib/i2c.c
diff --git a/firmware/microblaze/lib/i2c.h b/firmware/zpu/lib/i2c.h
index 1af4d72df..1af4d72df 100644
--- a/firmware/microblaze/lib/i2c.h
+++ b/firmware/zpu/lib/i2c.h
diff --git a/firmware/microblaze/lib/i2c_async.c b/firmware/zpu/lib/i2c_async.c
index 05c4c3a09..05c4c3a09 100644
--- a/firmware/microblaze/lib/i2c_async.c
+++ b/firmware/zpu/lib/i2c_async.c
diff --git a/firmware/microblaze/lib/i2c_async.h b/firmware/zpu/lib/i2c_async.h
index e6095fca6..e6095fca6 100644
--- a/firmware/microblaze/lib/i2c_async.h
+++ b/firmware/zpu/lib/i2c_async.h
diff --git a/firmware/microblaze/lib/if_arp.h b/firmware/zpu/lib/if_arp.h
index 63519c4be..63519c4be 100644
--- a/firmware/microblaze/lib/if_arp.h
+++ b/firmware/zpu/lib/if_arp.h
diff --git a/firmware/microblaze/lib/ihex.c b/firmware/zpu/lib/ihex.c
index 97ecf73b6..97ecf73b6 100644
--- a/firmware/microblaze/lib/ihex.c
+++ b/firmware/zpu/lib/ihex.c
diff --git a/firmware/microblaze/lib/ihex.h b/firmware/zpu/lib/ihex.h
index 9f471fbe2..9f471fbe2 100644
--- a/firmware/microblaze/lib/ihex.h
+++ b/firmware/zpu/lib/ihex.h
diff --git a/firmware/microblaze/lib/mdelay.c b/firmware/zpu/lib/mdelay.c
index c8c119b1a..958acf3f5 100644
--- a/firmware/microblaze/lib/mdelay.c
+++ b/firmware/zpu/lib/mdelay.c
@@ -30,7 +30,7 @@
 inline static void
 delay_1ms(int loop_count)
 {
-  int	i;
+/*  int	i;
   for (i = 0; i < loop_count; i++){
     asm volatile ("or  r0, r0, r0\n\
 		   or  r0, r0, r0\n\
@@ -40,6 +40,7 @@ delay_1ms(int loop_count)
 		   or  r0, r0, r0\n\
 		   or  r0, r0, r0\n");
   }
+*/
 }
 
 // delay about ms milliseconds
diff --git a/firmware/microblaze/lib/mdelay.h b/firmware/zpu/lib/mdelay.h
index 226bbb3f7..226bbb3f7 100644
--- a/firmware/microblaze/lib/mdelay.h
+++ b/firmware/zpu/lib/mdelay.h
diff --git a/firmware/microblaze/lib/memcpy_wa.c b/firmware/zpu/lib/memcpy_wa.c
index ef20efaa9..ef20efaa9 100644
--- a/firmware/microblaze/lib/memcpy_wa.c
+++ b/firmware/zpu/lib/memcpy_wa.c
diff --git a/firmware/microblaze/lib/memcpy_wa.h b/firmware/zpu/lib/memcpy_wa.h
index 072fc148f..072fc148f 100644
--- a/firmware/microblaze/lib/memcpy_wa.h
+++ b/firmware/zpu/lib/memcpy_wa.h
diff --git a/firmware/microblaze/lib/memset_wa.c b/firmware/zpu/lib/memset_wa.c
index da5da21ab..da5da21ab 100644
--- a/firmware/microblaze/lib/memset_wa.c
+++ b/firmware/zpu/lib/memset_wa.c
diff --git a/firmware/microblaze/lib/memset_wa.h b/firmware/zpu/lib/memset_wa.h
index 46d903d53..46d903d53 100644
--- a/firmware/microblaze/lib/memset_wa.h
+++ b/firmware/zpu/lib/memset_wa.h
diff --git a/firmware/microblaze/lib/net/eth_mac_addr.h b/firmware/zpu/lib/net/eth_mac_addr.h
index b44fb68f7..b44fb68f7 100644
--- a/firmware/microblaze/lib/net/eth_mac_addr.h
+++ b/firmware/zpu/lib/net/eth_mac_addr.h
diff --git a/firmware/microblaze/lib/net/padded_eth_hdr.h b/firmware/zpu/lib/net/padded_eth_hdr.h
index df816734f..df816734f 100644
--- a/firmware/microblaze/lib/net/padded_eth_hdr.h
+++ b/firmware/zpu/lib/net/padded_eth_hdr.h
diff --git a/firmware/microblaze/lib/net/socket_address.h b/firmware/zpu/lib/net/socket_address.h
index 336f30a0c..336f30a0c 100644
--- a/firmware/microblaze/lib/net/socket_address.h
+++ b/firmware/zpu/lib/net/socket_address.h
diff --git a/firmware/microblaze/lib/net_common.c b/firmware/zpu/lib/net_common.c
index 6305408d6..c1ca280d9 100644
--- a/firmware/microblaze/lib/net_common.c
+++ b/firmware/zpu/lib/net_common.c
@@ -22,7 +22,6 @@
 #include "net_common.h"
 #include "banal.h"
 #include <hal_io.h>
-#include <buffer_pool.h>
 #include <memory_map.h>
 #include <memcpy_wa.h>
 #include <ethernet.h>
@@ -36,28 +35,21 @@
 #include "if_arp.h"
 #include <ethertype.h>
 #include <string.h>
+#include "pkt_ctrl.h"
 
+static const bool debug = false;
 
-int cpu_tx_buf_dest_port = PORT_ETH;
+static const eth_mac_addr_t BCAST_MAC_ADDR = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
 
-// If this is non-zero, this dbsm could be writing to the ethernet
-dbsm_t *ac_could_be_sending_to_eth;
-
-static inline bool
-ip_addr_eq(const struct ip_addr a, const struct ip_addr b)
-{
-  return a.addr == b.addr;
-}
+//used in the top level application...
+struct socket_address fp_socket_src, fp_socket_dst;
 
 // ------------------------------------------------------------------------
 
 static eth_mac_addr_t _local_mac_addr;
-void register_mac_addr(const eth_mac_addr_t *mac_addr){
-    _local_mac_addr = *mac_addr;
-}
-
 static struct ip_addr _local_ip_addr;
-void register_ip_addr(const struct ip_addr *ip_addr){
+void register_addrs(const eth_mac_addr_t *mac_addr, const struct ip_addr *ip_addr){
+    _local_mac_addr = *mac_addr;
     _local_ip_addr = *ip_addr;
 }
 
@@ -72,6 +64,12 @@ struct listener_entry {
 
 static struct listener_entry listeners[MAX_UDP_LISTENERS];
 
+void init_udp_listeners(void){
+    for (int i = 0; i < MAX_UDP_LISTENERS; i++){
+        listeners[i].rcvr = NULL;
+    }
+}
+
 static struct listener_entry *
 find_listener_by_port(unsigned short port)
 {
@@ -86,7 +84,7 @@ static struct listener_entry *
 find_free_listener(void)
 {
   for (int i = 0; i < MAX_UDP_LISTENERS; i++){
-    if (listeners[i].rcvr == 0)
+    if (listeners[i].rcvr == NULL)
       return &listeners[i];
   }
   abort();
@@ -126,13 +124,6 @@ send_pkt(eth_mac_addr_t dst, int ethertype,
 	 const void *buf1, size_t len1,
 	 const void *buf2, size_t len2)
 {
-  // Wait for buffer to become idle
-  // FIXME can this ever not be ready?
-
-  //hal_set_leds(LED_BUF_BUSY, LED_BUF_BUSY);
-  while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
-    ;
-  //hal_set_leds(0, LED_BUF_BUSY);
 
   // Assemble the header
   padded_eth_hdr_t	ehdr;
@@ -141,9 +132,10 @@ send_pkt(eth_mac_addr_t dst, int ethertype,
   ehdr.src = _local_mac_addr;
   ehdr.ethertype = ethertype;
 
-  uint32_t *p = buffer_ram(CPU_TX_BUF);
+  uint32_t *buff = (uint32_t *)pkt_ctrl_claim_outgoing_buffer();
 
   // Copy the pieces into the buffer
+  uint32_t *p = buff;
   *p++ = 0x0;  				  // slow path
   memcpy_wa(p, &ehdr, sizeof(ehdr));      // 4 lines
   p += sizeof(ehdr)/sizeof(uint32_t);
@@ -173,34 +165,23 @@ send_pkt(eth_mac_addr_t dst, int ethertype,
     p += len2/sizeof(uint32_t);
   }
 
-  size_t total_len = (p - buffer_ram(CPU_TX_BUF)) * sizeof(uint32_t);
+  size_t total_len = (p - buff) * sizeof(uint32_t);
   if (total_len < 60)		// ensure that we don't try to send a short packet
     total_len = 60;
-  
-  // wait until nobody else is sending to the ethernet
-  if (ac_could_be_sending_to_eth){
-    //hal_set_leds(LED_ETH_BUSY, LED_ETH_BUSY);
-    dbsm_wait_for_opening(ac_could_be_sending_to_eth);
-    //hal_set_leds(0x0, LED_ETH_BUSY);
-  }
-
-  if (0){
-    printf("send_pkt to port %d, len = %d\n",
-	   cpu_tx_buf_dest_port, (int) total_len);
-    print_buffer(buffer_ram(CPU_TX_BUF), total_len/4);
-  }
 
-  // fire it off
-  bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, total_len/4);
-
-  // wait for it to complete (not long, it's a small pkt)
-  while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
-    ;
+  pkt_ctrl_commit_outgoing_buffer(total_len/4);
+  if (debug) printf("sent %d bytes\n", (int)total_len);
+}
 
-  bp_clear_buf(CPU_TX_BUF);
+unsigned int CHKSUM(unsigned int x, unsigned int *chksum)
+{
+  *chksum += x;
+  *chksum = (*chksum & 0xffff) + (*chksum>>16);
+  *chksum = (*chksum & 0xffff) + (*chksum>>16);
+  return x;
 }
 
-unsigned int 
+static unsigned int
 chksum_buffer(unsigned short *buf, int nshorts, unsigned int initial_chksum)
 {
   unsigned int chksum = initial_chksum;
@@ -210,7 +191,6 @@ chksum_buffer(unsigned short *buf, int nshorts, unsigned int initial_chksum)
   return chksum;
 }
 
-
 void
 send_ip_pkt(struct ip_addr dst, int protocol,
 	    const void *buf0, size_t len0,
@@ -235,7 +215,7 @@ send_ip_pkt(struct ip_addr dst, int protocol,
   bool found = arp_cache_lookup_mac(&ip.dest, &dst_mac);
   if (!found){
     printf("net_common: failed to hit cache looking for ");
-    print_ip(ip.dest);
+    print_ip_addr(&ip.dest);
     newline();
     return;
   }
@@ -294,6 +274,11 @@ handle_icmp_packet(struct ip_addr src, struct ip_addr dst,
     if (icmp->code == ICMP_DUR_PORT){	// port unreachable
       //handle destination port unreachable (the host ctrl+c'd the app):
 
+      //filter out non udp data response
+      struct ip_hdr *ip = (struct ip_hdr *)(((uint8_t*)icmp) + sizeof(struct icmp_echo_hdr));
+      struct udp_hdr *udp = (struct udp_hdr *)(((char *)ip) + IP_HLEN);
+      if (IPH_PROTO(ip) != IP_PROTO_UDP || udp->dest != fp_socket_dst.port) return;
+
       //end async update packets per second
       sr_tx_ctrl->cyc_per_up = 0;
 
@@ -373,8 +358,7 @@ void send_gratuitous_arp(void){
   memcpy(req.ar_tip, get_ip_addr(),       sizeof(struct ip_addr));
 
   //send the request with a broadcast ethernet mac address
-  eth_mac_addr_t t; memset(&t, 0xff, sizeof(t));
-  send_pkt(t, ETHERTYPE_ARP, &req, sizeof(req), 0, 0, 0, 0);
+  send_pkt(BCAST_MAC_ADDR, ETHERTYPE_ARP, &req, sizeof(req), 0, 0, 0, 0);
 }
 
 static void
@@ -412,7 +396,7 @@ handle_arp_packet(struct arp_eth_ipv4 *p, size_t size)
   sip.addr = get_int32(p->ar_sip);
   tip.addr = get_int32(p->ar_tip);
 
-  if (ip_addr_eq(tip, _local_ip_addr)){	// They're looking for us...
+  if (memcmp(&tip, &_local_ip_addr, sizeof(_local_ip_addr)) == 0){	// They're looking for us...
     send_arp_reply(p, _local_mac_addr);
   }
 }
@@ -420,15 +404,17 @@ handle_arp_packet(struct arp_eth_ipv4 *p, size_t size)
 void
 handle_eth_packet(uint32_t *p, size_t nlines)
 {
-  //print_buffer(p, nlines);
+  static size_t bcount = 0;
+  if (debug) printf("===> %d\n", (int)bcount++);
+  if (debug) print_buffer(p, nlines);
 
-  int ethertype = p[3] & 0xffff;
+  padded_eth_hdr_t *eth_hdr = (padded_eth_hdr_t *)p;
 
-  if (ethertype == ETHERTYPE_ARP){
+  if (eth_hdr->ethertype == ETHERTYPE_ARP){
     struct arp_eth_ipv4 *arp = (struct arp_eth_ipv4 *)(p + 4);
     handle_arp_packet(arp, nlines*sizeof(uint32_t) - 14);
   }
-  else if (ethertype == ETHERTYPE_IPV4){
+  else if (eth_hdr->ethertype == ETHERTYPE_IPV4){
     struct ip_hdr *ip = (struct ip_hdr *)(p + 4);
     if (IPH_V(ip) != 4 || IPH_HL(ip) != 5)	// ignore pkts w/ bad version or options
       return;
@@ -436,7 +422,10 @@ handle_eth_packet(uint32_t *p, size_t nlines)
     if (IPH_OFFSET(ip) & (IP_MF | IP_OFFMASK))	// ignore fragmented packets
       return;
 
-    // FIXME filter on dest ip addr (should be broadcast or for us)
+    // filter on dest ip addr (should be broadcast or for us)
+    bool is_bcast = memcmp(&eth_hdr->dst, &BCAST_MAC_ADDR, sizeof(BCAST_MAC_ADDR)) == 0;
+    bool is_my_ip = memcmp(&ip->dest, &_local_ip_addr, sizeof(_local_ip_addr)) == 0;
+    if (!is_bcast && !is_my_ip) return;
 
     arp_cache_update(&ip->src, (eth_mac_addr_t *)(((char *)p)+8));
 
diff --git a/firmware/microblaze/lib/net_common.h b/firmware/zpu/lib/net_common.h
index 3040e5ef3..409022352 100644
--- a/firmware/microblaze/lib/net_common.h
+++ b/firmware/zpu/lib/net_common.h
@@ -20,25 +20,22 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <dbsm.h>
 #include <net/socket_address.h>
 #include <net/eth_mac_addr.h>
 
-#define CPU_TX_BUF 	7	// cpu -> eth
-
-extern int cpu_tx_buf_dest_port;
-
-// If this is non-zero, this dbsm could be writing to the ethernet
-extern dbsm_t *ac_could_be_sending_to_eth;
-
-void stop_streaming(void);
+/*
+ * 1's complement sum for IP and UDP headers
+ *
+ * init chksum to zero to start.
+ */
+unsigned int CHKSUM(unsigned int x, unsigned int *chksum);
 
 typedef void (*udp_receiver_t)(struct socket_address src, struct socket_address dst,
 			       unsigned char *payload, int payload_len);
 
-void register_mac_addr(const eth_mac_addr_t *mac_addr);
+void init_udp_listeners(void);
 
-void register_ip_addr(const struct ip_addr *ip_addr);
+void register_addrs(const eth_mac_addr_t *mac_addr, const struct ip_addr *ip_addr);
 
 void register_udp_listener(int port, udp_receiver_t rcvr);
 
diff --git a/firmware/microblaze/lib/nonstdio.c b/firmware/zpu/lib/nonstdio.c
index 4b5fa4123..4b5fa4123 100644
--- a/firmware/microblaze/lib/nonstdio.c
+++ b/firmware/zpu/lib/nonstdio.c
diff --git a/firmware/microblaze/lib/nonstdio.h b/firmware/zpu/lib/nonstdio.h
index 62ebfa46d..6aca7ed9a 100644
--- a/firmware/microblaze/lib/nonstdio.h
+++ b/firmware/zpu/lib/nonstdio.h
@@ -45,4 +45,6 @@ void print_buffer(uint32_t *buf, size_t n);
 //char *itoa(signed long value, char *result, int base);
 //void reverse(char s[]);
 
+void print_ip_addr(const void *t);
+
 #endif /* INCLUDED_NONSTDIO_H */
diff --git a/firmware/microblaze/lib/pic.c b/firmware/zpu/lib/pic.c
index 226da5f85..bd627ce6b 100644
--- a/firmware/microblaze/lib/pic.c
+++ b/firmware/zpu/lib/pic.c
@@ -26,17 +26,7 @@
 /*
  * Our secondary interrupt vector.
  */
-irq_handler_t pic_vector[NVECTORS] = {
-  nop_handler,
-  nop_handler,
-  nop_handler,
-  nop_handler,
-  nop_handler,
-  nop_handler,
-  nop_handler,
-  nop_handler
-};
-
+irq_handler_t pic_vector[NVECTORS];
 
 void
 pic_init(void)
@@ -47,6 +37,10 @@ pic_init(void)
   pic_regs->edge_enable = PIC_ONETIME_INT | PIC_UNDERRUN_INT | PIC_OVERRUN_INT | PIC_PPS_INT;
   pic_regs->polarity = ~0 & ~PIC_PHY_INT;	       // rising edge
   pic_regs->pending = ~0;			       // clear all pending ints
+
+  for (int i = 0; i < NVECTORS; i++){
+    pic_vector[i] = pic_nop_handler;
+  }
 }
 
 /*
@@ -54,7 +48,8 @@ pic_init(void)
  * system interrupt handler with the appropriate prologue and
  * epilogue.
  */
-void pic_interrupt_handler() __attribute__ ((interrupt_handler));
+//FIXME zpu-gcc does not install interrupt_handler like this
+//void pic_interrupt_handler() __attribute__ ((interrupt_handler));
 
 void pic_interrupt_handler()
 {
@@ -88,7 +83,7 @@ pic_register_handler(unsigned irq, irq_handler_t handler)
 }
 
 void
-nop_handler(unsigned irq)
+pic_nop_handler(unsigned irq)
 {
   // nop
 }
diff --git a/firmware/microblaze/lib/pic.h b/firmware/zpu/lib/pic.h
index 68918f9ad..cfdf721f4 100644
--- a/firmware/microblaze/lib/pic.h
+++ b/firmware/zpu/lib/pic.h
@@ -24,12 +24,13 @@ typedef void (*irq_handler_t)(unsigned irq);
 void pic_init(void);
 void pic_register_handler(unsigned irq, irq_handler_t handler);
 
-void nop_handler(unsigned irq);	// default handler does nothing
+void pic_nop_handler(unsigned irq);	// default handler does nothing
 
 // FIXME inline assembler
 int  pic_disable_interrupts();
 int  pic_enable_interrupts();
 void pic_restore_interrupts(int prev_status);
 
+void pic_interrupt_handler();
 
 #endif /* INCLUDED_PIC_H */
diff --git a/firmware/zpu/lib/pkt_ctrl.c b/firmware/zpu/lib/pkt_ctrl.c
new file mode 100644
index 000000000..ebda35049
--- /dev/null
+++ b/firmware/zpu/lib/pkt_ctrl.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2010 Ettus Research LLC
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pkt_ctrl.h"
+#include "memory_map.h"
+#include <nonstdio.h>
+
+void pkt_ctrl_program_inspector(
+    const struct ip_addr *ip_addr, uint16_t data_port
+){
+    router_ctrl->ip_addr = ip_addr->addr;
+    router_ctrl->data_ports = data_port;
+}
+
+void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode){
+    switch(mode){
+    case PKT_CTRL_ROUTING_MODE_SLAVE:  router_ctrl->mode_ctrl = 0; break;
+    case PKT_CTRL_ROUTING_MODE_MASTER: router_ctrl->mode_ctrl = 1; break;
+    }
+}
+
+static inline bool is_status_bit_set(int bit){
+    return router_status->status & (1 << bit);
+}
+
+#define CPU_OUT_HS_BIT 0 //from packet router to CPU
+#define CPU_INP_HS_BIT 1 //from CPU to packet router
+
+void *pkt_ctrl_claim_incoming_buffer(size_t *num_lines){
+    if (!is_status_bit_set(CPU_OUT_HS_BIT)) return NULL;
+    *num_lines = (router_status->status >> 16) & 0xffff;
+    return router_ram(0);
+}
+
+void pkt_ctrl_release_incoming_buffer(void){
+    router_ctrl->cpu_out_ctrl = 1;
+    while (is_status_bit_set(CPU_OUT_HS_BIT)){}
+    router_ctrl->cpu_out_ctrl = 0;
+}
+
+void *pkt_ctrl_claim_outgoing_buffer(void){
+    while (!is_status_bit_set(CPU_INP_HS_BIT)){}
+    return router_ram(1);
+}
+
+void pkt_ctrl_commit_outgoing_buffer(size_t num_lines){
+    router_ctrl->cpu_inp_ctrl = ((num_lines & 0xffff) << 16) | 1;
+    while (is_status_bit_set(CPU_INP_HS_BIT)){}
+    router_ctrl->cpu_inp_ctrl = 0;
+}
diff --git a/firmware/zpu/lib/pkt_ctrl.h b/firmware/zpu/lib/pkt_ctrl.h
new file mode 100644
index 000000000..410ffdaa4
--- /dev/null
+++ b/firmware/zpu/lib/pkt_ctrl.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2010 Ettus Research LLC
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef INCLUDED_PKT_CTRL_H
+#define INCLUDED_PKT_CTRL_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <lwip/ip_addr.h>
+
+typedef enum {
+    PKT_CTRL_ROUTING_MODE_SLAVE,
+    PKT_CTRL_ROUTING_MODE_MASTER,
+} pkt_ctrl_routing_mode_t;
+
+//! Program the decision values into the packet inspector
+void pkt_ctrl_program_inspector(
+    const struct ip_addr *ip_addr, uint16_t data_port
+);
+
+//! Set the routing mode for this device
+void pkt_ctrl_set_routing_mode(pkt_ctrl_routing_mode_t mode);
+
+/*!
+ * Try to claim an incomming buffer.
+ * \param num_lines filled with the buffer size
+ * \return a pointer to the buffer memory or NULL
+ */
+void *pkt_ctrl_claim_incoming_buffer(size_t *num_lines);
+
+/*!
+ * Release the incoming buffer. Call when done.
+ */
+void pkt_ctrl_release_incoming_buffer(void);
+
+/*!
+ * Claim an outgoing buffer.
+ * \return a pointer to the buffer
+ */
+void *pkt_ctrl_claim_outgoing_buffer(void);
+
+/*!
+ * Commit the outgoing buffer.
+ * \param num_lines how many lines written.
+ */
+void pkt_ctrl_commit_outgoing_buffer(size_t num_lines);
+
+#endif /* INCLUDED_PKT_CTRL_H */
diff --git a/firmware/microblaze/lib/print_mac_addr.c b/firmware/zpu/lib/print_addrs.c
index 475082325..29601c47c 100644
--- a/firmware/microblaze/lib/print_mac_addr.c
+++ b/firmware/zpu/lib/print_addrs.c
@@ -26,3 +26,7 @@ print_mac_addr(const unsigned char addr[6])
   }
 }
 
+void print_ip_addr(const void *t){
+    uint8_t *p = (uint8_t *)t;
+    printf("%d.%d.%d.%d", p[0], p[1], p[2], p[3]);
+}
diff --git a/firmware/microblaze/lib/print_buffer.c b/firmware/zpu/lib/print_buffer.c
index 9f9104bb5..9f9104bb5 100644
--- a/firmware/microblaze/lib/print_buffer.c
+++ b/firmware/zpu/lib/print_buffer.c
diff --git a/firmware/microblaze/lib/print_rmon_regs.c b/firmware/zpu/lib/print_rmon_regs.c
index 6d9986909..6d9986909 100644
--- a/firmware/microblaze/lib/print_rmon_regs.c
+++ b/firmware/zpu/lib/print_rmon_regs.c
diff --git a/firmware/microblaze/lib/print_rmon_regs.h b/firmware/zpu/lib/print_rmon_regs.h
index 44e52da84..44e52da84 100644
--- a/firmware/microblaze/lib/print_rmon_regs.h
+++ b/firmware/zpu/lib/print_rmon_regs.h
diff --git a/firmware/microblaze/lib/printf.c b/firmware/zpu/lib/printf.c
index 45bd57cb9..45bd57cb9 100644
--- a/firmware/microblaze/lib/printf.c
+++ b/firmware/zpu/lib/printf.c
diff --git a/firmware/microblaze/lib/printf.c.smaller b/firmware/zpu/lib/printf.c.smaller
index 4d858648d..4d858648d 100644
--- a/firmware/microblaze/lib/printf.c.smaller
+++ b/firmware/zpu/lib/printf.c.smaller
diff --git a/firmware/microblaze/lib/spi.c b/firmware/zpu/lib/spi.c
index 2a41a1bfa..af0d8a68f 100644
--- a/firmware/microblaze/lib/spi.c
+++ b/firmware/zpu/lib/spi.c
@@ -20,9 +20,9 @@
 #include "pic.h"
 #include "nonstdio.h"
 
-void (*volatile spi_callback)(void); //SPI callback when xfer complete.
+//void (*volatile spi_callback)(void); //SPI callback when xfer complete.
 
-static void spi_irq_handler(unsigned irq);
+//static void spi_irq_handler(unsigned irq);
 
 void
 spi_init(void) 
@@ -66,6 +66,7 @@ spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags
     return 0;
 }
 
+/*
 void spi_register_callback(void (*volatile callback)(void)) {
   spi_callback = callback;
 }
@@ -106,3 +107,4 @@ spi_async_transact(int slave, uint32_t data, int length, uint32_t flags, void (*
 
   return true;
 }
+*/
diff --git a/firmware/microblaze/lib/spi.h b/firmware/zpu/lib/spi.h
index 54618cedd..71245150a 100644
--- a/firmware/microblaze/lib/spi.h
+++ b/firmware/zpu/lib/spi.h
@@ -48,12 +48,12 @@ void spi_wait(void);
 uint32_t
 spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags);
 
-uint32_t spi_get_data(void);
+//uint32_t spi_get_data(void);
 //static void spi_irq_handler(unsigned irq);
-void spi_register_callback(void (*volatile callback)(void));
+//void spi_register_callback(void (*volatile callback)(void));
 
-bool 
-spi_async_transact(int slave, uint32_t data, int length, uint32_t flags, void (*volatile callback)(void));
+//bool 
+//spi_async_transact(int slave, uint32_t data, int length, uint32_t flags, void (*volatile callback)(void));
 
 // ----------------------------------------------------------------
 // Routines that manipulate the FLASH SPI BUS
diff --git a/firmware/microblaze/lib/stdint.h b/firmware/zpu/lib/stdint.h
index b5a8611a9..b5a8611a9 100644
--- a/firmware/microblaze/lib/stdint.h
+++ b/firmware/zpu/lib/stdint.h
diff --git a/firmware/microblaze/lib/stdio.h b/firmware/zpu/lib/stdio.h
index 12a7ed0bb..12a7ed0bb 100644
--- a/firmware/microblaze/lib/stdio.h
+++ b/firmware/zpu/lib/stdio.h
diff --git a/firmware/microblaze/lib/u2_init.c b/firmware/zpu/lib/u2_init.c
index 4a553a713..191a0e816 100644
--- a/firmware/microblaze/lib/u2_init.c
+++ b/firmware/zpu/lib/u2_init.c
@@ -20,25 +20,13 @@
 #include "spi.h"
 #include "pic.h"
 #include "hal_io.h"
-#include "buffer_pool.h"
 #include "hal_uart.h"
 #include "i2c.h"
-#include "i2c_async.h"
 #include "mdelay.h"
 #include "clocks.h"
 #include "usrp2/fw_common.h"
 #include "nonstdio.h"
 
-unsigned char u2_hw_rev_major;
-unsigned char u2_hw_rev_minor;
-
-static inline void
-get_hw_rev(void)
-{
-  bool ok = eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_REV, &u2_hw_rev_minor, 1);
-  ok &= eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_REV+1, &u2_hw_rev_major, 1);
-}
-
 /*
  * We ought to arrange for this to be called before main, but for now,
  * we require that the user's main call u2_init as the first thing...
@@ -60,13 +48,8 @@ u2_init(void)
   // init i2c so we can read our rev
   pic_init();	// progammable interrupt controller
   i2c_init();
-  i2c_register_handler(); //for using async I2C
   hal_enable_ints();
 
-  bp_init();	// buffer pool
-  
-
-
   // flash all leds to let us know board is alive
   hal_set_leds(0x0, 0x1f);
   mdelay(100);
@@ -85,6 +68,8 @@ u2_init(void)
     printf("ad9510 reg[0x%x] = 0x%x\n", rr, vv);
   }
 #endif
-  
+
+  output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
+
   return true;
 }
diff --git a/firmware/microblaze/lib/u2_init.h b/firmware/zpu/lib/u2_init.h
index 848bd88de..848bd88de 100644
--- a/firmware/microblaze/lib/u2_init.h
+++ b/firmware/zpu/lib/u2_init.h
diff --git a/firmware/microblaze/lib/udp_fw_update.h b/firmware/zpu/lib/udp_fw_update.h
index d25525bd2..d25525bd2 100644
--- a/firmware/microblaze/lib/udp_fw_update.h
+++ b/firmware/zpu/lib/udp_fw_update.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/CHANGELOG b/firmware/zpu/lwip/lwip-1.3.1/CHANGELOG
index a45765010..a45765010 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/CHANGELOG
+++ b/firmware/zpu/lwip/lwip-1.3.1/CHANGELOG
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/COPYING b/firmware/zpu/lwip/lwip-1.3.1/COPYING
index e23898b5e..e23898b5e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/COPYING
+++ b/firmware/zpu/lwip/lwip-1.3.1/COPYING
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/FILES b/firmware/zpu/lwip/lwip-1.3.1/FILES
index 66253196f..66253196f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/FILES
+++ b/firmware/zpu/lwip/lwip-1.3.1/FILES
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/README b/firmware/zpu/lwip/lwip-1.3.1/README
index 8dda4b468..8dda4b468 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/README
+++ b/firmware/zpu/lwip/lwip-1.3.1/README
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/FILES b/firmware/zpu/lwip/lwip-1.3.1/doc/FILES
index 05d356f4f..05d356f4f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/FILES
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/FILES
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/contrib.txt b/firmware/zpu/lwip/lwip-1.3.1/doc/contrib.txt
index 39596fca3..39596fca3 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/contrib.txt
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/contrib.txt
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/rawapi.txt b/firmware/zpu/lwip/lwip-1.3.1/doc/rawapi.txt
index 8eec6e786..8eec6e786 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/rawapi.txt
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/rawapi.txt
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/savannah.txt b/firmware/zpu/lwip/lwip-1.3.1/doc/savannah.txt
index 409905b10..409905b10 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/savannah.txt
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/savannah.txt
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/snmp_agent.txt b/firmware/zpu/lwip/lwip-1.3.1/doc/snmp_agent.txt
index 9b58616a6..9b58616a6 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/snmp_agent.txt
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/snmp_agent.txt
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/doc/sys_arch.txt b/firmware/zpu/lwip/lwip-1.3.1/doc/sys_arch.txt
index 66310a91e..66310a91e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/doc/sys_arch.txt
+++ b/firmware/zpu/lwip/lwip-1.3.1/doc/sys_arch.txt
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/.hgignore b/firmware/zpu/lwip/lwip-1.3.1/src/.hgignore
index f88587df3..f88587df3 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/.hgignore
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/.hgignore
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/FILES b/firmware/zpu/lwip/lwip-1.3.1/src/FILES
index 952aeabb4..952aeabb4 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/FILES
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/FILES
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/api_lib.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/api_lib.c
index 86df911ea..86df911ea 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/api_lib.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/api_lib.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/api_msg.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/api_msg.c
index 28d101019..28d101019 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/api_msg.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/api_msg.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/err.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/err.c
index a90cb98c8..a90cb98c8 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/err.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/err.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netbuf.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/netbuf.c
index af44eefc7..af44eefc7 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netbuf.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/netbuf.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netdb.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/netdb.c
index 8aa237f4c..8aa237f4c 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netdb.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/netdb.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netifapi.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/netifapi.c
index 491837378..491837378 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/netifapi.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/netifapi.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/sockets.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/sockets.c
index f177261e1..f177261e1 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/sockets.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/sockets.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/api/tcpip.c b/firmware/zpu/lwip/lwip-1.3.1/src/api/tcpip.c
index 002df90b2..002df90b2 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/api/tcpip.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/api/tcpip.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/#tcp_out.c# b/firmware/zpu/lwip/lwip-1.3.1/src/core/#tcp_out.c#
index ca72d9dcc..ca72d9dcc 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/#tcp_out.c#
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/#tcp_out.c#
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/dhcp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/dhcp.c
index df0f97881..df0f97881 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/dhcp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/dhcp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/dns.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/dns.c
index 62a2592e9..62a2592e9 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/dns.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/dns.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/init.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/init.c
index 277811a6a..277811a6a 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/init.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/init.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/autoip.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/autoip.c
index 367adb060..367adb060 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/autoip.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/autoip.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/icmp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/icmp.c
index b97a587a7..b97a587a7 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/icmp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/icmp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/igmp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/igmp.c
index 7c07bc465..7c07bc465 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/igmp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/igmp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/inet.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet.c
index 69baf1d50..69baf1d50 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/inet.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c
index 185881efd..185881efd 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/inet_chksum.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip.c
index 7e404a9f3..7e404a9f3 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c
index 94bf4678a..94bf4678a 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_addr.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c
index 1939d831b..1939d831b 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv4/ip_frag.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/README b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/README
index 362000486..362000486 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/README
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/README
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c
index 4fcc89551..4fcc89551 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/icmp6.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/inet6.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/inet6.c
index c3de85c09..c3de85c09 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/inet6.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/inet6.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/ip6.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6.c
index 7e4342001..7e4342001 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/ip6.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c
index 2da6cea42..2da6cea42 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/ipv6/ip6_addr.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/mem.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/mem.c
index b5f13ab3b..b5f13ab3b 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/mem.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/mem.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/memp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/memp.c
index dfc32213d..dfc32213d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/memp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/memp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/netif.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/netif.c
index c9b6b9b5e..c9b6b9b5e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/netif.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/netif.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/pbuf.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/pbuf.c
index 50b22c354..50b22c354 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/pbuf.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/pbuf.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/raw.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/raw.c
index 589950e75..589950e75 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/raw.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/raw.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c
index 650fb4037..650fb4037 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_dec.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c
index 77af6b4ba..77af6b4ba 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/asn1_enc.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/mib2.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib2.c
index 33eeee66c..33eeee66c 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/mib2.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib2.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c
index af8994ed2..af8994ed2 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/mib_structs.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/msg_in.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_in.c
index d0c3c7534..d0c3c7534 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/msg_in.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_in.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/msg_out.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_out.c
index b705aaca7..b705aaca7 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/snmp/msg_out.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/snmp/msg_out.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/stats.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/stats.c
index a036d83bb..a036d83bb 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/stats.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/stats.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/sys.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/sys.c
index d1fbda4e6..d1fbda4e6 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/sys.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/sys.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp.c
index 0f3fd41c3..0f3fd41c3 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp_in.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_in.c
index 362a4a62d..362a4a62d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp_in.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_in.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp_out.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_out.c
index ca72d9dcc..ca72d9dcc 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/tcp_out.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/tcp_out.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/core/udp.c b/firmware/zpu/lwip/lwip-1.3.1/src/core/udp.c
index d8d644d44..d8d644d44 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/core/udp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/core/udp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h
index 076a2ed23..076a2ed23 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/autoip.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h
index ff838f43a..ff838f43a 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/icmp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h
index 59c933f35..59c933f35 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/igmp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h
index 6f30d0d12..6f30d0d12 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h
index 5cae59cbd..5cae59cbd 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/inet_chksum.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h
index 14eba3ca5..14eba3ca5 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h
index f2e4c2233..f2e4c2233 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_addr.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h
index 380e604dc..380e604dc 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv4/lwip/ip_frag.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h
index 87e9ffd96..87e9ffd96 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/icmp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h
index de1a0b636..de1a0b636 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/inet.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h
index a01cfc65b..a01cfc65b 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h
index b2d8ae566..b2d8ae566 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/ipv6/lwip/ip_addr.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/api.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api.h
index f6b1f7434..f6b1f7434 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/api.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/api_msg.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api_msg.h
index 4272d77cc..4272d77cc 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/api_msg.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/api_msg.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/arch.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/arch.h
index 3a5a0e4f2..3a5a0e4f2 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/arch.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/arch.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/debug.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/debug.h
index d5c4e4747..d5c4e4747 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/debug.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/debug.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/def.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/def.h
index d2ed251df..d2ed251df 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/def.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/def.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/dhcp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dhcp.h
index 825dba6ec..825dba6ec 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/dhcp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dhcp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/dns.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dns.h
index e5f4b7a3d..e5f4b7a3d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/dns.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/dns.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/err.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/err.h
index 696764454..696764454 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/err.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/err.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/init.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/init.h
index a4dc0577f..a4dc0577f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/init.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/init.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/mem.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/mem.h
index 327c2049f..327c2049f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/mem.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/mem.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/memp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp.h
index f0d073994..f0d073994 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/memp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/memp_std.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp_std.h
index 344690328..344690328 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/memp_std.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/memp_std.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netbuf.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netbuf.h
index 6d84dd073..6d84dd073 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netbuf.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netbuf.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netdb.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netdb.h
index 0f7b2ec04..0f7b2ec04 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netdb.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netdb.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netif.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netif.h
index a32503052..a32503052 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netif.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netif.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netifapi.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netifapi.h
index 36c6bd0a2..36c6bd0a2 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/netifapi.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/netifapi.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/opt.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/opt.h
index e8bd8b89e..e8bd8b89e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/opt.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/opt.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/pbuf.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/pbuf.h
index 8380f65da..8380f65da 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/pbuf.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/pbuf.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/raw.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/raw.h
index 20b0a11bb..20b0a11bb 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/raw.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/raw.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sio.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sio.h
index 7d9162e49..7d9162e49 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sio.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sio.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp.h
index dd03d5d70..dd03d5d70 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h
index 8a602881f..8a602881f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_asn1.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h
index b2f69c4be..b2f69c4be 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_msg.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h
index 9f3f8a94e..9f3f8a94e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/snmp_structs.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sockets.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sockets.h
index 7b52e151c..7b52e151c 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sockets.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sockets.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/stats.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/stats.h
index aa179f5c0..aa179f5c0 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/stats.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/stats.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sys.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sys.h
index 0cc84ddf1..0cc84ddf1 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/sys.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/sys.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/tcp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcp.h
index 8f6b9d3c1..8f6b9d3c1 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/tcp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/tcpip.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcpip.h
index 75393ee91..75393ee91 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/tcpip.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/tcpip.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/udp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/udp.h
index d7b2a3820..d7b2a3820 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/lwip/udp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/lwip/udp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/etharp.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/etharp.h
index db691d91d..db691d91d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/etharp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/etharp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/loopif.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/loopif.h
index 304af4b39..304af4b39 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/loopif.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/loopif.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h
index 3aa55aec7..3aa55aec7 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/ppp_oe.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/slipif.h b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/slipif.h
index aa08ada4a..aa08ada4a 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/include/netif/slipif.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/include/netif/slipif.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/FILES b/firmware/zpu/lwip/lwip-1.3.1/src/netif/FILES
index 1c4f5928d..1c4f5928d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/FILES
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/FILES
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/etharp.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/etharp.c
index 73ea21173..73ea21173 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/etharp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/etharp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ethernetif.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ethernetif.c
index ccd7bd67f..ccd7bd67f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ethernetif.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ethernetif.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/loopif.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/loopif.c
index 1e1f28cf1..1e1f28cf1 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/loopif.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/loopif.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/auth.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c
index 4c0ee6a8e..4c0ee6a8e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/auth.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/auth.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.h
index 86ff04945..86ff04945 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/auth.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/auth.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chap.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c
index 6d9c3c3ce..6d9c3c3ce 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chap.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chap.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h
index 83dafd734..83dafd734 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chap.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chap.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chpms.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.c
index 0c7521f20..0c7521f20 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chpms.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chpms.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.h
index df070fb35..df070fb35 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/chpms.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/chpms.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/fsm.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.c
index c073f1e36..c073f1e36 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/fsm.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/fsm.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.h
index 14034ec7f..14034ec7f 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/fsm.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/fsm.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c
index 3a403a0a6..3a403a0a6 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h
index dfcf4fba6..dfcf4fba6 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ipcp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/lcp.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.c
index 85a0add95..85a0add95 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/lcp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/lcp.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.h
index 1a5e5a4c0..1a5e5a4c0 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/lcp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/lcp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/magic.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.c
index d3922bb56..d3922bb56 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/magic.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/magic.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.h
index bc5174993..bc5174993 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/magic.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/magic.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/md5.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.c
index d65ecedbf..d65ecedbf 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/md5.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/md5.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.h
index e129533f3..e129533f3 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/md5.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/md5.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pap.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.c
index 7c3fd7e4c..7c3fd7e4c 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pap.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pap.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.h
index 0a09fc841..0a09fc841 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pap.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pap.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c
index 8720c3368..8720c3368 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h
index d5caa0a7e..d5caa0a7e 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c
index c34c529b6..c34c529b6 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/ppp_oe.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h
index 6253863c9..6253863c9 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/pppdebug.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/randm.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.c
index 0c622a0b0..0c622a0b0 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/randm.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/randm.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.h
index a0984b020..a0984b020 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/randm.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/randm.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vj.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.c
index 814ea72c5..814ea72c5 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vj.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.c
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vj.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.h
index b9617da4d..b9617da4d 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vj.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vj.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h
index f46267614..f46267614 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/ppp/vjbsdhdr.h
diff --git a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/slipif.c b/firmware/zpu/lwip/lwip-1.3.1/src/netif/slipif.c
index 6cb2db442..6cb2db442 100644
--- a/firmware/microblaze/lwip/lwip-1.3.1/src/netif/slipif.c
+++ b/firmware/zpu/lwip/lwip-1.3.1/src/netif/slipif.c
diff --git a/firmware/microblaze/lwip/lwipopts.h b/firmware/zpu/lwip/lwipopts.h
index 3839eea83..3839eea83 100644
--- a/firmware/microblaze/lwip/lwipopts.h
+++ b/firmware/zpu/lwip/lwipopts.h
diff --git a/firmware/microblaze/lwip/lwippools.h b/firmware/zpu/lwip/lwippools.h
index caee23c82..caee23c82 100644
--- a/firmware/microblaze/lwip/lwippools.h
+++ b/firmware/zpu/lwip/lwippools.h
diff --git a/firmware/microblaze/lwip_port/arch/cc.h b/firmware/zpu/lwip_port/arch/cc.h
index d8d53ecf8..d8d53ecf8 100644
--- a/firmware/microblaze/lwip_port/arch/cc.h
+++ b/firmware/zpu/lwip_port/arch/cc.h
diff --git a/firmware/microblaze/lwip_port/arch/perf.h b/firmware/zpu/lwip_port/arch/perf.h
index f0906d03f..f0906d03f 100644
--- a/firmware/microblaze/lwip_port/arch/perf.h
+++ b/firmware/zpu/lwip_port/arch/perf.h
diff --git a/firmware/microblaze/lwip_port/netif/eth_driver.c b/firmware/zpu/lwip_port/netif/eth_driver.c
index 18c6eaf3e..18c6eaf3e 100644
--- a/firmware/microblaze/lwip_port/netif/eth_driver.c
+++ b/firmware/zpu/lwip_port/netif/eth_driver.c
diff --git a/firmware/microblaze/lwip_port/netif/eth_driver.h b/firmware/zpu/lwip_port/netif/eth_driver.h
index 72a212091..72a212091 100644
--- a/firmware/microblaze/lwip_port/netif/eth_driver.h
+++ b/firmware/zpu/lwip_port/netif/eth_driver.h
diff --git a/firmware/microblaze/usrp2/Makefile.am b/firmware/zpu/usrp2/CMakeLists.txt
index 7a58e7253..8ed31b8d4 100644
--- a/firmware/microblaze/usrp2/Makefile.am
+++ b/firmware/zpu/usrp2/CMakeLists.txt
@@ -15,33 +15,22 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-include $(top_srcdir)/Makefile.common
-
-AM_CFLAGS = \
-	$(COMMON_CFLAGS)
-
-AM_LDFLAGS = \
-	$(COMMON_LFLAGS) \
-	-Wl,-defsym -Wl,_TEXT_START_ADDR=0x0050 \
-	-Wl,-defsym -Wl,_STACK_SIZE=3072
-	
-LDADD = libusrp2.a
-
-LDADD = libusrp2.a
-
-########################################################################
-# USRP2 specific library and programs
 ########################################################################
-noinst_LIBRARIES = libusrp2.a
+INCLUDE(${CMAKE_SOURCE_DIR}/lib/CMakeLists.txt)
+INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
 
-libusrp2_a_SOURCES = \
-	$(COMMON_SRCS) \
-	sd.c \
-	ethernet.c \
-  udp_fw_update.c
+ADD_LIBRARY(libusrp2fw STATIC
+    ${COMMON_SRCS}
+    sd.c
+    ethernet.c
+    udp_fw_update.c
+)
 
-noinst_PROGRAMS = \
-	usrp2_txrx_uhd.elf
+########################################################################
+ADD_EXECUTABLE(usrp2_txrx_uhd.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c)
+TARGET_LINK_LIBRARIES(usrp2_txrx_uhd.elf libusrp2fw)
+GEN_OUTPUTS(usrp2_txrx_uhd.elf)
 
-usrp2_txrx_uhd_elf_SOURCES = \
-	$(top_srcdir)/apps/txrx_uhd.c
+ADD_EXECUTABLE(usrp2_blinkenlights.elf ${CMAKE_SOURCE_DIR}/apps/blinkenlights.c)
+TARGET_LINK_LIBRARIES(usrp2_blinkenlights.elf libusrp2fw)
+GEN_OUTPUTS(usrp2_blinkenlights.elf)
diff --git a/firmware/microblaze/usrp2/eth_phy.h b/firmware/zpu/usrp2/eth_phy.h
index 6c16f97b7..6c16f97b7 100644
--- a/firmware/microblaze/usrp2/eth_phy.h
+++ b/firmware/zpu/usrp2/eth_phy.h
diff --git a/firmware/microblaze/usrp2/ethernet.c b/firmware/zpu/usrp2/ethernet.c
index 5d4654bda..5d4654bda 100644
--- a/firmware/microblaze/usrp2/ethernet.c
+++ b/firmware/zpu/usrp2/ethernet.c
diff --git a/firmware/microblaze/usrp2/memory_map.h b/firmware/zpu/usrp2/memory_map.h
index eac0c217f..ca7453c24 100644
--- a/firmware/microblaze/usrp2/memory_map.h
+++ b/firmware/zpu/usrp2/memory_map.h
@@ -18,7 +18,7 @@
 
 /* Overall Memory Map
  *   0000-7FFF  32K   RAM space (16K on 1500, 24K on 2000, 32K on DSP)
- *   8000-BFFF  16K   Buffer Pool
+ *   8000-BFFF  16K   Packet Router
  *   C000-FFFF  16K   Peripherals
  */
 
@@ -45,22 +45,18 @@
 #define RAM_BASE 0x0000
 
 ////////////////////////////////////////////////////////////////
-// Buffer Pool RAM, Slave 1
+// Packet Router RAM, Slave 1
 //
-// The buffers themselves are located in Slave 1, Buffer Pool RAM.
-// The status registers are in Slave 5, Buffer Pool Status.
+// The buffers themselves are located in Slave 1, Packet Router RAM.
+// The status registers are in Slave 5, Packet Router Status.
 // The control register is in Slave 7, Settings Bus.
 
-#define BUFFER_POOL_RAM_BASE 0x8000
+#define ROUTER_RAM_BASE 0x8000
 
-#define	NBUFFERS                8
-#define BP_NLINES	   0x0200	// number of 32-bit lines in a buffer
-#define BP_LAST_LINE	(BP_NLINES - 1)	// last line in a buffer
+#define RAM_NLINES	   0x0200	// number of 32-bit lines in a buffer
 
-#define buffer_pool_ram \
-  ((uint32_t *) BUFFER_POOL_RAM_BASE)
-
-#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES])
+#define _router_ram ((uint32_t *) ROUTER_RAM_BASE)
+#define router_ram(n) (&_router_ram[(n) * RAM_NLINES])
 
 
 /////////////////////////////////////////////////////
@@ -164,93 +160,25 @@ typedef struct {
 #define gpio_base ((gpio_regs_t *) GPIO_BASE)
 
 ///////////////////////////////////////////////////
-// Buffer Pool Status, Slave 5
+// Packet Router Status, Slave 5
 //
-// The buffers themselves are located in Slave 1, Buffer Pool RAM.
-// The status registers are in Slave 5, Buffer Pool Status.
+// The buffers themselves are located in Slave 1, Packet Router RAM.
+// The status registers are in Slave 5, Packet Router Status.
 // The control register is in Slave 7, Settings Bus.
 
-#define BUFFER_POOL_STATUS_BASE 0xCC00
+#define ROUTER_STATUS_BASE 0xCC00
 
 typedef struct {
-  volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer
-  volatile uint32_t status;	         // error and done flags
+  volatile uint32_t _padding[8];
+  volatile uint32_t status;
   volatile uint32_t hw_config;	         // see below
   volatile uint32_t dummy[3];
   volatile uint32_t irqs;
   volatile uint32_t pri_enc_bp_status;
   volatile uint32_t cycle_count;
-} buffer_pool_status_t;
+} router_status_t;
 
-#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
-
-/*
- * Buffer n's xfer is done.
- * Clear this bit by issuing bp_clear_buf(n)
- */
-#define BPS_DONE(n)     (0x00000001 << (n))
-#define BPS_DONE_0	BPS_DONE(0)
-#define BPS_DONE_1	BPS_DONE(1)
-#define BPS_DONE_2	BPS_DONE(2)
-#define BPS_DONE_3	BPS_DONE(3)
-#define BPS_DONE_4	BPS_DONE(4)
-#define BPS_DONE_5	BPS_DONE(5)
-#define BPS_DONE_6	BPS_DONE(6)
-#define BPS_DONE_7	BPS_DONE(7)
-
-/*
- * Buffer n's xfer had an error.
- * Clear this bit by issuing bp_clear_buf(n)
- */
-#define BPS_ERROR(n)	(0x00000100 << (n))
-#define BPS_ERROR_0	BPS_ERROR(0)
-#define BPS_ERROR_1	BPS_ERROR(1)
-#define BPS_ERROR_2	BPS_ERROR(2)
-#define BPS_ERROR_3	BPS_ERROR(3)
-#define BPS_ERROR_4	BPS_ERROR(4)
-#define BPS_ERROR_5	BPS_ERROR(5)
-#define BPS_ERROR_6	BPS_ERROR(6)
-#define BPS_ERROR_7	BPS_ERROR(7)
-
-/*
- * Buffer n is idle.  A buffer is idle if it's not
- * DONE, ERROR, or processing a transaction.  If it's
- * IDLE, it's safe to start a new transaction.
- *
- * Clear this bit by starting a xfer with
- * bp_send_from_buf or bp_receive_to_buf.
- */
-#define BPS_IDLE(n)     (0x00010000 << (n))
-#define BPS_IDLE_0	BPS_IDLE(0)
-#define BPS_IDLE_1	BPS_IDLE(1)
-#define BPS_IDLE_2	BPS_IDLE(2)
-#define BPS_IDLE_3	BPS_IDLE(3)
-#define BPS_IDLE_4	BPS_IDLE(4)
-#define BPS_IDLE_5	BPS_IDLE(5)
-#define BPS_IDLE_6	BPS_IDLE(6)
-#define BPS_IDLE_7	BPS_IDLE(7)
-
-/*
- * Buffer n has a "slow path" packet in it.
- * This bit is orthogonal to the bits above and indicates that
- * the FPGA ethernet rx protocol engine has identified this packet
- * as one requiring firmware intervention.
- */
-#define BPS_SLOWPATH(n) (0x01000000 << (n))
-#define BPS_SLOWPATH_0	BPS_SLOWPATH(0)
-#define BPS_SLOWPATH_1	BPS_SLOWPATH(1)
-#define BPS_SLOWPATH_2	BPS_SLOWPATH(2)
-#define BPS_SLOWPATH_3	BPS_SLOWPATH(3)
-#define BPS_SLOWPATH_4	BPS_SLOWPATH(4)
-#define BPS_SLOWPATH_5	BPS_SLOWPATH(5)
-#define BPS_SLOWPATH_6	BPS_SLOWPATH(6)
-#define BPS_SLOWPATH_7	BPS_SLOWPATH(7)
-
-
-#define BPS_DONE_ALL	  0x000000ff	// mask of all dones
-#define BPS_ERROR_ALL	  0x0000ff00	// mask of all errors
-#define BPS_IDLE_ALL      0x00ff0000	// mask of all idles
-#define BPS_SLOWPATH_ALL  0xff000000	// mask of all slowpaths
+#define router_status ((router_status_t *) ROUTER_STATUS_BASE)
 
 // The hw_config register
 
@@ -263,7 +191,7 @@ typedef struct {
 inline static int
 hwconfig_simulation_p(void)
 {
-  return buffer_pool_status->hw_config & HWC_SIMULATION;
+  return router_status->hw_config & HWC_SIMULATION;
 }
 
 /*!
@@ -273,7 +201,7 @@ hwconfig_simulation_p(void)
 inline static int
 hwconfig_wishbone_divisor(void)
 {
-  return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK;
+  return router_status->hw_config & HWC_WB_CLK_DIV_MASK;
 }
 
 ///////////////////////////////////////////////////
@@ -295,13 +223,13 @@ hwconfig_wishbone_divisor(void)
 #define MISC_OUTPUT_BASE        0xD400
 #define	TX_PROTOCOL_ENGINE_BASE 0xD480
 #define	RX_PROTOCOL_ENGINE_BASE 0xD4C0
-#define BUFFER_POOL_CTRL_BASE   0xD500
+#define ROUTER_CTRL_BASE   0xD500
 #define LAST_SETTING_REG        0xD7FC	// last valid setting register
 
 #define SR_MISC 0
 #define SR_TX_PROT_ENG 32
 #define SR_RX_PROT_ENG 48
-#define SR_BUFFER_POOL_CTRL 64
+#define SR_ROUTER_CTRL 64
 #define SR_UDP_SM 96
 #define SR_TX_DSP 208
 #define SR_TX_CTRL 224
@@ -313,53 +241,17 @@ hwconfig_wishbone_divisor(void)
 
 #define	_SR_ADDR(sr)	(MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t))
 
-// --- buffer pool control regs ---
+// --- packet router control regs ---
 
 typedef struct {
-  volatile uint32_t ctrl;
-} buffer_pool_ctrl_t;
-
-// buffer pool ports
-
-#define	PORT_SERDES	0	// serial/deserializer
-#define	PORT_DSP	1	// DSP tx or rx pipeline
-#define	PORT_ETH	2	// ethernet tx or rx
-#define	PORT_RAM	3	// RAM tx or rx
-
-// the buffer pool ctrl register fields
-
-#define BPC_BUFFER(n) (((n) & 0xf) << 28)
-#define   BPC_BUFFER_MASK      BPC_BUFFER(~0)
-#define   BPC_BUFFER_0	       BPC_BUFFER(0)
-#define   BPC_BUFFER_1	       BPC_BUFFER(1)
-#define   BPC_BUFFER_2	       BPC_BUFFER(2)
-#define   BPC_BUFFER_3	       BPC_BUFFER(3)
-#define   BPC_BUFFER_4	       BPC_BUFFER(4)
-#define   BPC_BUFFER_5	       BPC_BUFFER(5)
-#define   BPC_BUFFER_6	       BPC_BUFFER(6)
-#define   BPC_BUFFER_7	       BPC_BUFFER(7)
-#define	  BPC_BUFFER_NIL       BPC_BUFFER(0x8)	// disable
-
-#define BPC_PORT(n) (((n) & 0x7) << 25)
-#define   BPC_PORT_MASK        BPC_PORT(~0)
-#define   BPC_PORT_SERDES      BPC_PORT(PORT_SERDES)
-#define   BPC_PORT_DSP	       BPC_PORT(PORT_DSP)
-#define   BPC_PORT_ETH         BPC_PORT(PORT_ETH)
-#define   BPC_PORT_RAM         BPC_PORT(PORT_RAM)
-#define   BPC_PORT_NIL	       BPC_PORT(0x4)   	// disable
-
-#define	BPC_CLR	       	       (1 << 24)  // mutually excl commands
-#define	BPC_READ	       (1 << 23)
-#define BPC_WRITE              (1 << 22)
-
-#define BPC_STEP(step) (((step) & 0xf) << 18)
-#define   BPC_STEP_MASK	       BPC_STEP(~0)
-#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
-#define   BPC_LAST_LINE_MASK   BPC_LAST_LINE(~0)
-#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
-#define   BPC_FIRST_LINE_MASK  BPC_FIRST_LINE(~0)
-
-#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
+  volatile uint32_t mode_ctrl;
+  volatile uint32_t ip_addr;
+  volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16)
+  volatile uint32_t cpu_out_ctrl;
+  volatile uint32_t cpu_inp_ctrl;
+} router_ctrl_t;
+
+#define router_ctrl ((router_ctrl_t *) ROUTER_CTRL_BASE)
 
 // --- misc outputs ---
 
@@ -435,11 +327,21 @@ typedef struct {
     uint32_t length;
     uint32_t checksum; //word 22
   } udp_hdr;
-  volatile uint32_t _pad[32-23];
+  volatile uint32_t _pad[1];
+  volatile uint32_t dsp0_port;
+  volatile uint32_t err0_port;
+  volatile uint32_t dsp1_port;
+  volatile uint32_t err1_port;
 } sr_udp_sm_t;
 
 // control bits (all expect UDP_SM_LAST_WORD are mutually exclusive)
 
+// Insert a UDP source port from the table
+#define UDP_SM_INS_UDP_SRC_PORT     (1 << 21)
+
+// Insert a UDP dest port from the table
+#define UDP_SM_INS_UDP_DST_PORT     (1 << 20)
+
 // This is the last word of the header
 #define	UDP_SM_LAST_WORD		(1 << 19)
 
diff --git a/firmware/microblaze/usrp2/sd.c b/firmware/zpu/usrp2/sd.c
index d000b28ae..d000b28ae 100644
--- a/firmware/microblaze/usrp2/sd.c
+++ b/firmware/zpu/usrp2/sd.c
diff --git a/firmware/microblaze/usrp2/sd.h b/firmware/zpu/usrp2/sd.h
index e2d0ae38e..e2d0ae38e 100644
--- a/firmware/microblaze/usrp2/sd.h
+++ b/firmware/zpu/usrp2/sd.h
diff --git a/firmware/microblaze/usrp2/udp_fw_update.c b/firmware/zpu/usrp2/udp_fw_update.c
index 14eb0b1ee..14eb0b1ee 100644
--- a/firmware/microblaze/usrp2/udp_fw_update.c
+++ b/firmware/zpu/usrp2/udp_fw_update.c
diff --git a/firmware/zpu/usrp2p/CMakeLists.txt b/firmware/zpu/usrp2p/CMakeLists.txt
new file mode 100644
index 000000000..41ef8f1dd
--- /dev/null
+++ b/firmware/zpu/usrp2p/CMakeLists.txt
@@ -0,0 +1,48 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+INCLUDE(${CMAKE_SOURCE_DIR}/lib/CMakeLists.txt)
+INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
+
+ADD_DEFINITIONS(-DUSRP2P)
+
+ADD_LIBRARY(libusrp2pfw STATIC
+    ${COMMON_SRCS}
+    spif.c
+    spi_flash.c
+    spi_flash_read.c
+    bootloader_utils.c
+    ethernet.c
+    xilinx_s3_icap.c
+    udp_fw_update.c
+)
+
+ADD_SUBDIRECTORY(bootloader)
+
+########################################################################
+ADD_EXECUTABLE(usrp2p_txrx_uhd.elf ${CMAKE_SOURCE_DIR}/apps/txrx_uhd.c)
+TARGET_LINK_LIBRARIES(usrp2p_txrx_uhd.elf libusrp2pfw)
+GEN_OUTPUTS(usrp2p_txrx_uhd.elf)
+
+ADD_EXECUTABLE(usrp2p_blinkenlights.elf ${CMAKE_SOURCE_DIR}/apps/blinkenlights.c)
+TARGET_LINK_LIBRARIES(usrp2p_blinkenlights.elf libusrp2pfw)
+GEN_OUTPUTS(usrp2p_blinkenlights.elf)
+
+ADD_EXECUTABLE(usrp2p_uart_flash_loader.elf ${CMAKE_SOURCE_DIR}/apps/uart_flash_loader.c)
+TARGET_LINK_LIBRARIES(usrp2p_uart_flash_loader.elf libusrp2pfw)
+GEN_OUTPUTS(usrp2p_uart_flash_loader.elf)
diff --git a/firmware/microblaze/usrp2p/bootconfig.h b/firmware/zpu/usrp2p/bootconfig.h
index 35c2726ed..35c2726ed 100644
--- a/firmware/microblaze/usrp2p/bootconfig.h
+++ b/firmware/zpu/usrp2p/bootconfig.h
diff --git a/firmware/zpu/usrp2p/bootloader/CMakeLists.txt b/firmware/zpu/usrp2p/bootloader/CMakeLists.txt
new file mode 100644
index 000000000..41c86cc9a
--- /dev/null
+++ b/firmware/zpu/usrp2p/bootloader/CMakeLists.txt
@@ -0,0 +1,39 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+########################################################################
+INCLUDE(FindPythonInterp)
+
+MACRO(GEN_RMI target)
+    GET_FILENAME_COMPONENT(name ${target} NAME_WE)
+    #command to create a rmi from elf
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${name}.rmi DEPENDS ${name}.bin
+        COMMAND ${PYTHON_EXECUTABLE}
+        ARGS ${CMAKE_SOURCE_DIR}/bin/bin_to_ram_macro_init.py ${name}.bin ${name}.rmi
+    )
+    #add a top level target for output files
+    ADD_CUSTOM_TARGET(
+        ${name}_rmi ALL DEPENDS ${name}.rmi
+    )
+ENDMACRO(GEN_RMI)
+
+########################################################################
+ADD_EXECUTABLE(init_bootloader.elf init_bootloader.c)
+TARGET_LINK_LIBRARIES(init_bootloader.elf libusrp2pfw)
+GEN_OUTPUTS(init_bootloader.elf)
+GEN_RMI(init_bootloader.bin)
diff --git a/firmware/microblaze/usrp2p/bootloader/fpga_bootloader.c b/firmware/zpu/usrp2p/bootloader/fpga_bootloader.c
index 9feff6ecd..9feff6ecd 100644
--- a/firmware/microblaze/usrp2p/bootloader/fpga_bootloader.c
+++ b/firmware/zpu/usrp2p/bootloader/fpga_bootloader.c
diff --git a/firmware/microblaze/usrp2p/bootloader/fw_bootloader.c b/firmware/zpu/usrp2p/bootloader/fw_bootloader.c
index a2c32bf8e..a2c32bf8e 100644
--- a/firmware/microblaze/usrp2p/bootloader/fw_bootloader.c
+++ b/firmware/zpu/usrp2p/bootloader/fw_bootloader.c
diff --git a/firmware/microblaze/usrp2p/bootloader/icap_test.c b/firmware/zpu/usrp2p/bootloader/icap_test.c
index 5feb9d014..5feb9d014 100644
--- a/firmware/microblaze/usrp2p/bootloader/icap_test.c
+++ b/firmware/zpu/usrp2p/bootloader/icap_test.c
diff --git a/firmware/microblaze/usrp2p/bootloader/init_bootloader.c b/firmware/zpu/usrp2p/bootloader/init_bootloader.c
index 1d9d681d7..cfa80ffea 100644
--- a/firmware/microblaze/usrp2p/bootloader/init_bootloader.c
+++ b/firmware/zpu/usrp2p/bootloader/init_bootloader.c
@@ -18,7 +18,7 @@
 #include <i2c.h>
 #include "usrp2/fw_common.h"
 
-void pic_interrupt_handler() __attribute__ ((interrupt_handler));
+//void pic_interrupt_handler() __attribute__ ((interrupt_handler));
 
 void pic_interrupt_handler()
 {
@@ -42,7 +42,7 @@ void load_ihex(void) { //simple IHEX parser to load proper records into RAM. loa
 			} else if(ihex_record.type == 1) { //end of record
 				puts("OK");
 				//load main firmware
-				start_program(RAM_BASE);
+				start_program();
 				puts("ERROR: main image returned! Back in IHEX load mode.");
 			} else puts("NOK"); //RAM loads do not support extended segment address records (04) -- upper 16 bits are always "0".
 		} else puts("NOK");
@@ -56,12 +56,12 @@ void delay(uint32_t t) {
 int main(int argc, char *argv[]) {
   hal_disable_ints();	// In case we got here via jmp 0x0
 	output_regs->leds = 0xFF;
-	delay(500000);
+	delay(5000);
 	output_regs->leds = 0x00;
 	hal_uart_init();
 	spif_init();
 	i2c_init(); //for EEPROM
-	puts("USRP2+ bootloader\n");
+	puts("USRP2+ bootloader super ultra ZPU edition\n");
 	
 	bool production_image = find_safe_booted_flag();
 	set_safe_booted_flag(0); //haven't booted yet
@@ -71,7 +71,7 @@ int main(int argc, char *argv[]) {
 		if(is_valid_fw_image(SAFE_FW_IMAGE_LOCATION_ADDR)) {
 				set_safe_booted_flag(1); //let the firmware know it's the safe image
 				spi_flash_read(SAFE_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE);
-				start_program(RAM_BASE);
+				start_program();
 				puts("ERROR: return from main program! This should never happen!");
 				icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR);
 			} else {
@@ -85,7 +85,7 @@ int main(int argc, char *argv[]) {
 		if(is_valid_fpga_image(PROD_FPGA_IMAGE_LOCATION_ADDR)) {
 			puts("Valid production FPGA image found. Attempting to boot.");
 			set_safe_booted_flag(1);
-			delay(30000); //so serial output can finish
+			delay(300); //so serial output can finish
 			icap_reload_fpga(PROD_FPGA_IMAGE_LOCATION_ADDR);
 		}
 		puts("No valid production FPGA image found.\nAttempting to load production firmware...");
@@ -93,17 +93,23 @@ int main(int argc, char *argv[]) {
 	if(is_valid_fw_image(PROD_FW_IMAGE_LOCATION_ADDR)) {
 		puts("Valid production firmware found. Loading...");
 		spi_flash_read(PROD_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE);
-		start_program(RAM_BASE);
+		puts("Finished loading. Starting image.");
+		delay(300);
+		start_program();
 		puts("ERROR: Return from main program! This should never happen!");
 		//if this happens, though, the safest thing to do is reboot the whole FPGA and start over.
+		delay(300);
 		icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR);
 		return 1;
 	}
 	puts("No valid production firmware found. Trying safe firmware...");
 	if(is_valid_fw_image(SAFE_FW_IMAGE_LOCATION_ADDR)) {
 		spi_flash_read(SAFE_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE);
-		start_program(RAM_BASE);
+		puts("Finished loading. Starting image.");
+		delay(300);
+		start_program();
 		puts("ERROR: return from main program! This should never happen!");
+		delay(300);
 		icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR);
 		return 1;
 	}
diff --git a/firmware/microblaze/usrp2p/bootloader/serial_loader_burner.c b/firmware/zpu/usrp2p/bootloader/serial_loader_burner.c
index 4ac4df454..4ac4df454 100644
--- a/firmware/microblaze/usrp2p/bootloader/serial_loader_burner.c
+++ b/firmware/zpu/usrp2p/bootloader/serial_loader_burner.c
diff --git a/firmware/microblaze/usrp2p/bootloader/spi_bootloader.c b/firmware/zpu/usrp2p/bootloader/spi_bootloader.c
index 678e66cf7..678e66cf7 100644
--- a/firmware/microblaze/usrp2p/bootloader/spi_bootloader.c
+++ b/firmware/zpu/usrp2p/bootloader/spi_bootloader.c
diff --git a/firmware/microblaze/usrp2p/bootloader/u2p2-rom.ld b/firmware/zpu/usrp2p/bootloader/u2p2-rom.ld
index 4c9eaa8e5..4c9eaa8e5 100644
--- a/firmware/microblaze/usrp2p/bootloader/u2p2-rom.ld
+++ b/firmware/zpu/usrp2p/bootloader/u2p2-rom.ld
diff --git a/firmware/zpu/usrp2p/bootloader_utils.c b/firmware/zpu/usrp2p/bootloader_utils.c
new file mode 100644
index 000000000..379c5f957
--- /dev/null
+++ b/firmware/zpu/usrp2p/bootloader_utils.c
@@ -0,0 +1,48 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2010 Ettus Research LLC
+ *
+ */
+
+//contains routines for loading programs from Flash. depends on Flash libraries.
+//also contains routines for reading / writing EEPROM flags for the bootloader
+#include <stdbool.h>
+#include <string.h>
+#include <bootloader_utils.h>
+#include <spi_flash.h>
+#include <memory_map.h>
+#include <nonstdio.h>
+
+int is_valid_fpga_image(uint32_t addr) {
+//	printf("is_valid_fpga_image(): starting with addr=%x...\n", addr);
+	uint8_t imgbuf[64];
+	spi_flash_read(addr, 64, imgbuf);
+	//we're just looking for leading 0xFF padding, followed by the sync bytes 0xAA 0x99
+	for(size_t i = 0; i<63; i++) {
+		if(imgbuf[i] == 0xFF) continue;
+		if(imgbuf[i] == 0xAA && imgbuf[i+1] == 0x99) {
+			//printf("is_valid_fpga_image(): found valid FPGA image\n");
+			return 1;
+		}
+	}
+	
+	return 0;
+}
+
+int is_valid_fw_image(uint32_t addr) {
+	static const uint8_t fwheader[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x80, 0x70}; //just lookin for a jump to anywhere located at the reset vector
+	//printf("is_valid_fw_image(): starting with addr=%x...\n", addr);
+	uint8_t buf[12];
+	spi_flash_read(addr, 6, buf);
+	//printf("is_valid_fw_image(): read ");
+	//for(int i = 0; i < 5; i++) printf("%x ", buf[i]);
+	//printf("\n");
+	return memcmp(buf, fwheader, 6) == 0;
+}
+
+void start_program(void)
+{
+	//ignoring the addr now
+	//all this does is tap that register
+	*((volatile uint32_t *) SR_ADDR_BLDRDONE) = 1;
+}
diff --git a/firmware/microblaze/usrp2p/bootloader_utils.h b/firmware/zpu/usrp2p/bootloader_utils.h
index f597c0113..0f49ae6cd 100644
--- a/firmware/microblaze/usrp2p/bootloader_utils.h
+++ b/firmware/zpu/usrp2p/bootloader_utils.h
@@ -9,8 +9,8 @@
 //we're working in bytes and byte addresses so we can run the same code with Flash chips of different sector sizes.
 //it's really 1463736, but rounded up to 1.5MB
 #define FPGA_IMAGE_SIZE_BYTES 1572864
-//instead of 32K, we write 31K because we're using the top 1K for stack space!
-#define FW_IMAGE_SIZE_BYTES 31744
+//16K
+#define FW_IMAGE_SIZE_BYTES 0x3fff
 
 #define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000
 #define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000
@@ -19,4 +19,4 @@
 
 int is_valid_fpga_image(uint32_t addr);
 int is_valid_fw_image(uint32_t addr);
-void start_program(uint32_t addr);
+void start_program(void);
diff --git a/firmware/microblaze/usrp2p/eth_phy.h b/firmware/zpu/usrp2p/eth_phy.h
index d233e96e8..d233e96e8 100644
--- a/firmware/microblaze/usrp2p/eth_phy.h
+++ b/firmware/zpu/usrp2p/eth_phy.h
diff --git a/firmware/microblaze/usrp2p/ethernet.c b/firmware/zpu/usrp2p/ethernet.c
index 36d6a17ca..03891f959 100644
--- a/firmware/microblaze/usrp2p/ethernet.c
+++ b/firmware/zpu/usrp2p/ethernet.c
@@ -279,101 +279,6 @@ ethernet_init(void)
   eth_mac_miim_write(PHY_CTRL, t | MII_CR_RESTART_AUTO_NEG);
 }
 
-static bool 
-unprogrammed(const void *t, size_t len)
-{
-  int i;
-  uint8_t *p = (uint8_t *)t;
-  bool all_zeros = true;
-  bool all_ones =  true;
-  for (i = 0; i < len; i++){
-    all_zeros &= p[i] == 0x00;
-    all_ones  &= p[i] == 0xff;
-  }
-  return all_ones | all_zeros;
-}
-
-//////////////////// MAC Addr Stuff ///////////////////////
-/*
-static int8_t src_mac_addr_initialized = false;
-static eth_mac_addr_t src_mac_addr = {{
-    0x00, 0x50, 0xC2, 0x85, 0x3f, 0xff
-  }};
-
-const eth_mac_addr_t *
-ethernet_mac_addr(void)
-{
-  if (!src_mac_addr_initialized){    // fetch from eeprom
-    src_mac_addr_initialized = true;
-
-    // if we're simulating, don't read the EEPROM model, it's REALLY slow
-    if (hwconfig_simulation_p())
-      return &src_mac_addr;
-    
-    eth_mac_addr_t tmp;
-    bool ok = eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_MAC_ADDR, &tmp, sizeof(tmp));
-    if (!ok || unprogrammed(&tmp, sizeof(tmp))){
-      // use the default
-    }
-    else
-      src_mac_addr = tmp;
-  }
-
-  return &src_mac_addr;
-}
-
-bool
-ethernet_set_mac_addr(const eth_mac_addr_t *t)
-{
-  bool ok = eeprom_write(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_MAC_ADDR, t, sizeof(eth_mac_addr_t));
-  if (ok){
-    src_mac_addr = *t;
-    src_mac_addr_initialized = true;
-    //eth_mac_set_addr(t); //this breaks the link
-  }
-
-  return ok;
-}
-
-//////////////////// IP Addr Stuff ///////////////////////
-
-static int8_t src_ip_addr_initialized = false;
-static struct ip_addr src_ip_addr = {
-    (192 << 24 | 168 << 16 | 10 << 8 | 2 << 0)
-};
-
-
-const struct ip_addr *get_ip_addr(void)
-{
-  if (!src_ip_addr_initialized){    // fetch from eeprom
-    src_ip_addr_initialized = true;
-
-    // if we're simulating, don't read the EEPROM model, it's REALLY slow
-    if (hwconfig_simulation_p())
-      return &src_ip_addr;
-    
-    struct ip_addr tmp;
-    bool ok = eeprom_read(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_IP_ADDR, &tmp, sizeof(tmp));
-    if (!ok || unprogrammed(&tmp, sizeof(tmp))){
-      // use the default
-    }
-    else
-      src_ip_addr = tmp;
-  }
-
-  return &src_ip_addr;
-}
-
-bool set_ip_addr(const struct ip_addr *t){
-  bool ok = eeprom_write(USRP2_I2C_ADDR_MBOARD, USRP2_EE_MBOARD_IP_ADDR, t, sizeof(struct ip_addr));
-  if (ok){
-    src_ip_addr = *t;
-    src_ip_addr_initialized = true;
-  }
-
-  return ok;
-}
-*/
 int
 ethernet_check_errors(void)
 {
diff --git a/firmware/microblaze/usrp2p/memory_map.h b/firmware/zpu/usrp2p/memory_map.h
index 3b2dc0057..151c71237 100644
--- a/firmware/microblaze/usrp2p/memory_map.h
+++ b/firmware/zpu/usrp2p/memory_map.h
@@ -16,38 +16,6 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* Overall Memory Map
- *   0000-FFFF  64K    RAM space
- *
- *   0000-1FFF  8K     Boot RAM
- *   2000-5FFF  16K    Buffer pool
- *   6000-7FFF  8K     Peripherals
- *   8000-FFFF  32K    Main System RAM
-
-
-From u2plus_core.v:
-wb_1master #(.decode_w(8),
-.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000),  // 0-8K, Boot RAM
-.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000),  // 16K-32K, Buffer Pool
-.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111),  // SPI 0x3000
-.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111),  // I2C 0x3100
-.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111),  // GPIO 0x3200
-.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111),  // Readback 0x3300
-.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111),  // Ethernet MAC 0x3400
-.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000),  // 8-12K, Settings Bus (only uses 1K) 0x2000-0x2FFF
-.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111),  // PIC 0x3500
-.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111),  // Unused 0x3600
-.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111),  // UART 0x3700
-.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111),  // ATR 0x3800
-.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111),  // Unused 0x3900
-.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111),  // ICAP 0x3A00
-.se_addr(8'b0011_1011),.se_mask(8'b1111_1111),  // SPI Flash 0x3B00
-.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000),  // 32-64K, Main RAM 0x8000-0xFFFF
-               .dw(dw),.aw(aw),.sw(sw)) wb_1master
-
- */
-
-
 #ifndef INCLUDED_MEMORY_MAP_H
 #define INCLUDED_MEMORY_MAP_H
 
@@ -70,27 +38,23 @@ wb_1master #(.decode_w(8),
 
 
 ////////////////////////////////////////////////////////////////
-// Buffer Pool RAM, Slave 1
+// Packet Router RAM, Slave 1
 //
-// The buffers themselves are located in Slave 1, Buffer Pool RAM.
-// The status registers are in Slave 5, Buffer Pool Status.
+// The buffers themselves are located in Slave 1, Packet Router RAM.
+// The status registers are in Slave 5, Packet Router Status.
 // The control register is in Slave 7, Settings Bus.
 
-#define BUFFER_POOL_RAM_BASE 0x4000
-
-#define	NBUFFERS                8
-#define BP_NLINES	   0x0200	// number of 32-bit lines in a buffer
-#define BP_LAST_LINE	(BP_NLINES - 1)	// last line in a buffer
+#define ROUTER_RAM_BASE 0x4000
 
-#define buffer_pool_ram \
-  ((uint32_t *) BUFFER_POOL_RAM_BASE)
+#define RAM_NLINES	   0x0200	// number of 32-bit lines in a buffer
 
-#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES])
+#define _router_ram ((uint32_t *) ROUTER_RAM_BASE)
+#define router_ram(n) (&_router_ram[(n) * RAM_NLINES])
 
 
 /////////////////////////////////////////////////////
 // SPI Core, Slave 2.  See core docs for more info
-#define SPI_BASE 0x3000   // Base address (16-bit) is base peripheral addr
+#define SPI_BASE 0x6000   // Base address (16-bit) is base peripheral addr
 
 typedef struct {
   volatile uint32_t	txrx0;
@@ -129,7 +93,7 @@ typedef struct {
 // I2C, Slave 3
 // See Wishbone I2C-Master Core Specification.
 
-#define I2C_BASE 0x3100
+#define I2C_BASE 0x6100
 
 typedef struct {
   volatile uint32_t  prescaler_lo;	// r/w
@@ -171,7 +135,7 @@ typedef struct {
 //
 // These go to the daughterboard i/o pins
 
-#define GPIO_BASE 0x3200
+#define GPIO_BASE 0x6200
 
 typedef struct {
   volatile uint32_t	io;	  // tx data in high 16, rx in low 16
@@ -189,95 +153,27 @@ typedef struct {
 #define gpio_base ((gpio_regs_t *) GPIO_BASE)
 
 ///////////////////////////////////////////////////
-// Buffer Pool Status, Slave 5
+// Packet Router Status, Slave 5
 //
-// The buffers themselves are located in Slave 1, Buffer Pool RAM.
-// The status registers are in Slave 5, Buffer Pool Status.
+// The buffers themselves are located in Slave 1, Packet Router RAM.
+// The status registers are in Slave 5, Packet Router Status.
 // The control register is in Slave 7, Settings Bus.
 
-#define BUFFER_POOL_STATUS_BASE 0x3300
+#define ROUTER_STATUS_BASE 0x6300
 
 typedef struct {
-  volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer
-  volatile uint32_t status;	         // error and done flags
+  volatile uint32_t _padding[8];
+  volatile uint32_t status;
   volatile uint32_t hw_config;	         // see below
   volatile uint32_t dummy[3];
   volatile uint32_t irqs;
   volatile uint32_t pri_enc_bp_status;
   volatile uint32_t cycle_count;
-} buffer_pool_status_t;
+} router_status_t;
 
-#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
+#define router_status ((router_status_t *) ROUTER_STATUS_BASE)
 
-#define BUTTON_PUSHED ((buffer_pool_status->irqs & PIC_BUTTON) ? 0 : 1)
-
-/*
- * Buffer n's xfer is done.
- * Clear this bit by issuing bp_clear_buf(n)
- */
-#define BPS_DONE(n)     (0x00000001 << (n))
-#define BPS_DONE_0	BPS_DONE(0)
-#define BPS_DONE_1	BPS_DONE(1)
-#define BPS_DONE_2	BPS_DONE(2)
-#define BPS_DONE_3	BPS_DONE(3)
-#define BPS_DONE_4	BPS_DONE(4)
-#define BPS_DONE_5	BPS_DONE(5)
-#define BPS_DONE_6	BPS_DONE(6)
-#define BPS_DONE_7	BPS_DONE(7)
-
-/*
- * Buffer n's xfer had an error.
- * Clear this bit by issuing bp_clear_buf(n)
- */
-#define BPS_ERROR(n)	(0x00000100 << (n))
-#define BPS_ERROR_0	BPS_ERROR(0)
-#define BPS_ERROR_1	BPS_ERROR(1)
-#define BPS_ERROR_2	BPS_ERROR(2)
-#define BPS_ERROR_3	BPS_ERROR(3)
-#define BPS_ERROR_4	BPS_ERROR(4)
-#define BPS_ERROR_5	BPS_ERROR(5)
-#define BPS_ERROR_6	BPS_ERROR(6)
-#define BPS_ERROR_7	BPS_ERROR(7)
-
-/*
- * Buffer n is idle.  A buffer is idle if it's not
- * DONE, ERROR, or processing a transaction.  If it's
- * IDLE, it's safe to start a new transaction.
- *
- * Clear this bit by starting a xfer with
- * bp_send_from_buf or bp_receive_to_buf.
- */
-#define BPS_IDLE(n)     (0x00010000 << (n))
-#define BPS_IDLE_0	BPS_IDLE(0)
-#define BPS_IDLE_1	BPS_IDLE(1)
-#define BPS_IDLE_2	BPS_IDLE(2)
-#define BPS_IDLE_3	BPS_IDLE(3)
-#define BPS_IDLE_4	BPS_IDLE(4)
-#define BPS_IDLE_5	BPS_IDLE(5)
-#define BPS_IDLE_6	BPS_IDLE(6)
-#define BPS_IDLE_7	BPS_IDLE(7)
-
-/*
- * Buffer n has a "slow path" packet in it.
- * This bit is orthogonal to the bits above and indicates that
- * the FPGA ethernet rx protocol engine has identified this packet
- * as one requiring firmware intervention.
- */
-#define BPS_SLOWPATH(n) (0x01000000 << (n))
-#define BPS_SLOWPATH_0	BPS_SLOWPATH(0)
-#define BPS_SLOWPATH_1	BPS_SLOWPATH(1)
-#define BPS_SLOWPATH_2	BPS_SLOWPATH(2)
-#define BPS_SLOWPATH_3	BPS_SLOWPATH(3)
-#define BPS_SLOWPATH_4	BPS_SLOWPATH(4)
-#define BPS_SLOWPATH_5	BPS_SLOWPATH(5)
-#define BPS_SLOWPATH_6	BPS_SLOWPATH(6)
-#define BPS_SLOWPATH_7	BPS_SLOWPATH(7)
-
-
-#define BPS_DONE_ALL	  0x000000ff	// mask of all dones
-#define BPS_ERROR_ALL	  0x0000ff00	// mask of all errors
-#define BPS_IDLE_ALL      0x00ff0000	// mask of all idles
-#define BPS_SLOWPATH_ALL  0xff000000	// mask of all slowpaths
+#define BUTTON_PUSHED ((router_status->irqs & PIC_BUTTON) ? 0 : 1)
 
 // The hw_config register
 
@@ -290,7 +186,7 @@ typedef struct {
 inline static int
 hwconfig_simulation_p(void)
 {
-  return buffer_pool_status->hw_config & HWC_SIMULATION;
+  return router_status->hw_config & HWC_SIMULATION;
 }
 
 /*!
@@ -300,13 +196,13 @@ hwconfig_simulation_p(void)
 inline static int
 hwconfig_wishbone_divisor(void)
 {
-  return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK;
+  return router_status->hw_config & HWC_WB_CLK_DIV_MASK;
 }
 
 ///////////////////////////////////////////////////
 // Ethernet Core, Slave 6
 
-#define ETH_BASE 0x3400
+#define ETH_BASE 0x6400
 
 #include "eth_mac_regs.h"
 
@@ -319,16 +215,12 @@ hwconfig_wishbone_divisor(void)
 // 1KB of address space (== 256 32-bit write-only regs)
 
 
-#define MISC_OUTPUT_BASE        0x2000
-#define	TX_PROTOCOL_ENGINE_BASE 0x2080
-#define	RX_PROTOCOL_ENGINE_BASE 0x20C0
-#define BUFFER_POOL_CTRL_BASE   0x2100
-#define LAST_SETTING_REG        0x23FC	// last valid setting register
+#define MISC_OUTPUT_BASE        0x5000
 
 #define SR_MISC 0
 #define SR_TX_PROT_ENG 32
 #define SR_RX_PROT_ENG 48
-#define SR_BUFFER_POOL_CTRL 64
+#define SR_ROUTER_CTRL 64
 #define SR_UDP_SM 96
 #define SR_TX_DSP 208
 #define SR_TX_CTRL 224
@@ -340,53 +232,19 @@ hwconfig_wishbone_divisor(void)
 
 #define	_SR_ADDR(sr)	(MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t))
 
-// --- buffer pool control regs ---
+#define SR_ADDR_BLDRDONE _SR_ADDR(5)
+
+// --- packet router control regs ---
 
 typedef struct {
-  volatile uint32_t ctrl;
-} buffer_pool_ctrl_t;
-
-// buffer pool ports
-
-#define	PORT_SERDES	0	// serial/deserializer
-#define	PORT_DSP	1	// DSP tx or rx pipeline
-#define	PORT_ETH	2	// ethernet tx or rx
-#define	PORT_RAM	3	// RAM tx or rx
-
-// the buffer pool ctrl register fields
-
-#define BPC_BUFFER(n) (((n) & 0xf) << 28)
-#define   BPC_BUFFER_MASK      BPC_BUFFER(~0)
-#define   BPC_BUFFER_0	       BPC_BUFFER(0)
-#define   BPC_BUFFER_1	       BPC_BUFFER(1)
-#define   BPC_BUFFER_2	       BPC_BUFFER(2)
-#define   BPC_BUFFER_3	       BPC_BUFFER(3)
-#define   BPC_BUFFER_4	       BPC_BUFFER(4)
-#define   BPC_BUFFER_5	       BPC_BUFFER(5)
-#define   BPC_BUFFER_6	       BPC_BUFFER(6)
-#define   BPC_BUFFER_7	       BPC_BUFFER(7)
-#define	  BPC_BUFFER_NIL       BPC_BUFFER(0x8)	// disable
-
-#define BPC_PORT(n) (((n) & 0x7) << 25)
-#define   BPC_PORT_MASK        BPC_PORT(~0)
-#define   BPC_PORT_SERDES      BPC_PORT(PORT_SERDES)
-#define   BPC_PORT_DSP	       BPC_PORT(PORT_DSP)
-#define   BPC_PORT_ETH         BPC_PORT(PORT_ETH)
-#define   BPC_PORT_RAM         BPC_PORT(PORT_RAM)
-#define   BPC_PORT_NIL	       BPC_PORT(0x4)   	// disable
-
-#define	BPC_CLR	       	       (1 << 24)  // mutually excl commands
-#define	BPC_READ	       (1 << 23)
-#define BPC_WRITE              (1 << 22)
-
-#define BPC_STEP(step) (((step) & 0xf) << 18)
-#define   BPC_STEP_MASK	       BPC_STEP(~0)
-#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
-#define   BPC_LAST_LINE_MASK   BPC_LAST_LINE(~0)
-#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
-#define   BPC_FIRST_LINE_MASK  BPC_FIRST_LINE(~0)
-
-#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
+  volatile uint32_t mode_ctrl;
+  volatile uint32_t ip_addr;
+  volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16)
+  volatile uint32_t cpu_out_ctrl;
+  volatile uint32_t cpu_inp_ctrl;
+} router_ctrl_t;
+
+#define router_ctrl ((router_ctrl_t *) _SR_ADDR(SR_ROUTER_CTRL))
 
 // --- misc outputs ---
 
@@ -462,11 +320,21 @@ typedef struct {
     uint32_t length;
     uint32_t checksum; //word 22
   } udp_hdr;
-  volatile uint32_t _pad[32-23];
+  volatile uint32_t _pad[1];
+  volatile uint32_t dsp0_port;
+  volatile uint32_t err0_port;
+  volatile uint32_t dsp1_port;
+  volatile uint32_t err1_port;
 } sr_udp_sm_t;
 
 // control bits (all expect UDP_SM_LAST_WORD are mutually exclusive)
 
+// Insert a UDP source port from the table
+#define UDP_SM_INS_UDP_SRC_PORT     (1 << 21)
+
+// Insert a UDP dest port from the table
+#define UDP_SM_INS_UDP_DST_PORT     (1 << 20)
+
 // This is the last word of the header
 #define	UDP_SM_LAST_WORD		(1 << 19)
 
@@ -679,7 +547,7 @@ typedef struct {
   volatile uint32_t  seqno;	     // Write to init seqno.  It autoincs on match
 } tx_proto_engine_regs_t;
 
-#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE)
+#define tx_proto_engine ((tx_proto_engine_regs_t *) _SR_ADDR(SR_TX_PROT_ENG))
 
 /*
  * --- ethernet rx protocol engine regs (write only) ---
@@ -706,14 +574,14 @@ typedef struct {
   volatile uint32_t  ethertype_pad;  // ethertype in high 16-bits
 } rx_proto_engine_regs_t;
 
-#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE)
+#define rx_proto_engine ((rx_proto_engine_regs_t *) _SR_ADDR(SR_RX_PROT_ENG))
 
 
 
 ///////////////////////////////////////////////////
 // Simple Programmable Interrupt Controller, Slave 8
 
-#define PIC_BASE  0x3500
+#define PIC_BASE  0x6500
 
 // Interrupt request lines
 // Bit numbers (LSB == 0) that correpond to interrupts into PIC
@@ -773,7 +641,7 @@ typedef struct {
 ///////////////////////////////////////////////////
 // UART, Slave 10
 
-#define UART_BASE  0x3700
+#define UART_BASE  0x6700
 
 typedef struct {
   //  All elements are 8 bits except for clkdiv (16), but we use uint32 to make 
@@ -791,7 +659,7 @@ typedef struct {
 ///////////////////////////////////////////////////
 // ATR Controller, Slave 11
 
-#define ATR_BASE  0x3800
+#define ATR_BASE  0x6800
 
 typedef struct {
   volatile uint32_t	v[16];
@@ -810,7 +678,7 @@ typedef struct {
 ///////////////////////////////////////////////////
 // ICAP, Slave 13
 
-#define ICAP_BASE 0x3A00
+#define ICAP_BASE 0x6A00
 typedef struct {
   uint32_t icap; //only the lower 8 bits matter
 } icap_regs_t;
@@ -822,7 +690,7 @@ typedef struct {
 // Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc.
 // Peripheral mask not needed since bus is dedicated (CE held low)
 
-#define SPIF_BASE 0x3B00
+#define SPIF_BASE 0x6B00
 typedef struct {
   volatile uint32_t	txrx0;
   volatile uint32_t	txrx1;
diff --git a/firmware/microblaze/usrp2p/spi_flash.c b/firmware/zpu/usrp2p/spi_flash.c
index 09b74a513..09b74a513 100644
--- a/firmware/microblaze/usrp2p/spi_flash.c
+++ b/firmware/zpu/usrp2p/spi_flash.c
diff --git a/firmware/microblaze/usrp2p/spi_flash.h b/firmware/zpu/usrp2p/spi_flash.h
index bbe7b650d..bbe7b650d 100644
--- a/firmware/microblaze/usrp2p/spi_flash.h
+++ b/firmware/zpu/usrp2p/spi_flash.h
diff --git a/firmware/microblaze/usrp2p/spi_flash_private.h b/firmware/zpu/usrp2p/spi_flash_private.h
index 9a1b8d3e3..9a1b8d3e3 100644
--- a/firmware/microblaze/usrp2p/spi_flash_private.h
+++ b/firmware/zpu/usrp2p/spi_flash_private.h
diff --git a/firmware/microblaze/usrp2p/spi_flash_read.c b/firmware/zpu/usrp2p/spi_flash_read.c
index 4682c5fe6..36c326e96 100644
--- a/firmware/microblaze/usrp2p/spi_flash_read.c
+++ b/firmware/zpu/usrp2p/spi_flash_read.c
@@ -19,6 +19,7 @@
 
 #include "spi_flash_private.h"
 #include <stdlib.h>		// abort
+#include <nonstdio.h>
 
 static size_t _spi_flash_log2_memory_size;
 
@@ -100,7 +101,8 @@ spi_flash_read(uint32_t flash_addr,  size_t nbytes, void *buf)
    */
   unsigned char *dst = (unsigned char *) buf;
   size_t m;
-  for (size_t n = 0; n < nbytes; n += m, dst += m){
+  for (size_t n = 0; n < nbytes; n += m){
+        
     spif_regs->ctrl = FLAGS | LEN(16 * 8);	// xfer 16 bytes
     spif_regs->ctrl = FLAGS | LEN(16 * 8) | SPI_CTRL_GO_BSY;
     spif_wait();
@@ -113,7 +115,7 @@ spi_flash_read(uint32_t flash_addr,  size_t nbytes, void *buf)
     unsigned char *src = (unsigned char *) &w[0];
     m = min(nbytes - n, 16);
     for (size_t i = 0; i < m; i++)
-      dst[i] = src[i];
+      *(dst++) = src[i];
   }
   spif_regs->ss = 0;			// deassert chip select
 }
diff --git a/firmware/microblaze/usrp2p/spif.c b/firmware/zpu/usrp2p/spif.c
index 1c1a348f4..1c1a348f4 100644
--- a/firmware/microblaze/usrp2p/spif.c
+++ b/firmware/zpu/usrp2p/spif.c
diff --git a/firmware/microblaze/usrp2p/udp_fw_update.c b/firmware/zpu/usrp2p/udp_fw_update.c
index ead08ad2c..ead08ad2c 100644
--- a/firmware/microblaze/usrp2p/udp_fw_update.c
+++ b/firmware/zpu/usrp2p/udp_fw_update.c
diff --git a/firmware/microblaze/usrp2p/xilinx_s3_icap.c b/firmware/zpu/usrp2p/xilinx_s3_icap.c
index 50c85231c..50c85231c 100644
--- a/firmware/microblaze/usrp2p/xilinx_s3_icap.c
+++ b/firmware/zpu/usrp2p/xilinx_s3_icap.c
diff --git a/firmware/microblaze/usrp2p/xilinx_s3_icap.h b/firmware/zpu/usrp2p/xilinx_s3_icap.h
index 7b7e9eccc..7b7e9eccc 100644
--- a/firmware/microblaze/usrp2p/xilinx_s3_icap.h
+++ b/firmware/zpu/usrp2p/xilinx_s3_icap.h
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index c66979132..5552fbd51 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -8,6 +8,8 @@
 FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \
 buffer_int.v \
 buffer_pool.v \
+crossbar36.v \
+dsp_framer36.v \
 fifo_2clock.v \
 fifo_2clock_cascade.v \
 ll8_shortfifo.v \
@@ -22,4 +24,7 @@ fifo36_to_fifo19.v \
 fifo19_to_fifo36.v \
 fifo36_mux.v \
 fifo36_demux.v \
+packet_router.v \
+splitter36.v \
+valve36.v \
 ))
diff --git a/fpga/usrp2/fifo/crossbar36.v b/fpga/usrp2/fifo/crossbar36.v
new file mode 100644
index 000000000..d90f5659c
--- /dev/null
+++ b/fpga/usrp2/fifo/crossbar36.v
@@ -0,0 +1,40 @@
+
+
+module crossbar36
+  (input clk, input reset, input clear,
+   input cross,
+   input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+   input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+   output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+   output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+   reg 		 cross_int, active0, active1;
+
+   assign data0_o = cross_int ? data1_i : data0_i;
+   assign data1_o = cross_int ? data0_i : data1_i;
+
+   assign src0_rdy_o = cross_int ? src1_rdy_i : src0_rdy_i;
+   assign src1_rdy_o = cross_int ? src0_rdy_i : src1_rdy_i;
+
+   assign dst0_rdy_o = cross_int ? dst1_rdy_i : dst0_rdy_i;
+   assign dst1_rdy_o = cross_int ? dst0_rdy_i : dst1_rdy_i;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       active0 <= 0;
+     else if(src0_rdy_i & dst0_rdy_o)
+       active0 <= ~data0_i[33];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       active1 <= 0;
+     else if(src1_rdy_i & dst1_rdy_o)
+       active1 <= ~data1_i[33];
+
+   always @(posedge clk)
+     if(reset | clear)
+       cross_int <= 0;
+     else if(~active0 & ~active1)
+       cross_int <= cross;
+   
+endmodule // crossbar36
diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v
new file mode 100644
index 000000000..34a05d91e
--- /dev/null
+++ b/fpga/usrp2/fifo/dsp_framer36.v
@@ -0,0 +1,98 @@
+
+// Frame DSP packets with a header line to be handled by the protocol machine
+
+module dsp_framer36
+    #(parameter BUF_SIZE = 9)
+    (
+        input clk, input rst, input clr,
+        input [35:0] inp_data, input inp_valid, output inp_ready,
+        output [35:0] out_data, output out_valid, input out_ready
+    );
+
+    localparam DSP_FRM_STATE_WAIT_SOF = 0;
+    localparam DSP_FRM_STATE_WAIT_EOF = 1;
+    localparam DSP_FRM_STATE_WRITE_HDR = 2;
+    localparam DSP_FRM_STATE_WRITE = 3;
+
+    reg [1:0] dsp_frm_state;
+    reg [BUF_SIZE-1:0] dsp_frm_addr;
+    reg [BUF_SIZE-1:0] dsp_frm_count;
+    wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
+
+    //DSP input stream ready in the following states
+    assign inp_ready = (
+        dsp_frm_state == DSP_FRM_STATE_WAIT_SOF ||
+        dsp_frm_state == DSP_FRM_STATE_WAIT_EOF
+    )? 1'b1 : 1'b0;
+
+    //DSP framer output data mux (header or BRAM):
+    //The header is generated here from the count.
+    wire [31:0] dsp_frm_data_bram;
+    wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
+    assign out_data =
+        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
+        (dsp_frm_addr == dsp_frm_count)           ? {4'b0010, dsp_frm_data_bram}    : (
+    {4'b0000, dsp_frm_data_bram}));
+    assign out_valid = (
+        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) ||
+        (dsp_frm_state == DSP_FRM_STATE_WRITE)
+    )? 1'b1 : 1'b0;
+
+    RAMB16_S36_S36 dsp_frm_buff(
+        //port A = DSP input interface (writes to BRAM)
+        .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0),
+        .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid),
+        //port B = DSP framer interface (reads from BRAM)
+        .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
+        .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
+    );
+
+    always @(posedge clk)
+    if(rst | clr) begin
+        dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+        dsp_frm_addr <= 0;
+    end
+    else begin
+        case(dsp_frm_state)
+        DSP_FRM_STATE_WAIT_SOF: begin
+            if (inp_ready & inp_valid & inp_data[32]) begin
+                dsp_frm_addr <= dsp_frm_addr_next;
+                dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF;
+            end
+        end
+
+        DSP_FRM_STATE_WAIT_EOF: begin
+            if (inp_ready & inp_valid) begin
+                if (inp_data[33]) begin
+                    dsp_frm_count <= dsp_frm_addr_next;
+                    dsp_frm_addr <= 0;
+                    dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR;
+                end
+                else begin
+                    dsp_frm_addr <= dsp_frm_addr_next;
+                end
+            end
+        end
+
+        DSP_FRM_STATE_WRITE_HDR: begin
+            if (out_ready & out_valid) begin
+                dsp_frm_addr <= dsp_frm_addr_next;
+                dsp_frm_state <= DSP_FRM_STATE_WRITE;
+            end
+        end
+
+        DSP_FRM_STATE_WRITE: begin
+            if (out_ready & out_valid) begin
+                if (out_data[33]) begin
+                    dsp_frm_addr <= 0;
+                    dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+                end
+                else begin
+                    dsp_frm_addr <= dsp_frm_addr_next;
+                end
+            end
+        end
+        endcase //dsp_frm_state
+    end
+
+endmodule //dsp_framer36
diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v
new file mode 100644
index 000000000..ade83bb87
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_router.v
@@ -0,0 +1,676 @@
+module packet_router
+    #(
+        parameter BUF_SIZE = 9,
+        parameter UDP_BASE = 0,
+        parameter CTRL_BASE = 0
+    )
+    (
+        //wishbone interface for memory mapped CPU frames
+        input wb_clk_i,
+        input wb_rst_i,
+        input wb_we_i,
+        input wb_stb_i,
+        input [15:0] wb_adr_i,
+        input [31:0] wb_dat_i,
+        output [31:0] wb_dat_o,
+        output reg wb_ack_o,
+        output wb_err_o,
+        output wb_rty_o,
+
+        //setting register interface
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        input stream_clk,
+        input stream_rst,
+        input stream_clr,
+
+        //output status register
+        output [31:0] status,
+
+        output sys_int_o, //want an interrupt?
+
+        output [31:0] debug,
+
+        // Input Interfaces (in to router)
+        input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready,
+        input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready,
+        input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
+        input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready,
+
+        // Output Interfaces (out of router)
+        output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready,
+        output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+        output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready
+    );
+
+    assign wb_err_o = 1'b0;  // Unused for now
+    assign wb_rty_o = 1'b0;  // Unused for now
+    always @(posedge wb_clk_i)
+        wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+    //which buffer: 0 = CPU read buffer, 1 = CPU write buffer
+    wire which_buf = wb_adr_i[BUF_SIZE+2];
+
+    ////////////////////////////////////////////////////////////////////
+    // CPU interface to this packet router
+    ////////////////////////////////////////////////////////////////////
+    wire [35:0] cpu_inp_data,  cpu_out_data;
+    wire        cpu_inp_valid, cpu_out_valid;
+    wire        cpu_inp_ready, cpu_out_ready;
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication interfaces
+    ////////////////////////////////////////////////////////////////////
+    wire [35:0] com_inp_data,  com_out_data,  udp_out_data;
+    wire        com_inp_valid, com_out_valid, udp_out_valid;
+    wire        com_inp_ready, com_out_ready, udp_out_ready;
+
+    ////////////////////////////////////////////////////////////////////
+    // Control signals (setting registers and status signals)
+    //    - handshake lines for the CPU communication
+    //    - setting registers to program the inspector
+    ////////////////////////////////////////////////////////////////////
+
+    //setting register for mode control
+    wire [31:0] _sreg_mode_ctrl;
+    wire master_mode_flag = _sreg_mode_ctrl[0];
+    wire mode_changed;
+    setting_reg #(.my_addr(CTRL_BASE+0)) sreg_mode_ctrl(
+        .clk(stream_clk),.rst(stream_rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(_sreg_mode_ctrl),.changed(mode_changed)
+    );
+
+    //setting register to program the IP address
+    wire [31:0] my_ip_addr;
+    setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr(
+        .clk(stream_clk),.rst(stream_rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(my_ip_addr),.changed()
+    );
+
+    //setting register to program the UDP data ports
+    wire [15:0] dsp0_udp_port, dsp1_udp_port;
+    setting_reg #(.my_addr(CTRL_BASE+2)) sreg_data_ports(
+        .clk(stream_clk),.rst(stream_rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({dsp1_udp_port, dsp0_udp_port}),.changed()
+    );
+
+    //setting register for CPU output handshake
+    wire [31:0] _sreg_cpu_out_ctrl;
+    wire cpu_out_hs_ctrl = _sreg_cpu_out_ctrl[0];
+    setting_reg #(.my_addr(CTRL_BASE+3)) sreg_cpu_out_ctrl(
+        .clk(stream_clk),.rst(stream_rst | mode_changed),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(_sreg_cpu_out_ctrl),.changed()
+    );
+
+    //setting register for CPU input handshake
+    wire [31:0] _sreg_cpu_inp_ctrl;
+    wire cpu_inp_hs_ctrl = _sreg_cpu_inp_ctrl[0];
+    wire [BUF_SIZE-1:0] cpu_inp_line_count = _sreg_cpu_inp_ctrl[BUF_SIZE-1+16:0+16];
+    setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_inp_ctrl(
+        .clk(stream_clk),.rst(stream_rst | mode_changed),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(_sreg_cpu_inp_ctrl),.changed()
+    );
+
+    //assign status output signals
+    wire cpu_out_hs_stat;
+    assign status[0] = cpu_out_hs_stat;
+    wire [BUF_SIZE-1:0] cpu_out_line_count;
+    assign status[BUF_SIZE-1+16:0+16] = cpu_out_line_count;
+    wire cpu_inp_hs_stat;
+    assign status[1] = cpu_inp_hs_stat;
+    assign status[8] = master_mode_flag; //for the host to readback
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication input source crossbar
+    // When in master mode:
+    //   - serdes input -> comm output combiner
+    //   - ethernet input -> comm input inspector
+    // When in slave mode:
+    //   - serdes input -> comm input inspector
+    //   - ethernet input -> null sink
+    ////////////////////////////////////////////////////////////////////
+
+    //streaming signals from the crossbar to the combiner
+    wire [35:0] ext_inp_data;
+    wire        ext_inp_valid;
+    wire        ext_inp_ready;
+
+    //dummy signals for valve/xbar below
+    wire [35:0] _eth_inp_data;
+    wire        _eth_inp_valid;
+    wire        _eth_inp_ready;
+
+    valve36 eth_inp_valve (
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag),
+        .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready),
+        .data_o(_eth_inp_data), .src_rdy_o(_eth_inp_valid), .dst_rdy_i(_eth_inp_ready)
+    );
+
+    crossbar36 com_inp_xbar (
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
+        .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready),
+        .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready),
+        .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready),
+        .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication output sink crossbar
+    // When in master mode:
+    //   - comm output -> ethernet output
+    //   - insp output -> serdes output
+    // When in slave mode:
+    //   - com output -> serdes output
+    //   - insp output -> null sink
+    ////////////////////////////////////////////////////////////////////
+
+    //streaming signals from the inspector to the crossbar
+    wire [35:0] ext_out_data;
+    wire        ext_out_valid;
+    wire        ext_out_ready;
+
+    //dummy signals for valve/xbar below
+    wire [35:0] _eth_out_data;
+    wire        _eth_out_valid;
+    wire        _eth_out_ready;
+
+    crossbar36 com_out_xbar (
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
+        .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready),
+        .data1_i(ext_out_data), .src1_rdy_i(ext_out_valid), .dst1_rdy_o(ext_out_ready),
+        .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready),
+        .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready)
+    );
+
+    valve36 eth_out_valve (
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag),
+        .data_i(_eth_out_data), .src_rdy_i(_eth_out_valid), .dst_rdy_o(_eth_out_ready),
+        .data_o(eth_out_data), .src_rdy_o(eth_out_valid), .dst_rdy_i(eth_out_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication output source combiner (feeds UDP proto machine)
+    //   - DSP framer
+    //   - CPU input
+    //   - ERR input
+    ////////////////////////////////////////////////////////////////////
+
+    //streaming signals from the dsp framer to the combiner
+    wire [35:0] dsp_frm_data;
+    wire        dsp_frm_valid;
+    wire        dsp_frm_ready;
+
+    //dummy signals to join the the muxes below
+    wire [35:0] _combiner0_data, _combiner1_data;
+    wire        _combiner0_valid, _combiner1_valid;
+    wire        _combiner0_ready, _combiner1_ready;
+
+    fifo36_mux _com_output_combiner0(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready),
+        .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready),
+        .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
+    );
+
+    fifo36_mux _com_output_combiner1(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here
+        .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
+        .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
+    );
+
+    fifo36_mux com_output_source(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
+        .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
+        .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Interface CPU output to memory mapped wishbone
+    ////////////////////////////////////////////////////////////////////
+    localparam CPU_OUT_STATE_WAIT_SOF = 0;
+    localparam CPU_OUT_STATE_WAIT_EOF = 1;
+    localparam CPU_OUT_STATE_WAIT_CTRL_HI = 2;
+    localparam CPU_OUT_STATE_WAIT_CTRL_LO = 3;
+
+    reg [1:0] cpu_out_state;
+    reg [BUF_SIZE-1:0] cpu_out_addr;
+    assign cpu_out_line_count = cpu_out_addr;
+    wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1;
+
+    assign cpu_out_ready = (
+        cpu_out_state == CPU_OUT_STATE_WAIT_SOF ||
+        cpu_out_state == CPU_OUT_STATE_WAIT_EOF
+    )? 1'b1 : 1'b0;
+    assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
+
+    RAMB16_S36_S36 cpu_out_buff(
+        //port A = wishbone memory mapped address space (output only)
+        .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0),
+        .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i),
+        //port B = packet router interface to CPU (input only)
+        .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data[31:0]),.DIPB(4'h0),
+        .ENB(cpu_out_ready & cpu_out_valid),.SSRB(0),.WEB(cpu_out_ready & cpu_out_valid)
+    );
+
+    always @(posedge stream_clk)
+    if(stream_rst | stream_clr | mode_changed) begin
+        cpu_out_state <= CPU_OUT_STATE_WAIT_SOF;
+        cpu_out_addr <= 0;
+    end
+    else begin
+        case(cpu_out_state)
+        CPU_OUT_STATE_WAIT_SOF: begin
+            if (cpu_out_ready & cpu_out_valid & cpu_out_data[32]) begin
+                cpu_out_state <= CPU_OUT_STATE_WAIT_EOF;
+                cpu_out_addr <= cpu_out_addr_next;
+            end
+        end
+
+        CPU_OUT_STATE_WAIT_EOF: begin
+            if (cpu_out_ready & cpu_out_valid & cpu_out_data[33]) begin
+                cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI;
+            end
+            if (cpu_out_ready & cpu_out_valid) begin
+                cpu_out_addr <= cpu_out_addr_next;
+            end
+        end
+
+        CPU_OUT_STATE_WAIT_CTRL_HI: begin
+            if (cpu_out_hs_ctrl == 1'b1) begin
+                cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO;
+            end
+        end
+
+        CPU_OUT_STATE_WAIT_CTRL_LO: begin
+            if (cpu_out_hs_ctrl == 1'b0) begin
+                cpu_out_state <= CPU_OUT_STATE_WAIT_SOF;
+            end
+            cpu_out_addr <= 0; //reset the address counter
+        end
+
+        endcase //cpu_out_state
+    end
+
+    ////////////////////////////////////////////////////////////////////
+    // Interface CPU input to memory mapped wishbone
+    ////////////////////////////////////////////////////////////////////
+    localparam CPU_INP_STATE_WAIT_CTRL_HI = 0;
+    localparam CPU_INP_STATE_WAIT_CTRL_LO = 1;
+    localparam CPU_INP_STATE_UNLOAD = 2;
+
+    reg [1:0] cpu_inp_state;
+    reg [BUF_SIZE-1:0] cpu_inp_addr;
+    wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1;
+
+    reg [BUF_SIZE-1:0] cpu_inp_line_count_reg;
+
+    assign cpu_inp_data[35:32] =
+        (cpu_inp_addr == 1                     )? 4'b0001 : (
+        (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : (
+    4'b0000));
+
+    wire cpu_inp_enb = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? (cpu_inp_ready & cpu_inp_valid) : 1'b1;
+    assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0;
+    assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
+
+    RAMB16_S36_S36 cpu_inp_buff(
+        //port A = wishbone memory mapped address space (input only)
+        .DOA(),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+        .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i),
+        //port B = packet router interface from CPU (output only)
+        .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0),
+        .ENB(cpu_inp_enb),.SSRB(0),.WEB(1'b0)
+    );
+
+    always @(posedge stream_clk)
+    if(stream_rst | stream_clr | mode_changed) begin
+        cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI;
+        cpu_inp_addr <= 0;
+    end
+    else begin
+        case(cpu_inp_state)
+        CPU_INP_STATE_WAIT_CTRL_HI: begin
+            if (cpu_inp_hs_ctrl == 1'b1) begin
+                cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO;
+            end
+            cpu_inp_line_count_reg <= cpu_inp_line_count;
+        end
+
+        CPU_INP_STATE_WAIT_CTRL_LO: begin
+            if (cpu_inp_hs_ctrl == 1'b0) begin
+                cpu_inp_state <= CPU_INP_STATE_UNLOAD;
+                cpu_inp_addr <= cpu_inp_addr_next;
+            end
+        end
+
+        CPU_INP_STATE_UNLOAD: begin
+            if (cpu_inp_ready & cpu_inp_valid) begin
+                if (cpu_inp_data[33]) begin
+                    cpu_inp_addr <= 0;
+                    cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI;
+                end
+                else begin
+                    cpu_inp_addr <= cpu_inp_addr_next;
+                end
+            end
+        end
+
+        endcase //cpu_inp_state
+    end
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication input inspector
+    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
+    ////////////////////////////////////////////////////////////////////
+    localparam COM_INSP_STATE_READ_COM_PRE = 0;
+    localparam COM_INSP_STATE_READ_COM = 1;
+    localparam COM_INSP_STATE_WRITE_REGS = 2;
+    localparam COM_INSP_STATE_WRITE_LIVE = 3;
+
+    localparam COM_INSP_DEST_DSP = 0;
+    localparam COM_INSP_DEST_EXT = 1;
+    localparam COM_INSP_DEST_CPU = 2;
+    localparam COM_INSP_DEST_BOF = 3;
+
+    localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
+    localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at
+
+    //output inspector interfaces
+    wire [35:0] com_insp_out_dsp_data;
+    wire        com_insp_out_dsp_valid;
+    wire        com_insp_out_dsp_ready;
+
+    wire [35:0] com_insp_out_ext_data;
+    wire        com_insp_out_ext_valid;
+    wire        com_insp_out_ext_ready;
+
+    wire [35:0] com_insp_out_cpu_data;
+    wire        com_insp_out_cpu_valid;
+    wire        com_insp_out_cpu_ready;
+
+    wire [35:0] com_insp_out_bof_data;
+    wire        com_insp_out_bof_valid;
+    wire        com_insp_out_bof_ready;
+
+    //connect this fast-path signals directly to the DSP out
+    assign dsp_out_data = com_insp_out_dsp_data;
+    assign dsp_out_valid = com_insp_out_dsp_valid;
+    assign com_insp_out_dsp_ready = dsp_out_ready;
+
+    reg [1:0] com_insp_state;
+    reg [1:0] com_insp_dest;
+    reg [3:0] com_insp_dreg_count; //data registers to buffer headers
+    wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1;
+    wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0;
+    reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0];
+
+    //extract various packet components:
+    wire [47:0] com_insp_dregs_eth_dst_mac   = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]};
+    wire [15:0] com_insp_dregs_eth_type      = com_insp_dregs[3][15:0];
+    wire [7:0]  com_insp_dregs_ipv4_proto    = com_insp_dregs[6][23:16];
+    wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0];
+    wire [15:0] com_insp_dregs_udp_dst_port  = com_insp_dregs[9][15:0];
+    wire [15:0] com_insp_dregs_vrt_size      = com_inp_data[15:0];
+
+    //Inspector output flags special case:
+    //Inject SOF into flags at first DSP line.
+    wire [3:0] com_insp_out_flags = (
+        (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) &&
+        (com_insp_dest == COM_INSP_DEST_DSP)
+    )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32];
+
+    //The communication inspector ouput data and valid signals:
+    //Mux between com input and data registers based on the state.
+    wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)?
+        {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data
+    ;
+    wire com_insp_out_valid =
+        (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1          : (
+        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : (
+    1'b0));
+
+    //The communication inspector ouput ready signal:
+    //Mux between the various destination ready signals.
+    wire com_insp_out_ready =
+        (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : (
+        (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : (
+        (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : (
+        (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : (
+    1'b0))));
+
+    //Always connected output data lines.
+    assign com_insp_out_dsp_data = com_insp_out_data;
+    assign com_insp_out_ext_data = com_insp_out_data;
+    assign com_insp_out_cpu_data = com_insp_out_data;
+    assign com_insp_out_bof_data = com_insp_out_data;
+
+    //Destination output valid signals:
+    //Comes from inspector valid when destination is selected, and otherwise low.
+    assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0;
+
+    //The communication inspector ouput ready signal:
+    //Always ready when storing to data registers,
+    //comes from inspector ready output when live,
+    //and otherwise low.
+    assign com_inp_ready =
+        (com_insp_state == COM_INSP_STATE_READ_COM_PRE)  ? 1'b1               : (
+        (com_insp_state == COM_INSP_STATE_READ_COM)      ? 1'b1               : (
+        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)    ? com_insp_out_ready : (
+    1'b0)));
+
+    always @(posedge stream_clk)
+    if(stream_rst | stream_clr) begin
+        com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+        com_insp_dreg_count <= 0;
+    end
+    else begin
+        case(com_insp_state)
+        COM_INSP_STATE_READ_COM_PRE: begin
+            if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
+                com_insp_state <= COM_INSP_STATE_READ_COM;
+                com_insp_dreg_count <= com_insp_dreg_count_next;
+                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
+            end
+        end
+
+        COM_INSP_STATE_READ_COM: begin
+            if (com_inp_ready & com_inp_valid) begin
+                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
+                if (com_insp_dreg_counter_done | com_inp_data[33]) begin
+                    com_insp_state <= COM_INSP_STATE_WRITE_REGS;
+                    com_insp_dreg_count <= 0;
+
+                    //---------- begin inspection decision -----------//
+                    //EOF or bcast or not IPv4 or not UDP:
+                    if (
+                        com_inp_data[33] || (com_insp_dregs_eth_dst_mac == 48'hffffffffffff) ||
+                        (com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)
+                    ) begin
+                        com_insp_dest <= COM_INSP_DEST_BOF;
+                    end
+
+                    //not my IP address:
+                    else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin
+                        com_insp_dest <= COM_INSP_DEST_EXT;
+                    end
+
+                    //UDP data port and VRT:
+                    else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
+                        com_insp_dest <= COM_INSP_DEST_DSP;
+                        com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
+                    end
+
+                    //other:
+                    else begin
+                        com_insp_dest <= COM_INSP_DEST_CPU;
+                    end
+                    //---------- end inspection decision -------------//
+
+                end
+                else begin
+                    com_insp_dreg_count <= com_insp_dreg_count_next;
+                end
+            end
+        end
+
+        COM_INSP_STATE_WRITE_REGS: begin
+            if (com_insp_out_ready & com_insp_out_valid) begin
+                if (com_insp_out_data[33]) begin
+                    com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+                    com_insp_dreg_count <= 0;
+                end
+                else if (com_insp_dreg_counter_done) begin
+                    com_insp_state <= COM_INSP_STATE_WRITE_LIVE;
+                    com_insp_dreg_count <= 0;
+                end
+                else begin
+                    com_insp_dreg_count <= com_insp_dreg_count_next;
+                end
+            end
+        end
+
+        COM_INSP_STATE_WRITE_LIVE: begin
+            if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin
+                com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+            end
+        end
+
+        endcase //com_insp_state
+    end
+
+    ////////////////////////////////////////////////////////////////////
+    // Splitter and output muxes for the bof packets
+    //   - split the bof packets into two streams
+    //   - mux split packets into cpu out and ext out
+    ////////////////////////////////////////////////////////////////////
+
+    //dummy signals to join the the splitter and muxes below
+    wire [35:0] _split_to_ext_data,  _split_to_cpu_data,  _cpu_out_data;
+    wire        _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid;
+    wire        _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready;
+
+    splitter36 bof_out_splitter(
+        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+        .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready),
+        .out0_data(_split_to_ext_data),   .out0_valid(_split_to_ext_valid),   .out0_ready(_split_to_ext_ready),
+        .out1_data(_split_to_cpu_data),   .out1_valid(_split_to_cpu_valid),   .out1_ready(_split_to_cpu_ready)
+    );
+
+    fifo36_mux ext_out_mux(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready),
+        .data1_i(_split_to_ext_data),    .src1_rdy_i(_split_to_ext_valid),    .dst1_rdy_o(_split_to_ext_ready),
+        .data_o(ext_out_data),           .src_rdy_o(ext_out_valid),           .dst_rdy_i(ext_out_ready)
+    );
+
+    fifo36_mux cpu_out_mux(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready),
+        .data1_i(_split_to_cpu_data),    .src1_rdy_i(_split_to_cpu_valid),    .dst1_rdy_o(_split_to_cpu_ready),
+        .data_o(_cpu_out_data),          .src_rdy_o(_cpu_out_valid),          .dst_rdy_i(_cpu_out_ready)
+    );
+
+    fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo (
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .datain(_cpu_out_data), .src_rdy_i(_cpu_out_valid), .dst_rdy_o(_cpu_out_ready),
+        .dataout(cpu_out_data), .src_rdy_o(cpu_out_valid),  .dst_rdy_i(cpu_out_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // DSP input framer
+    ////////////////////////////////////////////////////////////////////
+
+    dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36(
+        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+        .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready),
+        .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // UDP TX Protocol machine
+    ////////////////////////////////////////////////////////////////////
+
+    //dummy signals to connect the components below
+    wire [18:0] _udp_r2s_data, _udp_s2p_data, _udp_p2s_data, _udp_s2r_data;
+    wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid;
+    wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready;
+
+    wire [35:0] _com_out_data;
+    wire _com_out_valid, _com_out_ready;
+
+    fifo36_to_fifo19 udp_fifo36_to_fifo19
+     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+      .f36_datain(udp_out_data),   .f36_src_rdy_i(udp_out_valid),  .f36_dst_rdy_o(udp_out_ready),
+      .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) );
+
+    fifo_short #(.WIDTH(19)) udp_shortfifo19_inp
+     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+      .datain(_udp_r2s_data),  .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready),
+      .dataout(_udp_s2p_data), .src_rdy_o(_udp_s2p_valid), .dst_rdy_i(_udp_s2p_ready),
+      .space(), .occupied() );
+
+    prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx
+     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(_udp_s2p_data),  .src_rdy_i(_udp_s2p_valid), .dst_rdy_o(_udp_s2p_ready),
+      .dataout(_udp_p2s_data), .src_rdy_o(_udp_p2s_valid), .dst_rdy_i(_udp_p2s_ready) );
+
+    fifo_short #(.WIDTH(19)) udp_shortfifo19_out
+     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+      .datain(_udp_p2s_data),  .src_rdy_i(_udp_p2s_valid), .dst_rdy_o(_udp_p2s_ready),
+      .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready),
+      .space(), .occupied() );
+
+    fifo19_to_fifo36 udp_fifo19_to_fifo36
+     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+      .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready),
+      .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid),  .f36_dst_rdy_i(_com_out_ready) );
+
+    fifo36_mux com_out_mux(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(ext_inp_data),  .src0_rdy_i(ext_inp_valid),  .dst0_rdy_o(ext_inp_ready),
+        .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready),
+        .data_o(com_out_data),   .src_rdy_o(com_out_valid),   .dst_rdy_i(com_out_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Assign debugs
+    ////////////////////////////////////////////////////////////////////
+
+    assign debug = {
+        //inputs to the router (8)
+        dsp_inp_ready, dsp_inp_valid,
+        ser_inp_ready, ser_inp_valid,
+        eth_inp_ready, eth_inp_valid,
+        cpu_inp_ready, cpu_inp_valid,
+
+        //outputs from the router (8)
+        dsp_out_ready, dsp_out_valid,
+        ser_out_ready, ser_out_valid,
+        eth_out_ready, eth_out_valid,
+        cpu_out_ready, cpu_out_valid,
+
+        //inspector interfaces (8)
+        com_insp_out_dsp_ready, com_insp_out_dsp_valid,
+        com_insp_out_ext_ready, com_insp_out_ext_valid,
+        com_insp_out_cpu_ready, com_insp_out_cpu_valid,
+        com_insp_out_bof_ready, com_insp_out_bof_valid,
+
+        //other interfaces (8)
+        ext_inp_ready, ext_inp_valid,
+        com_out_ready, com_out_valid,
+        ext_out_ready, ext_out_valid,
+        com_inp_ready, com_inp_valid
+    };
+
+endmodule // packet_router
diff --git a/fpga/usrp2/fifo/splitter36.v b/fpga/usrp2/fifo/splitter36.v
new file mode 100644
index 000000000..ed998b4f5
--- /dev/null
+++ b/fpga/usrp2/fifo/splitter36.v
@@ -0,0 +1,68 @@
+
+// Split packets from a fifo based interface so it goes out identically on two interfaces
+
+module splitter36
+    (
+        input clk, input rst, input clr,
+        input [35:0] inp_data, input inp_valid, output inp_ready,
+        output [35:0] out0_data, output out0_valid, input out0_ready,
+        output [35:0] out1_data, output out1_valid, input out1_ready
+    );
+
+    localparam STATE_COPY_BOTH = 0;
+    localparam STATE_COPY_ZERO = 1;
+    localparam STATE_COPY_ONE = 2;
+
+    reg [1:0] state;
+    reg [35:0] data_reg;
+
+    assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+    assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+
+    assign out0_valid =
+        (state == STATE_COPY_BOTH)? inp_valid : (
+        (state == STATE_COPY_ZERO)? 1'b1      : (
+    1'b0));
+
+    assign out1_valid =
+        (state == STATE_COPY_BOTH)? inp_valid : (
+        (state == STATE_COPY_ONE)?  1'b1      : (
+    1'b0));
+
+    assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0;
+
+    always @(posedge clk)
+    if (rst | clr) begin
+        state <= STATE_COPY_BOTH;
+    end
+    else begin
+        case (state)
+
+        STATE_COPY_BOTH: begin
+            if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin
+                state <= STATE_COPY_ONE;
+            end
+            else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin
+                state <= STATE_COPY_ZERO;
+            end
+            data_reg <= inp_data;
+        end
+
+        STATE_COPY_ZERO: begin
+            if (out0_valid & out0_ready) begin
+                state <= STATE_COPY_BOTH;
+            end
+        end
+
+        STATE_COPY_ONE: begin
+            if (out1_valid & out1_ready) begin
+                state <= STATE_COPY_BOTH;
+            end
+        end
+
+        endcase //state
+    end
+
+
+
+endmodule //splitter36
diff --git a/fpga/usrp2/fifo/valve36.v b/fpga/usrp2/fifo/valve36.v
new file mode 100644
index 000000000..b4b23e5a6
--- /dev/null
+++ b/fpga/usrp2/fifo/valve36.v
@@ -0,0 +1,28 @@
+
+
+module valve36
+  (input clk, input reset, input clear,
+   input shutoff,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+   
+   reg 		 shutoff_int, active;
+   
+   assign data_o = data_i;
+
+   assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i;
+   assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       active <= 0;
+     else if(src_rdy_i & dst_rdy_o)
+       active <= ~data_i[33];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       shutoff_int <= 0;
+     else if(~active)
+       shutoff_int <= shutoff;
+   
+endmodule // valve36
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs
index 284578b39..838b1b813 100644
--- a/fpga/usrp2/opencores/Makefile.srcs
+++ b/fpga/usrp2/opencores/Makefile.srcs
@@ -25,4 +25,12 @@ spi/rtl/verilog/spi_defines.v \
 spi/rtl/verilog/spi_shift.v \
 spi/rtl/verilog/spi_top.v \
 spi/rtl/verilog/spi_top16.v \
+zpu/zpu_top_pkg.vhd \
+zpu/zpu_wb_top.vhd \
+zpu/wishbone/wishbone_pkg.vhd \
+zpu/wishbone/zpu_system.vhd \
+zpu/wishbone/zpu_wb_bridge.vhd \
+zpu/core/zpu_config.vhd \
+zpu/core/zpu_core.vhd \
+zpu/core/zpupkg.vhd \
 ))
diff --git a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd
new file mode 100644
index 000000000..b7e894232
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd
@@ -0,0 +1,15 @@
+library ieee;

+use ieee.std_logic_1164.all;

+use ieee.std_logic_unsigned.all;

+

+package zpu_config is

+	-- generate trace output or not.

+	constant	Generate_Trace		: boolean := false;

+	constant 	wordPower			: integer := 5;

+	-- during simulation, set this to '0' to get matching trace.txt 

+	constant	DontCareValue		: std_logic := '0';

+	-- Clock frequency in MHz.

+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"40";

+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)

+	constant 	maxAddrBitIncIO		: integer := 15;

+end zpu_config;

diff --git a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd
new file mode 100644
index 000000000..24586b2f6
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd
@@ -0,0 +1,949 @@
+
+-- Company: ZPU4 generic memory interface CPU
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+
+
+
+entity zpu_core is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  mem_req : out std_logic;
+	 		  mem_we : out std_logic;
+	 		  mem_ack : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+			  stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic;
+	 		  zpu_status : out std_logic_vector(63 downto 0));
+end zpu_core;
+
+architecture behave of zpu_core is
+
+type InsnType is 
+(
+State_AddTop,
+State_Dup,
+State_DupStackB,
+State_Pop,
+State_Popdown,
+State_Add,
+State_Or,
+State_And,
+State_Store,
+State_AddSP,
+State_Shift,
+State_Nop,
+State_Im,
+State_LoadSP,
+State_StoreSP,
+State_Emulate,
+State_Load,
+State_PushPC,
+State_PushSP,
+State_PopPC,
+State_PopPCRel,
+State_Not,
+State_Flip,
+State_PopSP,
+State_Neqbranch,
+State_Eq,
+State_Loadb,
+State_Mult,
+State_Lessthan,
+State_Lessthanorequal,
+State_Ulessthanorequal,
+State_Ulessthan,
+State_Pushspadd,
+State_Call,
+State_Callpcrel,
+State_Sub,
+State_Break,
+State_Storeb,
+State_Interrupt,
+State_InsnFetch
+);
+
+type StateType is 
+(
+State_Idle, -- using first state first on the list out of paranoia 
+State_Load2,
+State_Popped,
+State_LoadSP2,
+State_LoadSP3,
+State_AddSP2,
+State_Fetch,
+State_Execute,
+State_Decode,
+State_Decode2,
+State_Resync,
+
+State_StoreSP2,
+State_Resync2,
+State_Resync3,
+State_Loadb2,
+State_Storeb2,
+State_Mult2,
+State_Mult3,
+State_Mult5,
+State_Mult6,
+State_Mult4,
+State_BinaryOpResult
+); 
+
+
+signal	pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incIncSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	decSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal  stackA   		: std_logic_vector(wordSize-1 downto 0);
+signal  binaryOpResult		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult2  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult3  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult  		: std_logic_vector(wordSize-1 downto 0);
+signal  multA 		: std_logic_vector(wordSize-1 downto 0);
+signal  multB  		: std_logic_vector(wordSize-1 downto 0);
+signal  stackB  		: std_logic_vector(wordSize-1 downto 0);
+signal	idim_flag			: std_logic;
+signal	busy 				: std_logic;
+signal mem_readEnable : std_logic;
+signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayReadEnable : std_logic;
+signal mem_busy : std_logic;
+signal decodeWord : std_logic_vector(wordSize-1 downto 0);
+
+
+signal state : StateType;
+signal insn : InsnType;
+type InsnArray is array(0 to wordBytes-1) of InsnType;
+signal decodedOpcode : InsnArray;
+
+type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+
+signal opcode : OpcodeArray;
+
+
+
+
+signal	begin_inst			: std_logic;
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+signal	out_mem_req : std_logic;
+
+signal inInterrupt : std_logic;
+
+-- state machine.
+
+begin
+
+	zpu_status(maxAddrBitIncIO downto 0) <= trace_pc;
+	zpu_status(31) <= '1';
+	zpu_status(39 downto 32) <= trace_opcode;
+	zpu_status(40) <= '1' when (state = State_Idle) else '0';
+	zpu_status(62) <= '1';
+
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy,
+		intsp => (others => 'U')
+        );
+	end generate;
+
+	
+	-- the memory subsystem will tell us one cycle later whether or 
+	-- not it is busy
+	out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+	out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
+	mem_req <= out_mem_req;
+	
+	incSp <= sp + 1;
+	incIncSp <= sp + 2;
+	decSp <= sp - 1;
+	
+	mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy
+
+	opcodeControl:
+	process(clk, areset)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+		variable spOffset : std_logic_vector(4 downto 0);
+		variable tSpOffset : std_logic_vector(4 downto 0);
+		variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
+		variable tNextState : InsnType;
+		variable tDecodedOpcode : InsnArray;
+		variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
+	begin
+		if areset = '1' then
+			state <= State_Idle;
+			break <= '0';
+			sp <= stack_start(maxAddrBitIncIO downto minAddrBit);
+			 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			mem_we <= '0';
+			multA <= (others => '0');
+			multB <= (others => '0');
+			mem_writeMask <= (others => '1');
+			out_mem_req <= '0';
+			mem_addr <= (others => DontCareValue);
+			mem_write <= (others => DontCareValue);
+			inInterrupt <= '0';
+		elsif (clk'event and clk = '1') then
+			-- we must multiply unconditionally to get pipelined multiplication
+        	tMultResult := multA * multB;
+    		multResult3 <= multResult2;
+    		multResult2 <= multResult;
+    		multResult <= tMultResult(wordSize-1 downto 0);
+    		
+			
+			spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
+			spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
+			nextPC := pc + 1;
+
+			-- prepare trace snapshot
+			trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
+			trace_pc <= pc;
+			trace_sp <=	sp;
+			trace_topOfStack <= stackA;
+			trace_topOfStackB <= stackB;
+			begin_inst <= '0';
+
+			-- we terminate the requeset as soon as we get acknowledge
+			if mem_ack = '1' then
+				out_mem_req <= '0';
+				mem_we <= '0';
+			end if;
+			
+			if interrupt='0' then
+				inInterrupt <= '0'; -- no longer in an interrupt
+			end if;
+
+			case state is
+				when State_Idle =>
+					if enable='1' then
+						state <= State_Resync; 
+					end if;
+				-- Initial state of ZPU, fetch top of stack + first instruction 
+				when State_Resync =>
+					if mem_busy='0' then
+						mem_addr <= sp;
+						out_mem_req <= '1';
+						state <= State_Resync2;
+					end if;
+				when State_Resync2 =>
+					if mem_busy='0' then
+						stackA <= mem_read;
+						mem_addr <= incSp;
+						out_mem_req <= '1';
+						state <= State_Resync3;
+					end if;
+				when State_Resync3 =>
+					if mem_busy='0' then
+						stackB <= mem_read;
+						mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+						out_mem_req <= '1';
+						state <= State_Decode;
+					end if;
+				when State_Decode =>
+					if mem_busy='0' then
+						decodeWord <= mem_read;
+						state <= State_Decode2;
+					end if;
+				when State_Decode2 =>
+					-- decode 4 instructions in parallel
+					for i in 0 to wordBytes-1 loop
+						tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+						tSpOffset(4):=not tOpcode(4);
+						tSpOffset(3 downto 0):=tOpcode(3 downto 0);
+
+						opcode(i) <= tOpcode;
+						if (tOpcode(7 downto 7)=OpCode_Im) then
+							tNextState:=State_Im;
+						elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Pop;
+							elsif tSpOffset=1 then
+								tNextState := State_PopDown;
+							else
+								tNextState :=State_StoreSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+							if tSpOffset = 0 then
+								tNextState :=State_Dup;
+							elsif tSpOffset = 1 then
+								tNextState :=State_DupStackB;
+							else
+								tNextState :=State_LoadSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+							tNextState :=State_Emulate;
+							if tOpcode(5 downto 0)=OpCode_Neqbranch then
+								tNextState :=State_Neqbranch;
+							elsif tOpcode(5 downto 0)=OpCode_Eq then
+								tNextState :=State_Eq;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthan then
+								tNextState :=State_Lessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
+								--tNextState :=State_Lessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
+								tNextState :=State_Ulessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
+								--tNextState :=State_Ulessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Loadb then
+								tNextState :=State_Loadb;
+							elsif tOpcode(5 downto 0)=OpCode_Mult then
+								tNextState :=State_Mult;
+							elsif tOpcode(5 downto 0)=OpCode_Storeb then
+								tNextState :=State_Storeb;
+							elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
+								tNextState :=State_Pushspadd;
+							elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
+								tNextState :=State_Callpcrel;
+							elsif tOpcode(5 downto 0)=OpCode_Call then
+								--tNextState :=State_Call;
+							elsif tOpcode(5 downto 0)=OpCode_Sub then
+								tNextState :=State_Sub;
+							elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
+								--tNextState :=State_PopPCRel;
+							end if;								
+						elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Shift;
+							elsif tSpOffset = 1 then
+								tNextState := State_AddTop;
+							else
+								tNextState :=State_AddSP;
+							end if;
+						else
+							case tOpcode(3 downto 0) is
+								when OpCode_Nop =>
+									tNextState :=State_Nop;
+								when OpCode_PushSP =>
+									tNextState :=State_PushSP;
+								when OpCode_PopPC =>
+									tNextState :=State_PopPC;
+								when OpCode_Add =>
+									tNextState :=State_Add;
+								when OpCode_Or =>
+									tNextState :=State_Or;
+								when OpCode_And =>
+									tNextState :=State_And;
+								when OpCode_Load =>
+									tNextState :=State_Load;
+								when OpCode_Not =>
+									tNextState :=State_Not;
+								when OpCode_Flip =>
+									tNextState :=State_Flip;
+								when OpCode_Store =>
+									tNextState :=State_Store;
+								when OpCode_PopSP =>
+									tNextState :=State_PopSP;
+								when others =>
+									tNextState := State_Break;
+
+							end case;
+						end if;
+						tDecodedOpcode(i) := tNextState;
+						
+					end loop;
+					
+					insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
+					
+					-- once we wrap, we need to fetch
+					tDecodedOpcode(0) := State_InsnFetch;
+
+					decodedOpcode <= tDecodedOpcode;
+					state <= State_Execute;
+						
+
+
+					-- Each instruction must:
+					--
+					-- 1. set idim_flag
+					-- 2. increase pc if applicable
+					-- 3. set next state if appliable
+					-- 4. do it's operation
+					 
+				when State_Execute =>
+					insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
+									
+					case insn is
+						when State_InsnFetch =>
+							state <= State_Fetch;
+						when State_Im =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '1';
+								pc <= pc + 1;
+								
+								if idim_flag='1' then 
+									stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								else
+									out_mem_req <= '1';
+									mem_we <= '1';
+									mem_addr <= incSp;
+									mem_write <= stackB;
+									stackB <= stackA;
+									sp <= decSp;
+									for i in wordSize-1 downto 7 loop
+										stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
+									end loop;
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								end if;
+							else	
+								insn <= insn;
+							end if;
+						when State_StoreSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_StoreSP2;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= sp+spOffset;
+								mem_write <= stackA;
+								stackA <= stackB;
+								sp <= incSp;
+							else	
+								insn <= insn;
+							end if;
+
+					
+						when State_LoadSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_LoadSP2;
+		
+								sp <= decSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							else	
+								insn <= insn;
+							end if;
+						when State_Emulate =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								sp <= decSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								stackB <= stackA;
+								
+								-- The emulate address is:
+								--        98 7654 3210
+								-- 0000 00aa aaa0 0000
+								pc <= (others => '0');
+								pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_Callpcrel =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								
+								pc <= pc + stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_Call =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							else	
+								insn <= insn;
+							end if;
+						when State_AddSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_AddSP2;
+								
+								out_mem_req <= '1';
+								mem_addr <= sp+spOffset;
+							else	
+								insn <= insn;
+							end if;
+						when State_PushSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								sp <= decSp;
+								stackA <= (others => '0');
+								stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+								stackB <= stackA;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopPC =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								sp <= incSp;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopPCRel =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+								sp <= incSp;
+								
+								out_mem_req <= '1';
+								mem_we <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_Add =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA + stackB;
+								
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_Sub =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							binaryOpResult <= stackB - stackA;
+							state <= State_BinaryOpResult;
+						when State_Pop =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								out_mem_req <= '1';
+								sp <= incSp;
+								stackA <= stackB;
+								state <= State_Popped;						
+							else	
+								insn <= insn;
+							end if;
+						when State_PopDown =>
+							if mem_busy='0' then
+								-- PopDown leaves top of stack unchanged
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								out_mem_req <= '1';
+								sp <= incSp;
+								state <= State_Popped;						
+							else	
+								insn <= insn;
+							end if;
+						when State_Or =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA or stackB;
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_And =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+								stackA <= stackA and stackB;
+								out_mem_req <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							else	
+								insn <= insn;
+							end if;
+						when State_Eq =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA=stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Ulessthan =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA<stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Ulessthanorequal =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (stackA<=stackB) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Lessthan =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (signed(stackA)<signed(stackB)) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+		                when State_Lessthanorequal =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+	
+		            		binaryOpResult <= (others => '0');
+		                	if (signed(stackA)<=signed(stackB)) then
+		                		binaryOpResult(0) <= '1';
+		                	end if;
+							state <= State_BinaryOpResult;
+						when State_Load =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Load2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+
+						when State_Dup =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_DupStackB =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackA <= stackB;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_Store =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_write <= stackB;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								sp <= incIncSp;
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_PopSP =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								out_mem_req <= '1';
+								mem_we <= '1';
+								sp <= stackA(maxAddrBitIncIO downto minAddrBit);
+								state <= State_Resync;
+							else	
+								insn <= insn;
+							end if;
+						when State_Nop =>	
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1;
+						when State_Not =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= not stackA;
+						when State_Flip =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							for i in 0 to wordSize-1 loop
+								stackA(i) <= stackA(wordSize-1-i);
+				  			end loop;
+						when State_AddTop =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= stackA + stackB;
+						when State_Shift =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+							stackA(0) <= '0';
+						when State_Pushspadd =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= (others => '0');
+							stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+						when State_Neqbranch =>
+							-- branches are almost always taken as they form loops
+							begin_inst <= '1';
+							idim_flag <= '0';
+							sp <= incIncSp;
+		                	if (stackB/=0) then
+		                		pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+		                	else
+		                		pc <= pc + 1;
+		                	end if;		
+		                	-- need to fetch stack again.				
+							state <= State_Resync;
+		                when State_Mult =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+		
+							multA <= stackA;
+							multB <= stackB;
+							state <= State_Mult2;
+						when State_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+
+						when State_Loadb =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Loadb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+						when State_Storeb =>
+							if mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Storeb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								out_mem_req <= '1';
+							else	
+								insn <= insn;
+							end if;
+				
+						when others =>
+--							sp <= (others => DontCareValue);
+							report "Illegal instruction" severity failure;
+							break <= '1';
+					end case;
+
+
+				when State_StoreSP2 =>
+					if mem_busy='0' then
+						mem_addr <= incSp;
+						out_mem_req <= '1';
+						state <= State_Popped;
+					end if;
+				when State_LoadSP2 =>
+					if mem_busy='0' then
+						state <= State_LoadSP3;
+						out_mem_req <= '1';
+						mem_addr <= sp+spOffset+1;
+					end if;
+				when State_LoadSP3 =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackB <= stackA;
+						stackA <= mem_read;
+					end if;
+				when State_AddSP2 =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackA <= stackA + mem_read;
+					end if;
+				when State_Load2 =>
+					if mem_busy='0' then
+						stackA <= mem_read;
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Loadb2 =>
+					if mem_busy='0' then
+						stackA <= (others => '0');
+						stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Storeb2 =>
+					if mem_busy='0' then
+						mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+						mem_write <= mem_read;
+						mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
+						out_mem_req <= '1';
+						mem_we <= '1';
+						pc <= pc + 1;
+						sp <= incIncSp;
+						state <= State_Resync;
+					end if;
+				when State_Fetch =>
+					if mem_busy='0' then
+						if interrupt='1' and inInterrupt='0' and idim_flag='0' then
+							-- We got an interrupt
+							inInterrupt <= '1';
+							
+							sp <= decSp;
+							out_mem_req <= '1';
+							mem_we <= '1';
+							mem_addr <= incSp;
+							mem_write <= stackB;
+							stackA <= (others => DontCareValue);
+							stackA(maxAddrBitIncIO downto 0) <= pc;
+							stackB <= stackA;
+							
+							pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address
+							
+			  				report "ZPU jumped to interrupt!" severity note;
+						else
+							mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+							out_mem_req <= '1';
+							state <= State_Decode;
+						end if;
+					end if;
+                when State_Mult2 =>
+					state <= State_Mult3;
+                when State_Mult3 =>
+					state <= State_Mult4;
+                when State_Mult4 =>
+					state <= State_Mult5;
+                when State_Mult5 =>
+            		stackA <= multResult3;
+                	state <= State_Mult6;
+                when State_Mult6 =>
+					if mem_busy='0' then
+						out_mem_req <= '1';
+						mem_addr <= incIncSp;
+						sp <= incSp;
+						state <= State_Popped;
+					end if;
+				when State_BinaryOpResult =>
+					if mem_busy='0' then
+						-- NB!!!! we know that the memory isn't busy at this point!!!!
+						out_mem_req <= '1';
+						mem_addr <= incIncSp;
+						sp <= incSp;
+						stackA <= binaryOpResult;
+						state <= State_Popped;
+					end if;
+				when State_Popped =>
+					if mem_busy='0' then
+						pc <= pc + 1;
+						stackB <= mem_read;
+						state <= State_Execute;
+					end if;
+				when others =>	
+--					sp <= (others => DontCareValue);
+					report "Illegal state" severity failure;
+					break <= '1';
+			end case;
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd
new file mode 100644
index 000000000..eee967a09
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd
@@ -0,0 +1,169 @@
+library IEEE;

+use IEEE.STD_LOGIC_1164.all;

+use IEEE.STD_LOGIC_ARITH.all;

+

+library work;

+use work.zpu_config.all;

+

+package zpupkg is

+

+	-- This bit is set for read/writes to IO

+	-- FIX!!! eventually this should be set to wordSize-1 so as to

+	-- to make the address of IO independent of amount of memory

+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime

+	-- libraries.

+	

+	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes

+	constant maxAddrBit			: integer := maxAddrBitIncIO-1;

+	constant ioBit				: integer := maxAddrBit+1;

+	constant wordSize			: integer := 2**wordPower;

+	constant wordBytes			: integer := wordSize/8;

+	constant minAddrBit			: integer := byteBits;

+	-- configurable internal stack size. Probably going to be 16 after toolchain is done

+	constant	stack_bits		: integer := 5; 

+	constant	stack_size		: integer := 2**stack_bits; 

+

+	component dualport_ram is

+	port (clk : in std_logic;

+		memAWriteEnable : in std_logic;

+		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);

+		memAWrite : in std_logic_vector(wordSize-1 downto 0);

+		memARead : out std_logic_vector(wordSize-1 downto 0);

+		memBWriteEnable : in std_logic;

+		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);

+		memBWrite : in std_logic_vector(wordSize-1 downto 0);

+		memBRead : out std_logic_vector(wordSize-1 downto 0));

+	end component;

+

+	component dram is

+		port (clk : in std_logic;

+			areset : in std_logic;

+			mem_writeEnable : in std_logic;

+			mem_readEnable : in std_logic;

+			mem_addr : in std_logic_vector(maxAddrBit downto 0);

+			mem_write : in std_logic_vector(wordSize-1 downto 0);

+			mem_read : out std_logic_vector(wordSize-1 downto 0);

+			mem_busy : out std_logic;

+			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));

+	end component;

+

+

+	component trace is

+	  port(

+	       	clk         : in std_logic;

+	       	begin_inst  : in std_logic;

+	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);

+			opcode		: in std_logic_vector(7 downto 0);

+			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);

+			memA		: in std_logic_vector(wordSize-1 downto 0);

+			memB		: in std_logic_vector(wordSize-1 downto 0);

+			busy         : in std_logic;

+			intSp		: in std_logic_vector(stack_bits-1 downto 0)

+			);

+	end component;

+

+	component zpu_core is

+    port ( clk : in std_logic;

+	 		  areset : in std_logic;

+	 		  enable : in std_logic; 

+	 		  mem_req : out std_logic;

+	 		  mem_we : out std_logic;

+	 		  mem_ack : in std_logic; 

+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);

+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);

+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);

+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);

+			  stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);

+	 		  interrupt : in std_logic;

+	 		  break : out std_logic;

+	 		  zpu_status : out std_logic_vector(63 downto 0));

+	end component;

+

+

+	

+	component timer is

+  	port(

+       	clk             : in std_logic;

+		areset			: in std_logic;

+		sample			: in std_logic;

+		reset			: in std_logic;

+		counter			: out std_logic_vector(63 downto 0));

+	end component;

+

+	component  zpuio is

+		port (	areset			: in std_logic;

+				cpu_clk			: in std_logic;

+				clk_status		: in std_logic_vector(2 downto 0);

+				cpu_din			: in std_logic_vector(15 downto 0);

+				cpu_a			: in std_logic_vector(20 downto 0);

+				cpu_we			: in std_logic_vector(1 downto 0);

+				cpu_re			: in std_logic;

+				cpu_dout		: inout std_logic_vector(15 downto 0));

+	end component;

+

+

+

+	

+	-- opcode decode constants

+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";

+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";

+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";

+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";

+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";

+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";

+	

+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";

+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";

+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";

+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";

+	

+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";

+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";

+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";

+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";

+	

+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";

+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";

+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";

+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";

+	

+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";

+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";

+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";

+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";

+	

+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);

+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);

+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);

+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);

+

+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);

+	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);

+	

+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);

+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);

+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);

+	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);

+

+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);

+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);

+

+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);

+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);

+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);

+

+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);

+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);

+	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);

+

+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);

+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);

+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);

+	

+

+

+	constant OpCode_Size		: integer := 8;

+

+

+		

+end zpupkg;

diff --git a/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd b/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd
new file mode 100644
index 000000000..375c9ac7e
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,86 @@
+-- ZPU

+--

+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

+-- 

+-- The FreeBSD license

+-- 

+-- Redistribution and use in source and binary forms, with or without

+-- modification, are permitted provided that the following conditions

+-- are met:

+-- 

+-- 1. Redistributions of source code must retain the above copyright

+--    notice, this list of conditions and the following disclaimer.

+-- 2. Redistributions in binary form must reproduce the above

+--    copyright notice, this list of conditions and the following

+--    disclaimer in the documentation and/or other materials

+--    provided with the distribution.

+-- 

+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+-- 

+-- The views and conclusions contained in the software and documentation

+-- are those of the authors and should not be interpreted as representing

+-- official policies, either expressed or implied, of the ZPU Project.

+

+library IEEE;

+use IEEE.STD_LOGIC_1164.all;

+use IEEE.STD_LOGIC_UNSIGNED.ALL;

+

+package wishbone_pkg is

+

+	type wishbone_bus_in is record

+		adr			: std_logic_vector(15 downto 0); 

+		sel			: std_logic_vector(3 downto 0); 

+		we			: std_logic;

+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'

+		cyc			: std_logic; 

+		stb			: std_logic;

+	end record;

+

+	type wishbone_bus_out is record

+		dat		: std_logic_vector(31 downto 0);

+		ack			: std_logic;

+	end record;

+	

+	type wishbone_bus is record

+		insig		: wishbone_bus_in;

+		outsig  	: wishbone_bus_out;

+	end record;

+

+	component atomic32_access is

+	port (	cpu_clk			: in std_logic;

+			areset			: in std_logic;

+	

+			-- Wishbone from CPU interface

+			wb_16_i			: in wishbone_bus_in;

+			wb_16_o     	: out wishbone_bus_out;

+			-- Wishbone to FPGA registers and ethernet core

+			wb_32_i			: in wishbone_bus_out;

+			wb_32_o			: out wishbone_bus_in);

+	end component;

+	

+	component eth_access_corr is

+	port (	cpu_clk			: in std_logic;

+			areset			: in std_logic;

+	

+			-- Wishbone from Wishbone MUX

+			eth_raw_o		: out wishbone_bus_out;

+			eth_raw_i		: in wishbone_bus_in;

+			

+			-- Wishbone ethernet core

+			eth_slave_i 	: in wishbone_bus_out;

+			eth_slave_o		: out wishbone_bus_in);

+	end component;

+

+

+end wishbone_pkg;

diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd
new file mode 100644
index 000000000..8af678b6a
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd
@@ -0,0 +1,106 @@
+-- ZPU

+--

+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

+-- 

+-- The FreeBSD license

+-- 

+-- Redistribution and use in source and binary forms, with or without

+-- modification, are permitted provided that the following conditions

+-- are met:

+-- 

+-- 1. Redistributions of source code must retain the above copyright

+--    notice, this list of conditions and the following disclaimer.

+-- 2. Redistributions in binary form must reproduce the above

+--    copyright notice, this list of conditions and the following

+--    disclaimer in the documentation and/or other materials

+--    provided with the distribution.

+-- 

+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+-- 

+-- The views and conclusions contained in the software and documentation

+-- are those of the authors and should not be interpreted as representing

+-- official policies, either expressed or implied, of the ZPU Project.

+

+library IEEE;

+use IEEE.STD_LOGIC_1164.all;

+use IEEE.STD_LOGIC_UNSIGNED.all; 

+

+library work;

+use work.zpu_top_pkg.all;

+use work.wishbone_pkg.all;

+use work.zpupkg.all;

+use work.zpu_config.all;

+

+entity zpu_system is

+	generic(

+			simulate		: boolean := false);

+	port (	areset			: in std_logic;

+			cpu_clk			: in std_logic;

+

+			-- ZPU Control signals

+			enable			: in std_logic;

+			interrupt		: in std_logic;

+			stack_start		: in std_logic_vector(maxAddrBitIncIO downto 0);

+			zpu_status		: out std_logic_vector(63 downto 0);

+

+			-- wishbone interfaces

+			zpu_wb_i		: in wishbone_bus_out;

+			zpu_wb_o		: out wishbone_bus_in);

+end zpu_system;

+

+architecture behave of zpu_system is

+

+signal	mem_req					: std_logic;

+signal	mem_we 					: std_logic;

+signal	mem_ack 				: std_logic; 

+signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);

+signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);

+signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);

+signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);

+

+

+begin

+

+	my_zpu_core:

+	zpu_core port map (

+    	clk 				=> cpu_clk, 

+		areset 				=> areset,

+	 	enable 				=> enable,

+	  	mem_req 			=> mem_req,

+	 	mem_we 				=> mem_we,

+	 	mem_ack 			=> mem_ack, 

+	 	mem_read 			=> mem_read,

+	 	mem_write 			=> mem_write,

+		out_mem_addr 		=> out_mem_addr,

+	 	mem_writeMask		=> mem_writeMask,

+	 	stack_start			=> stack_start,

+	 	interrupt			=> interrupt,

+	 	zpu_status			=> zpu_status,

+	 	break				=> open);

+

+	my_zpu_wb_bridge:

+	zpu_wb_bridge port map (

+		clk 				=> cpu_clk,

+	 	areset 				=> areset,

+	  	mem_req 			=> mem_req,

+	 	mem_we 				=> mem_we,

+	 	mem_ack 			=> mem_ack, 

+	 	mem_read 			=> mem_read,

+	 	mem_write 			=> mem_write,

+		out_mem_addr 		=> out_mem_addr,

+	 	mem_writeMask		=> mem_writeMask,

+		zpu_wb_i			=> zpu_wb_i,

+		zpu_wb_o			=> zpu_wb_o);

+

+end behave;

diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd
new file mode 100644
index 000000000..104ee10b8
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_wb_bridge.vhd
@@ -0,0 +1,83 @@
+-- ZPU

+--

+-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com

+-- 

+-- The FreeBSD license

+-- 

+-- Redistribution and use in source and binary forms, with or without

+-- modification, are permitted provided that the following conditions

+-- are met:

+-- 

+-- 1. Redistributions of source code must retain the above copyright

+--    notice, this list of conditions and the following disclaimer.

+-- 2. Redistributions in binary form must reproduce the above

+--    copyright notice, this list of conditions and the following

+--    disclaimer in the documentation and/or other materials

+--    provided with the distribution.

+-- 

+-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY

+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+-- 

+-- The views and conclusions contained in the software and documentation

+-- are those of the authors and should not be interpreted as representing

+-- official policies, either expressed or implied, of the ZPU Project.

+

+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+use IEEE.STD_LOGIC_UNSIGNED.ALL;

+

+library work;

+use work.zpu_top_pkg.all;

+use work.wishbone_pkg.all;

+use work.zpupkg.all;

+use work.zpu_config.all;

+

+entity zpu_wb_bridge is

+	port (	-- Native ZPU interface

+ 			clk 				: in std_logic;

+	 		areset 				: in std_logic;

+

+	 		mem_req 			: in std_logic;

+	 		mem_we				: in std_logic;

+	 		mem_ack				: out std_logic; 

+	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);

+	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);

+			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);

+	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);

+			

+			-- Wishbone from ZPU

+			zpu_wb_i			: in wishbone_bus_out;

+			zpu_wb_o			: out wishbone_bus_in);

+

+end zpu_wb_bridge;

+

+architecture behave of zpu_wb_bridge is

+

+begin

+

+	mem_read <= zpu_wb_i.dat;

+	mem_ack <= zpu_wb_i.ack;

+	

+	zpu_wb_o.adr <= out_mem_addr;

+	zpu_wb_o.dat <= mem_write;

+	zpu_wb_o.sel <= mem_writeMask;

+	zpu_wb_o.stb <= mem_req;

+	zpu_wb_o.cyc <= mem_req;

+	zpu_wb_o.we <= mem_we;

+

+end behave;

+

+			

+

+	

+

diff --git a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd
new file mode 100644
index 000000000..a158ab9c0
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpupkg.all;
+use work.zpu_config.all;
+use work.wishbone_pkg.all;
+
+package zpu_top_pkg is
+    component zpu_wb_bridge is
+    port (	-- Native ZPU interface
+            clk 				: in std_logic;
+            areset 				: in std_logic;
+
+            mem_req 			: in std_logic;
+            mem_we				: in std_logic;
+            mem_ack				: out std_logic; 
+            mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+            mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+            out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+            mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+            
+            -- Wishbone from ZPU
+            zpu_wb_i			: in wishbone_bus_out;
+            zpu_wb_o			: out wishbone_bus_in);
+    end component;
+
+    component zpu_system is
+    generic(
+            simulate		: boolean := false);
+    port (	areset			: in std_logic;
+            cpu_clk			: in std_logic;
+
+            -- ZPU Control signals
+            enable			: in std_logic;
+            interrupt		: in std_logic;
+            stack_start		: in std_logic_vector(maxAddrBitIncIO downto 0);
+            zpu_status		: out std_logic_vector(63 downto 0);
+
+            -- wishbone interfaces
+            zpu_wb_i		: in wishbone_bus_out;
+            zpu_wb_o		: out wishbone_bus_in);
+    end component;
+
+end zpu_top_pkg;
diff --git a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
new file mode 100644
index 000000000..9735c4b54
--- /dev/null
+++ b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd
@@ -0,0 +1,76 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_top_pkg.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+------------------------------------------------------------------------
+-- Top level ZPU + wishbone componenent to use in a verilog design:
+--   zpu_wb_top wraps around the zpu_system component.
+--   All IO lines are exposed as std_logic for verilog.
+------------------------------------------------------------------------
+entity zpu_wb_top is
+    generic (
+        dat_w: integer := 32;
+        adr_w: integer := 16;
+        sel_w: integer := 4
+    );
+    port (
+        clk: in std_logic;
+        rst: in std_logic;
+        enb: in std_logic;
+
+        -- wishbone interface
+        dat_i: in std_logic_vector(dat_w-1 downto 0);
+        ack_i: in std_logic;
+        adr_o: out std_logic_vector(adr_w-1 downto 0);
+        sel_o: out std_logic_vector(sel_w-1 downto 0);
+        we_o: out std_logic;
+        dat_o: out std_logic_vector(dat_w-1 downto 0);
+        cyc_o: out std_logic;
+        stb_o: out std_logic;
+
+        -- misc zpu signals
+        interrupt: in std_logic;
+        stack_start: in std_logic_vector(adr_w-1 downto 0);
+        zpu_status: out std_logic_vector(63 downto 0)
+    );
+
+end zpu_wb_top;
+
+architecture syn of zpu_wb_top is
+
+--wishbone interface (records)
+signal zpu_wb_i: wishbone_bus_out;
+signal zpu_wb_o: wishbone_bus_in;
+
+begin
+
+--assign wishbone signals to records
+zpu_wb_i.dat <= dat_i;
+zpu_wb_i.ack <= ack_i;
+
+adr_o <= zpu_wb_o.adr;
+sel_o <= zpu_wb_o.sel;
+we_o <= zpu_wb_o.we;
+dat_o <= zpu_wb_o.dat;
+cyc_o <= zpu_wb_o.cyc;
+stb_o <= zpu_wb_o.stb;
+
+--instantiate the zpu system
+zpu_system0: zpu_system port map(
+    cpu_clk => clk,
+    areset => rst,
+    enable => enb,
+    interrupt => interrupt,
+    stack_start => stack_start,
+    zpu_status => zpu_status,
+    zpu_wb_i => zpu_wb_i,
+    zpu_wb_o => zpu_wb_o
+);
+
+end architecture syn;
diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs
index 6480cd5a4..b82e64208 100644
--- a/fpga/usrp2/simple_gemac/Makefile.srcs
+++ b/fpga/usrp2/simple_gemac/Makefile.srcs
@@ -17,6 +17,7 @@ delay_line.v \
 flow_ctrl_tx.v \
 flow_ctrl_rx.v \
 address_filter.v \
+address_filter_promisc.v \
 ll8_to_txmac.v \
 rxmac_to_ll8.v \
 miim/eth_miim.v \
diff --git a/fpga/usrp2/simple_gemac/address_filter_promisc.v b/fpga/usrp2/simple_gemac/address_filter_promisc.v
new file mode 100644
index 000000000..6047e7c93
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/address_filter_promisc.v
@@ -0,0 +1,32 @@
+
+
+module address_filter_promisc
+  (input clk,
+   input reset,
+   input go,
+   input [7:0] data,
+   output match,
+   output done);
+
+   reg [2:0] af_state;
+
+   always @(posedge clk)
+     if(reset)
+       af_state     <= 0;
+     else
+       if(go)
+	 af_state <= (data[0] == 1'b0) ? 1 : 7;
+       else
+	 case(af_state)
+	   1 : af_state <= 2;
+	   2 : af_state <= 3;
+	   3 : af_state <= 4;
+	   4 : af_state <= 5;
+	   5 : af_state <= 6;
+	   6, 7 : af_state <= 0;
+	 endcase // case (af_state)
+
+   assign match  = (af_state==6);
+   assign done 	 = (af_state==6)|(af_state==7);
+   
+endmodule // address_filter_promisc
diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f36.v b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
index efd72778b..dc64971d4 100644
--- a/fpga/usrp2/simple_gemac/eth_tasks_f36.v
+++ b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
@@ -4,11 +4,11 @@ task SendFlowCtrl;
    input [15:0] fc_len;
    begin
       $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
-      pause_time <= fc_len;
+      //pause_time <= fc_len;
       @(posedge eth_clk);
-      pause_req <= 1;
+      //pause_req <= 1;
       @(posedge eth_clk);
-      pause_req <= 0;
+      //pause_req <= 0;
       $display("Sent Flow Control");
    end
 endtask // SendFlowCtrl
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
index b02bb0758..32f517bb3 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_rx.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
@@ -56,10 +56,10 @@ module simple_gemac_rx
      else
        rx_ack <= (rx_state == RX_GOODFRAME);
 
-   wire is_ucast, is_bcast, is_mcast, is_pause;
-   wire keep_packet  = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | 
-	(pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
-   
+   wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
+   wire keep_packet  = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | 
+	(pass_bcast & is_bcast) | (pass_pause & is_pause);
+      
    assign rx_data   = rxd_del;
    assign rx_error  = (rx_state == RX_ERROR);
 
@@ -79,6 +79,8 @@ module simple_gemac_rx
 			    .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
    address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
 			    .address(48'h0180_c200_0001), .match(is_pause), .done());
+   address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+				      .match(is_any_ucast), .done());
 
    always @(posedge rx_clk)
      go_filt 			 <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
index 6df277e3e..1ef38be11 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
@@ -1,16 +1,17 @@
 
 module wb_reg
   #(parameter ADDR=0,
-    parameter DEFAULT=0)
+    parameter DEFAULT=0,
+    parameter WIDTH=32)
    (input clk, input rst, 
     input [5:0] adr, input wr_acc,
-    input [31:0] dat_i, output reg [31:0] dat_o);
+    input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);
 
    always @(posedge clk)
      if(rst)
        dat_o <= DEFAULT;
      else if(wr_acc & (adr == ADDR))
-       dat_o <= dat_i;
+       dat_o <= dat_i[WIDTH-1:0];
    
 endmodule // wb_reg
 
@@ -41,19 +42,19 @@ module simple_gemac_wb
    wire [6:0] misc_settings;
    assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
 
-   wb_reg #(.ADDR(0),.DEFAULT(7'b0111001))
+   wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7))
    wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		    .dat_i(wb_dat_i), .dat_o(misc_settings) );
-   wb_reg #(.ADDR(1),.DEFAULT(0))
+   wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16))
    wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
-   wb_reg #(.ADDR(2),.DEFAULT(0))
+   wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32))
    wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
-   wb_reg #(.ADDR(3),.DEFAULT(0))
+   wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16))
    wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
-   wb_reg #(.ADDR(4),.DEFAULT(0))
+   wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32))
    wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
 
@@ -80,15 +81,15 @@ module simple_gemac_wb
    reg [15:0]  MIIRX_DATA;
    wire [2:0]  MIISTATUS;
 
-   wb_reg #(.ADDR(5),.DEFAULT(0))
+   wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9))
    wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		    .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
    
-   wb_reg #(.ADDR(6),.DEFAULT(0))
+   wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13))
    wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
    
-   wb_reg #(.ADDR(7),.DEFAULT(0))
+   wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16))
    wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		   .dat_i(wb_dat_i), .dat_o(CtrlData) );
    
@@ -133,11 +134,11 @@ module simple_gemac_wb
       .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), 
       .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
 
-   wb_reg #(.ADDR(11),.DEFAULT(0))
+   wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16))
    wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		     .dat_i(wb_dat_i), .dat_o(pause_time) );
    
-   wb_reg #(.ADDR(12),.DEFAULT(0))
+   wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16))
    wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
 		       .dat_i(wb_dat_i), .dat_o(pause_thresh) );
    
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
index 30f65ab17..9293deca6 100755
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
index 4be0aac1f..b9475baa2 100755
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
index 7d57542dc..b61d60d30 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb;
    reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
    wire        wb_ack;
 
-   reg [18:0]  tx_f19_data=0;
+   reg [19:0]  tx_f19_data=0;
    reg 	       tx_f19_src_rdy = 0;
    wire        tx_f19_dst_rdy;
-   wire [35:0] rx_f36_data;
-   wire        rx_f36_src_rdy;
-   wire        rx_f36_dst_rdy = 1;
+   wire [35:0] rx_f19_data;
+   wire        rx_f19_src_rdy;
+   wire        rx_f19_dst_rdy = 1;
    
    simple_gemac_wrapper19 simple_gemac_wrapper19
      (.clk125(eth_clk),  .reset(reset),
@@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb;
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       //.pause_req(pause_req), .pause_time(pause_time),
 
-      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
       .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
 
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
index 26a471a49..0aadc7e93 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
@@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb;
    
    wire [7:0] rx_data, tx_data;
    
-   reg [15:0] pause_time;
-   reg pause_req      = 0;
-
    wire GMII_RX_CLK   = GMII_GTX_CLK;
 
    reg [7:0] FORCE_DAT_ERR = 0;
@@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb;
    reg [35:0]  tx_f36_data=0;
    reg 	       tx_f36_src_rdy = 0;
    wire        tx_f36_dst_rdy;
-   wire        rx_f36_data;
+   wire [35:0] rx_f36_data;
    wire        rx_f36_src_rdy;
    wire        rx_f36_dst_rdy = 1;
    
@@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb;
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      .pause_req(pause_req), .pause_time(pause_time),
 
       .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
       .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index 30b47b818..413931ec9 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -3,7 +3,7 @@
 // ////////////////////////////////////////////////////////////////////////////////
 
 module u2_core
-  #(parameter RAM_SIZE=32768)
+  #(parameter RAM_SIZE=16384, parameter RAM_AW=14)
   (// Clocks
    input dsp_clk,
    input wb_clk,
@@ -163,7 +163,7 @@ module u2_core
    wire 	ram_loader_rst, wb_rst, dsp_rst;
    assign dsp_rst = wb_rst;
 
-   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire [31:0] 	status;
    wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
    wire 	proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
 
@@ -286,13 +286,11 @@ module u2_core
    // ///////////////////////////////////////////////////////////////////
    // RAM Loader
 
-   wire [31:0] 	 ram_loader_dat, if_dat;
+   wire [31:0] 	 ram_loader_dat;
    wire [15:0] 	 ram_loader_adr;
-   wire [14:0] 	 if_adr;
    wire [3:0] 	 ram_loader_sel;
    wire 	 ram_loader_stb, ram_loader_we;
-   wire 	 iwb_ack, iwb_stb;
-   ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+   ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE))
      ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
 		 .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
 		 .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
@@ -308,36 +306,34 @@ module u2_core
    
    // /////////////////////////////////////////////////////////////////////////
    // Processor
-   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
-     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
-	   // Instruction Wishbone bus to I-RAM
-	   .if_adr(if_adr),
-	   .if_dat(if_dat),
+
+   assign 	 bus_error = m0_err | m0_rty;
+
+   wire [63:0] zpu_status;
+   zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw))
+     zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done),
 	   // Data Wishbone bus to system bus fabric
-	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
-	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr),
+	   .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc),
 	   // Interrupts and exceptions
-	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
-   
-   assign 	 bus_error = m0_err | m0_rty;
+	   .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
    
    // /////////////////////////////////////////////////////////////////////////
    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
    // I-port connects directly to processor and ram loader
 
    wire 	 flush_icache;
-   ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+   ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 	     
-	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat),
 	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
 	     .ram_loader_we_i(ram_loader_we),
 	     .ram_loader_done_i(ram_loader_done),
 	     
-	     .if_adr(if_adr), 
-	     .if_data(if_dat), 
+	     .if_adr(16'b0), .if_data(),
 	     
-	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
 	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
 	     .flush_icache(flush_icache));
    
@@ -359,33 +355,32 @@ module u2_core
    wire 	 wr3_ready_i, wr3_ready_o;
    wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
    wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
-   
-   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+
+   wire [35:0] 	 tx_err_data;
+   wire 	 tx_err_src_rdy, tx_err_dst_rdy;
+
+   wire [31:0] router_debug;
+
+   packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
-      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
-   
-      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+
       .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .status(status),.sys_int_o(buffer_int),
-
-      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
-      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
-
-      // Write Interfaces
-      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
-      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
-      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
-      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
-      // Read Interfaces
-      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
-      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
-      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
-      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
-      );
 
-   wire [31:0] 	 status_enc;
-   priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),
+
+      .status(status), .sys_int_o(buffer_int), .debug(router_debug),
+
+      .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+      .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o),
+      .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+      .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+
+      .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+      .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+      .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+      );
    
    // /////////////////////////////////////////////////////////////////////////
    // SPI -- Slave #2
@@ -427,23 +422,23 @@ module u2_core
        cycle_count <= cycle_count + 1;
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = 32'd3;
+   localparam compat_num = 32'd4;
 
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-      
-      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
-      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+
+      .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+      .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
-      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count)
       );
 
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
    wire [18:0] 	 rx_f19_data, tx_f19_data;
-   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
    
    simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
@@ -459,37 +454,39 @@ module u2_core
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
 
-   wire [35:0] 	 udp_tx_data, udp_rx_data;
-   wire 	 udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
-   
-   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+   wire [35:0] 	 rx_f36_data, tx_f36_data;
+   wire 	 rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
+
+   wire [18:0] 	 _rx_f19_data;
+   wire 	 _rx_f19_src_rdy, _rx_f19_dst_rdy;
+
+   //mac rx to eth input...
+   fifo19_rxrealign fifo19_rxrealign
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
-      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
-      .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
-      .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
-      .debug(debug_udp) );
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
+      .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
 
-   wire [35:0] 	 tx_err_data, udp1_tx_data;
-   wire 	 tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+   fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
-      .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+      .f19_datain(_rx_f19_data),  .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
+      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
 
-   fifo36_mux #(.prio(0)) mux_err_stream
-     (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
-      .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
-      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
-      .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
-   
    fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+      .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
       .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-   
+
+   //eth output to mac tx...
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+      .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
+
+   fifo36_to_fifo19 eth_out_fifo36_to_fifo19
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .f36_datain(tx_f36_data),  .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
+      .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
+
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
    settings_bus settings_bus
@@ -691,7 +688,8 @@ module u2_core
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
-		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) 
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
+		   .DSP_NUMBER(0))
    vita_tx_chain
      (.clk(dsp_clk), .reset(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
@@ -721,13 +719,13 @@ module u2_core
    // VITA Timing
 
    wire [31:0] 	 debug_sync;
-   
+
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
       .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
       .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
       .debug(debug_sync));
-   
+
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
index f2bba6c50..759f7b7b8 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.v
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -471,7 +471,7 @@ module u2_rev3
    //
    
    
-   u2_core #(.RAM_SIZE(32768))
+   u2_core #(.RAM_SIZE(16384), .RAM_AW(14))
      u2_core(.dsp_clk           (dsp_clk),
 	     .wb_clk            (wb_clk),
 	     .clock_ready       (clock_ready),
diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi
index 7c15699db..4c7d918c0 100644
--- a/fpga/usrp2/top/u2plus/bootloader.rmi
+++ b/fpga/usrp2/top/u2plus/bootloader.rmi
@@ -1,245 +1,216 @@
-defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050;
-defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764;
-defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000;
-defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc;
-defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000;
-defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec;
-defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001;
-defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4;
-defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90;
-defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000;
-defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014;
-defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c;
-defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000;
-defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780;
-defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec;
-defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004;
-defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000;
-defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c;
-defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000;
-defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003;
-defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc;
-defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c;
-defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000;
-defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0;
-defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e;
-defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc;
-defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c;
-defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000;
-defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff;
-defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000;
-defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c;
-defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180;
-defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000;
-defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000;
-defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c;
-defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000;
-defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c;
-defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc;
-defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000;
-defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018;
-defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8;
-defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028;
-defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000;
-defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000;
-defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000;
-defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530;
-defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff;
-defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000;
-defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c;
-defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000;
-defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028;
-defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020;
-defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d;
-defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000;
-defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008;
-defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008;
-defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000;
-defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030;
-defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000;
-defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c;
-defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c;
-defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020;
-defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000;
-defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000;
-defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008;
-defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000;
-defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001;
-defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008;
-defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008;
-defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c;
-defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc;
-defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000;
-defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000;
-defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000;
-defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000;
-defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000;
-defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000;
-defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008;
-defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000;
-defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000;
-defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4;
-defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002;
-defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c;
-defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008;
-defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c;
-defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008;
-defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800;
-defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002;
-defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028;
-defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000;
-defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc;
-defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000;
-defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000;
-defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008;
-defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0;
-defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8;
-defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c;
-defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a;
-defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000;
-defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac;
-defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000;
-defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c;
-defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0;
-defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008;
-defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014;
-defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc;
-defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010;
-defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001;
-defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c;
-defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001;
-defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100;
-defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110;
-defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110;
-defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038;
-defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000;
-defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001;
-defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110;
-defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110;
-defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068;
-defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110;
-defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001;
-defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000;
-defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80;
-defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000;
-defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc;
-defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800;
-defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024;
-defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff;
-defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c;
-defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034;
-defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c;
-defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001;
-defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe;
-defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800;
-defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0;
-defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006;
-defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0;
-defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000;
-defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000;
-defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001;
-defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000;
-defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10;
-defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff;
-defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8;
-defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10;
-defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10;
-defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000;
-defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001;
-defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030;
-defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000;
-defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001;
-defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c;
-defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8;
-defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024;
-defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000;
-defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800;
-defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000;
-defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000;
-defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000;
-defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000;
-defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff;
-defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0;
-defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824;
-defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000;
-defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015;
-defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828;
-defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000;
-defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008;
-defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000;
-defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff;
-defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8;
-defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4;
-defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8;
-defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f;
-defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405;
-defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000;
-defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800;
-defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405;
-defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800;
-defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000;
-defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff;
-defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c;
-defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c;
-defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c;
-defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c;
-defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec;
-defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0;
-defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000;
-defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003;
-defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040;
-defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff;
-defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff;
-defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003;
-defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000;
-defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008;
-defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008;
-defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003;
-defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003;
-defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0;
-defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000;
-defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800;
-defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8;
-defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000;
-defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265;
-defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00;
-defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67;
-defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072;
-defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368;
-defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361;
-defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061;
-defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845;
-defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070;
-defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072;
-defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d;
-defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374;
-defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67;
-defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00;
-defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e;
-defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d;
-defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068;
-defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d;
-defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265;
-defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000;
-defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162;
-defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020;
-defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404;
-defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101;
-defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202;
-defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020;
-defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404;
-defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101;
-defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202;
-defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000;
-defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff;
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b70400_3a0b0b0b_0bae9c0c_80700b0b_0b0b0b0b;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4f42d_88080b0b_80088408;
+defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608;
+defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608;
+defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105;
+defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473;
+defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109;
+defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673;
+defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88;
+defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b;
+defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06;
+defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff;
+defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351;
+defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105;
+defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105;
+defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105;
+defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981;
+defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206;
+defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608;
+defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_88738306_0b0b0bae_71fc0608;
+defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ae2d5050_0b0b0b9e_88087575_80088408;
+defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_e02d5050_0b0b0b9f_88087575_80088408;
+defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081;
+defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081;
+defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504;
+defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae980c_810b0b0b;
+defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552;
+defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572;
+defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff;
+defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_943f0410_81f33f9e;
+defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010;
+defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472;
+defparam bootram.RAM0.INIT_23=256'hec0c8290_a0800bb5_b5e80c82_0b0b0b0b_38838080_08822eb9_a138ae9c_9808802e;
+defparam bootram.RAM0.INIT_24=256'h80808480_b5ec0cf8_8082800b_e80cf880_0b0b0bb5_8080a40b_0c04f880_800bb5f0;
+defparam bootram.RAM0.INIT_25=256'h0ba6c40b_ec0c0b0b_80940bb5_0c80c0a8_0b0bb5e8_808c0b0b_0480c0a8_0bb5f00c;
+defparam bootram.RAM0.INIT_26=256'haea40c70_92388412_5270802e_08700852_a338aea4_f4335170_ff3d0db5_b5f00c04;
+defparam bootram.RAM0.INIT_27=256'he408802e_0b0b0bb5_04803d0d_833d0d04_0bb5f434_70f03881_70085252_2daea408;
+defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5e4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b;
+defparam bootram.RAM0.INIT_29=256'h518bc93f_d0055273_3fb23dfe_525486a0_59923d70_3dfee005_d03d0db2_3d0d0404;
+defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c93fa6c8_52735198_38765378_ff74278f_775481ff_8008b238;
+defparam bootram.RAM0.INIT_2B=256'hb039803d_859e3fff_39a78051_a6cc5184_3f91d73f_c85185ac_068f38a6_812e0981;
+defparam bootram.RAM0.INIT_2C=256'h0ca78851_0b81a08c_3d0d81ff_3d0d04fc_51f63982_380bff11_70ff2e87_0dff1351;
+defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84e23f83_3fa78451_e13f86d6_85e13f8e_81a08c0c_dd3f800b;
+defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184bd3f_c338a7b0_51547380_70810651_08708d2a_3f81c6b4_805182ed;
+defparam bootram.RAM0.INIT_2F=256'h8eab3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190b63f;
+defparam bootram.RAM0.INIT_30=256'he45183f8_74b238a8_3ffe8d3f_8c518484_3f8a39a8_73519192_5184913f_c53fa7d0;
+defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183e53f_9938a990_8008802e_518fa13f_3fb0800a;
+defparam bootram.RAM0.INIT_32=256'h83ba3f82_38aa9851_08802eaa_8fc73f80_98800a51_5183cd3f_d93fa9c8_800a5190;
+defparam bootram.RAM0.INIT_33=256'h3faae851_853f8fca_82ac51fe_5183a53f_bc3faac4_800a518d_ffff5298_80805380;
+defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518f8a3f_81fc8080_5183913f_ba39aba4;
+defparam bootram.RAM0.INIT_35=256'hdb3f82ac_a7d05182_3f8f8f3f_ac51fdca_82ea3f82_3faac451_80518d81_5281fc80;
+defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82c63ffc_39a88c51_3f81548a_80518fd6_51fdbb3f;
+defparam bootram.RAM0.INIT_37=256'h70810558_8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f;
+defparam bootram.RAM0.INIT_38=256'h8a5186fd_81ff0654_cf3f8008_ff065185_05527781_538a3dfc_a1053482_33028405;
+defparam bootram.RAM0.INIT_39=256'h748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e;
+defparam bootram.RAM0.INIT_3A=256'h7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d;
+defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_ef3f8008_70525684_02a70533_3dfc0552_34815389_0533893d;
+defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183b2_76537b52_77259738_2e9e3880;
+defparam bootram.RAM0.INIT_3D=256'h883d3356_a03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89;
+defparam bootram.RAM0.INIT_3E=256'h7081ff06_56567433_3d0d7779_3d0d04fb_75800c88_83388156_2e098106_567480de;
+defparam bootram.RAM0.INIT_3F=256'h0d04fe3d_800c873d_e539800b_5581bb3f_06537652_157481ff_2e903881_54547280;
+defparam bootram.RAM1.INIT_00=256'h528051de_ff3d0d73_843d0d04_800b800c_51819f3f_3f8a5272_705253cb_0d747653;
+defparam bootram.RAM1.INIT_01=256'h800881ff_80087334_5181b23f_81135374_55558439_76787055_04fc3d0d_3f833d0d;
+defparam bootram.RAM1.INIT_02=256'h3f833d0d_528051c9_ff3d0d73_863d0d04_3473800c_e7388073_2e098106_0652718a;
+defparam bootram.RAM1.INIT_03=256'h7510abe0_81ce8005_0d73a029_0d04ff3d_1234823d_0533aea8_7251028f_04803d0d;
+defparam bootram.RAM1.INIT_04=256'h33527251_3faeac13_527251c9_aea81333_3d0d8053_3d0d04fe_0c535183_05702272;
+defparam bootram.RAM1.INIT_05=256'h38aea814_09810694_54748a2e_0d767856_0d04fc3d_e738843d_53827325_d13f8113;
+defparam bootram.RAM1.INIT_06=256'h72802ef8_84140853_ce800554_73a02981_7351df3f_87388d52_2e098106_33537281;
+defparam bootram.RAM1.INIT_07=256'h38901208_70802ef8_88120851_ce800552_73a02981_04ff3d0d_0c863d0d_38748c15;
+defparam bootram.RAM1.INIT_08=256'h38845170_84712583_8f065151_c6a40870_c2880c81_0d800b81_0d04ff3d_800c833d;
+defparam bootram.RAM1.INIT_09=256'h880c833d_800b81c2_0c515181_2a81c284_800c7088_ff0681c2_70227081_10aeb005;
+defparam bootram.RAM1.INIT_0A=256'h70862a70_81c29008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d;
+defparam bootram.RAM1.INIT_0B=256'h812a7081_c2900870_c2900c81_81900b81_81c28c0c_72108107_5170f138_81065151;
+defparam bootram.RAM1.INIT_0C=256'h3871802e_70802eba_51515151_06708132_872a7081_c2900870_70f13881_06515151;
+defparam bootram.RAM1.INIT_0D=256'h515170f1_70810651_0870812a_0c81c290_7081c290_8338a051_5171812e_b13880e8;
+defparam bootram.RAM1.INIT_0E=256'h0c70800c_0b81c290_883980c0_cc398151_34ff1252_70810556_08517074_3881c28c;
+defparam bootram.RAM1.INIT_0F=256'h51515170_2a708106_90087086_535481c2_97053355_78028805_fd3d0d76_853d0d04;
+defparam bootram.RAM1.INIT_10=256'h70812a70_81c29008_81c2900c_81905170_802e8438_81d05171_81c28c0c_f1387210;
+defparam bootram.RAM1.INIT_11=256'h80cf3871_5170802e_32515151_81067081_70872a70_81c29008_5170f138_81065151;
+defparam bootram.RAM1.INIT_12=256'h90087081_900c81c2_517081c2_2e833890_d0517181_c28c0c80_38733381_802e80c5;
+defparam bootram.RAM1.INIT_13=256'h802e8e38_51515170_70813251_2a708106_90087087_f13881c2_51515170_2a708106;
+defparam bootram.RAM1.INIT_14=256'h04ff3d0d_0c853d0d_80517080_81c2900c_3980c00b_3981518a_5354ffb7_8114ff13;
+defparam bootram.RAM1.INIT_15=256'hc01122ae_108e06ae_c6a40870_25923881_aebc0880_7124a638_08525280_7381c6a4;
+defparam bootram.RAM1.INIT_16=256'hffa91170_028f0533_04ff3d0d_38833d0d_115170fb_387151ff_80722589_bc0c5151;
+defparam bootram.RAM1.INIT_17=256'h81ff0651_38d01270_71b92689_ff065151_c9127081_da269638_52527180_81ff0651;
+defparam bootram.RAM1.INIT_18=256'h82ef3881_2e098106_ff5371ba_76335358_7b585680_f93d0d79_833d0d04_5170800c;
+defparam bootram.RAM1.INIT_19=256'hc4065151_11337080_7033abf5_ff067219_81147081_2eaa3872_53537178_0b811733;
+defparam bootram.RAM1.INIT_1A=256'h08842b9f_fefb3f80_81163351_5271d838_16703351_82bd3872_5271802e_51535154;
+defparam bootram.RAM1.INIT_1B=256'h5354fd53_8b113357_0c701017_05708419_81ff0672_ec3f8008_335252fe_f0068217;
+defparam bootram.RAM1.INIT_1C=256'h08882b83_febb3f80_17335253_e0800684_088c2bbf_fecb3f80_83163351_74828a38;
+defparam bootram.RAM1.INIT_1D=256'h983f8008_335253fe_73058617_2b9ff006_3f800884_5253fea9_05851733_fe800673;
+defparam bootram.RAM1.INIT_1E=256'hf83f8008_335252fd_f0068817_08842b9f_fe873f80_87163351_0588180c_81ff0673;
+defparam bootram.RAM1.INIT_1F=256'h05523355_19707081_19081771_81ff068c_10890570_80d23874_34747427_12527177;
+defparam bootram.RAM1.INIT_20=256'h8c170815_53727434_3f800813_5253fdc1_f0067233_08842b9f_fdcf3f80_52565152;
+defparam bootram.RAM1.INIT_21=256'h84170888_26ffb038_84170875_5b515152_ff065a52_81197081_7081ff06_7033701a;
+defparam bootram.RAM1.INIT_22=256'h5b515354_11335654_73101a89_7081ff06_05197030_2a055473_72057188_18087833;
+defparam bootram.RAM1.INIT_23=256'h5377722e_065152fb_127081ff_e43f8008_335252fc_f0068a15_08842b9f_fcf33f80;
+defparam bootram.RAM1.INIT_24=256'h882a7081_d6900870_803d0d81_893d0d04_5372800c_53833980_388539fe_09810689;
+defparam bootram.RAM1.INIT_25=256'hc0800753_80060780_ff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151;
+defparam bootram.RAM1.INIT_26=256'h81ff0681_d6900c75_800c7181_387681d6_515170f1_70810651_0870882a_5381d690;
+defparam bootram.RAM1.INIT_27=256'h51515170_2a708106_90087088_963881d6_5172802e_d6900c72_82800781_d6980c71;
+defparam bootram.RAM1.INIT_28=256'h80538052_80558854_d6940c88_0d810b81_0d04fc3d_800c843d_80085170_f13881d6;
+defparam bootram.RAM1.INIT_29=256'h900c8b0b_800b81d6_d6980c88_3f800b81_7d56fee4_04f63d0d_3f863d0d_8051ff87;
+defparam bootram.RAM1.INIT_2A=256'hd6900cfe_8aa80b81_81d6900c_0c88a80b_0b81d698_d6800c81_7c882b81_81d6840c;
+defparam bootram.RAM1.INIT_2B=256'h3f81d68c_900cfe98_800b81d6_d6900c8a_88800b81_2780d338_80547376_b33f7e55;
+defparam bootram.RAM1.INIT_2C=256'h27833870_90537073_75315257_5b883d76_81d68008_d684085a_88085981_085881d6;
+defparam bootram.RAM1.INIT_2D=256'ha939800b_721454ff_1252ec39_05573481_33757081_71175170_73279138_53805271;
+defparam bootram.RAM1.INIT_2E=256'h9d055755_80028405_51fed23f_80c05268_3d705457_ea3d0d88_8c3d0d04_81d6980c;
+defparam bootram.RAM1.INIT_2F=256'h81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381_74177033;
+defparam bootram.RAM1.INIT_30=256'h863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39_81068538;
+defparam bootram.RAM1.INIT_31=256'h38815574_09810683_8008752e_5185f73f_abec5273_80558653_51fe823f_54865279;
+defparam bootram.RAM1.INIT_32=256'h0771832a_0671872a_70852a82_02970533_04fd3d0d_81a0940c_0d04810b_800c893d;
+defparam bootram.RAM1.INIT_33=256'h76852b80_7081ff06_71730707_832ba006_10900674_73070773_2a880671_84067281;
+defparam bootram.RAM1.INIT_34=256'h0d04fe3d_5552853d_51555255_0c515253_0681d480_077081ff_0778872b_c0067072;
+defparam bootram.RAM1.INIT_35=256'h819951ff_51ff923f_983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a;
+defparam bootram.RAM1.INIT_36=256'h0651feed_3f7281ff_5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251;
+defparam bootram.RAM1.INIT_37=256'hfecf3fb0_ff065253_902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe;
+defparam bootram.RAM1.INIT_38=256'hb03fa051_3f8051fe_a051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f;
+defparam bootram.RAM1.INIT_39=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_ff398c08_843d0d04_51fea63f_feab3f80;
+defparam bootram.RAM1.INIT_3A=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025;
+defparam bootram.RAM1.INIT_3B=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4;
+defparam bootram.RAM1.INIT_3C=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c;
+defparam bootram.RAM1.INIT_3D=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80;
+defparam bootram.RAM1.INIT_3E=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e;
+defparam bootram.RAM1.INIT_3F=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c;
+defparam bootram.RAM2.INIT_00=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81;
+defparam bootram.RAM2.INIT_01=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05;
+defparam bootram.RAM2.INIT_02=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805;
+defparam bootram.RAM2.INIT_03=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b;
+defparam bootram.RAM2.INIT_04=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e;
+defparam bootram.RAM2.INIT_05=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc;
+defparam bootram.RAM2.INIT_06=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508;
+defparam bootram.RAM2.INIT_07=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508;
+defparam bootram.RAM2.INIT_08=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c;
+defparam bootram.RAM2.INIT_09=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c;
+defparam bootram.RAM2.INIT_0A=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff;
+defparam bootram.RAM2.INIT_0B=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff;
+defparam bootram.RAM2.INIT_0C=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414;
+defparam bootram.RAM2.INIT_0D=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079;
+defparam bootram.RAM2.INIT_0E=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081;
+defparam bootram.RAM2.INIT_0F=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084;
+defparam bootram.RAM2.INIT_10=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553;
+defparam bootram.RAM2.INIT_11=256'hae9c0854_3d0d800b_ff8339fd_ed387054_52718326_530cfc12_71708405_84055408;
+defparam bootram.RAM2.INIT_12=256'h3f72b5f8_8008519b_51e6bc3f_aed05281_3fe3b13f_f80ce493_983873b5_5472812e;
+defparam bootram.RAM2.INIT_13=256'hd40882c8_3d0d7bae_00ff39f7_0851843f_e6a53f80_d0528151_e39a3fae_0ce3fc3f;
+defparam bootram.RAM2.INIT_14=256'h80e93880_59807424_712b5955_08ff0581_88188419_80d93881_5a77802e_11085a54;
+defparam bootram.RAM2.INIT_15=256'h08535379_38781670_72802eb5_08770653_56818019_11880556_73822b78_7424b538;
+defparam bootram.RAM2.INIT_16=256'hffad38ae_77085877_8025d638_57575473_79812c5a_fc17fc17_722dff14_51740853;
+defparam bootram.RAM2.INIT_17=256'h57575473_79812c5a_fc17fc17_722dff14_3f740853_7951f8c0_1308a538_d40853bc;
+defparam bootram.RAM2.INIT_18=256'hb5d80bfc_3fff3d0d_7951f894_0853722d_7251bc13_57ff9439_38d23980_8025ffa9;
+defparam bootram.RAM2.INIT_19=256'h0d0404e3_f138833d_2e098106_525270ff_fc127008_9138702d_5270ff2e_05700852;
+defparam bootram.RAM2.INIT_1A=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_833f0400;
+defparam bootram.RAM2.INIT_1B=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e;
+defparam bootram.RAM2.INIT_1C=256'h756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00;
+defparam bootram.RAM2.INIT_1D=256'h50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50;
+defparam bootram.RAM2.INIT_1E=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073;
+defparam bootram.RAM2.INIT_1F=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d;
+defparam bootram.RAM2.INIT_20=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068;
+defparam bootram.RAM2.INIT_21=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520;
+defparam bootram.RAM2.INIT_22=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046;
+defparam bootram.RAM2.INIT_23=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000;
+defparam bootram.RAM2.INIT_24=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650;
+defparam bootram.RAM2.INIT_25=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047;
+defparam bootram.RAM2.INIT_26=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f;
+defparam bootram.RAM2.INIT_27=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61;
+defparam bootram.RAM2.INIT_28=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f;
+defparam bootram.RAM2.INIT_29=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563;
+defparam bootram.RAM2.INIT_2A=256'h6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00;
+defparam bootram.RAM2.INIT_2B=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765;
+defparam bootram.RAM2.INIT_2C=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67;
+defparam bootram.RAM2.INIT_2D=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000;
+defparam bootram.RAM2.INIT_2E=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75;
+defparam bootram.RAM2.INIT_2F=256'h20202828_20202020_00202020_80700000_0b0b0b0b_01b200d9_05160364_14580a2c;
+defparam bootram.RAM2.INIT_30=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820;
+defparam bootram.RAM2.INIT_31=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010;
+defparam bootram.RAM2.INIT_32=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101;
+defparam bootram.RAM2.INIT_33=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202;
+defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_37=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_38=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000;
+defparam bootram.RAM2.INIT_39=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001ae0_00000000;
+defparam bootram.RAM2.INIT_3A=256'h000019c0_00000000_00001758_000016f8_06820594_09c407d0_13880d05_00002710;
+defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001a78_00001a1c;
+defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00001704_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001;
+defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_16=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
index 4e0b190ef..c152f083e 100644
--- a/fpga/usrp2/top/u2plus/u2plus_core.v
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -131,7 +131,7 @@ module u2plus_core
    output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi
    );
 
-   localparam SR_BUF_POOL = 64;   // Uses 1 reg
+   localparam SR_BUF_POOL = 64;   // router
    localparam SR_UDP_SM   = 96;   // 64 regs
    localparam SR_RX_DSP   = 160;  // 16
    localparam SR_RX_CTRL  = 176;  // 16
@@ -155,7 +155,7 @@ module u2plus_core
    
    wire 	wb_rst, dsp_rst;
 
-   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire [31:0] 	status;
    wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
    wire 	proc_int, overrun, underrun;
    wire [3:0] 	uart_tx_int, uart_rx_int;
@@ -197,21 +197,21 @@ module u2plus_core
    
    wb_1master #(.decode_w(8),
 		.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000),  // 0-8K, Boot RAM
-		.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000),  // 16K-32K, Buffer Pool
- 		.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111),  // SPI
-		.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111),  // I2C
-		.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111),  // GPIO
-		.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111),  // Readback
-		.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111),  // Ethernet MAC
-		.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000),  // 8-12K, Settings Bus (only uses 1K)
-		.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111),  // PIC
-		.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111),  // Unused
-		.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111),  // UART
-		.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111),  // ATR
-		.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111),  // Unused
-		.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111),  // ICAP
-		.se_addr(8'b0011_1011),.se_mask(8'b1111_1111),  // SPI Flash
-		.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000),  // 32-64K, Main RAM
+		.s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000),  // 16K-20K, Buffer Pool
+		.s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111),  // SPI
+		.s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111),  // I2C
+		.s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111),  // GPIO
+		.s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111),  // Readback
+		.s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111),  // Ethernet MAC
+		.s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000),  // 20K-24K, Settings Bus (only uses 1K)
+		.s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111),  // PIC
+		.s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111),  // Unused
+		.sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111),  // UART
+		.sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111),  // ATR
+		.sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111),  // Unused
+		.sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111),  // ICAP
+		.se_addr(8'b0110_1011),.se_mask(8'b1111_1111),  // SPI Flash
+		.sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000),  // 32-48K, Main RAM
 		.dw(dw),.aw(aw),.sw(sw)) wb_1master
      (.clk_i(wb_clk),.rst_i(wb_rst),       
       .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
@@ -251,35 +251,72 @@ module u2plus_core
       
    //////////////////////////////////////////////////////////////////////////////////////////
    // Reset Controller
-   
+
+    reg cpu_bldr_ctrl_state;
+    localparam CPU_BLDR_CTRL_WAIT = 0;
+    localparam CPU_BLDR_CTRL_DONE = 1;
+
+    wire bldr_done;
+    reg cpu_rst;
+    wire cpu_enb = ~cpu_rst;
+    wire [aw-1:0] cpu_adr;
+    wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)?
+        16'hfff8 : //top of 8K boot ram re-purposed at 56K
+        16'h1ff8 ; //top of 8K boot ram
+
+    //When the main program runs, it will try to access system ram at 0.
+    //This logic re-maps the cpu address to force select the system ram.
+    assign m0_adr =
+        (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader
+        (cpu_adr[15:14] == 2'b00)?   {2'b10, cpu_adr[13:0]}  : ( //map 0-16 to 32-48 (main ram)
+        (cpu_adr[15:13] == 3'b111)?  {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram)
+    cpu_adr))); //otherwise
+
+    always @(posedge wb_clk)
+    if(wb_rst) begin
+        cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT;
+        cpu_rst <= 1'b1;
+    end
+    else begin
+        case(cpu_bldr_ctrl_state)
+
+        CPU_BLDR_CTRL_WAIT: begin
+            cpu_rst <= 1'b0;
+            if (bldr_done == 1'b1) begin //set by the bootloader
+                cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE;
+                cpu_rst <= 1'b1;
+            end
+        end
+
+        CPU_BLDR_CTRL_DONE: begin //stay here forever
+            cpu_rst <= 1'b0;
+        end
+
+        endcase //cpu_bldr_ctrl_state
+    end
+
    // /////////////////////////////////////////////////////////////////////////
    // Processor
-   wire [31:0] 	 if_dat;
-   wire [15:0] 	 if_adr;
-
-   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
-     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
-	   // Instruction Wishbone bus to I-RAM
-	   .if_adr(if_adr),
-	   .if_dat(if_dat),
+
+   assign 	 bus_error = m0_err | m0_rty;
+
+   wire [63:0] zpu_status;
+   zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw))
+     zpu_top0 (.clk(wb_clk), .rst(wb_rst | cpu_rst), .enb(cpu_enb),
 	   // Data Wishbone bus to system bus fabric
-	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
-	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr),
+	   .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc),
 	   // Interrupts and exceptions
-	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
-   
-   assign 	 bus_error = m0_err | m0_rty;
-   
+	   .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
+
+
    // /////////////////////////////////////////////////////////////////////////
    // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
    // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone
    // I-port connects directly to processor
 
-   wire [31:0] 	 if_dat_boot, if_dat_main;
-   assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot;
-   
    bootram bootram(.clk(wb_clk), .reset(wb_rst),
-		   .if_adr(if_adr[12:0]), .if_data(if_dat_boot), 
+		   .if_adr(13'b0), .if_data(),
 		   .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
 		   .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
 
@@ -289,10 +326,10 @@ module u2plus_core
 
 `include "bootloader.rmi"
 
-   ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768))
+   ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384))
    sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),	     
-	   .if_adr(if_adr[14:0]), .if_data(if_dat_main), 
-	   .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
+	   .if_adr(14'b0), .if_data(),
+	   .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
 	   .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel));
    
    // /////////////////////////////////////////////////////////////////////////
@@ -310,34 +347,33 @@ module u2plus_core
    wire 	 wr3_ready_i, wr3_ready_o;
    wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
    wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
-   
-   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+
+   wire [35:0] 	 tx_err_data;
+   wire 	 tx_err_src_rdy, tx_err_dst_rdy;
+
+   wire [31:0] router_debug;
+
+   packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
-      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
-   
-      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+
       .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .status(status),.sys_int_o(buffer_int),
-
-      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
-      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
-
-      // Write Interfaces
-      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
-      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
-      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
-      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
-      // Read Interfaces
-      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
-      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
-      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
-      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),
+
+      .status(status), .sys_int_o(buffer_int), .debug(router_debug),
+
+      .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+      .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o),
+      .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+      .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+
+      .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+      .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+      .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
       );
 
-   wire [31:0] 	 status_enc;
-   priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
-   
    // /////////////////////////////////////////////////////////////////////////
    // SPI -- Slave #2
    spi_top shared_spi
@@ -378,23 +414,23 @@ module u2plus_core
        cycle_count <= cycle_count + 1;
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = 32'd3;
+   localparam compat_num = 32'd4;
 
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
       
-      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
-      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+      .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
-      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count)
       );
 
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
    wire [18:0] 	 rx_f19_data, tx_f19_data;
-   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
    
    simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
@@ -410,36 +446,38 @@ module u2plus_core
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
 
-   wire [35:0] 	 udp_tx_data, udp_rx_data;
-   wire 	 udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
-   
-   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+   wire [35:0] 	 rx_f36_data, tx_f36_data;
+   wire 	 rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
+
+   wire [18:0] 	 _rx_f19_data;
+   wire 	 _rx_f19_src_rdy, _rx_f19_dst_rdy;
+
+   //mac rx to eth input...
+   fifo19_rxrealign fifo19_rxrealign
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
-      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
-      .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
-      .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
-      .debug(debug_udp) );
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
+      .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
 
-   wire [35:0] 	 tx_err_data, udp1_tx_data;
-   wire 	 tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+   fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
-      .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+      .f19_datain(_rx_f19_data),  .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
+      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
 
-   fifo36_mux #(.prio(0)) mux_err_stream
-     (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
-      .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
-      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
-      .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
-   
    fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+      .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
       .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
+
+   //eth output to mac tx...
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+      .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
+
+   fifo36_to_fifo19 eth_out_fifo36_to_fifo19
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .f36_datain(tx_f36_data),  .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
+      .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
    
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
@@ -471,6 +509,8 @@ module u2plus_core
 				      .in(set_data),.out(adc_outs),.changed());
    setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 				      .in(set_data),.out(phy_reset),.changed());
+   setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(bldr_done),.changed());
 
    // /////////////////////////////////////////////////////////////////////////
    //  LEDS
@@ -652,7 +692,8 @@ module u2plus_core
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
-		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) 
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
+		   .DSP_NUMBER(0))
    vita_tx_chain
      (.clk(dsp_clk), .reset(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v
index a18eb73ae..c642842f6 100644
--- a/fpga/usrp2/udp/prot_eng_tx.v
+++ b/fpga/usrp2/udp/prot_eng_tx.v
@@ -7,6 +7,8 @@
 //            Odd means the last word is half full
 //   Flags[1:0] is {eop, sop}
 //   Protocol word format is:
+//             21   UDP Source Port Here
+//             20   UDP Dest Port Here
 //             19   Last Header Line
 //             18   IP Header Checksum XOR
 //             17   IP Length Here
@@ -34,28 +36,40 @@ module prot_eng_tx
    assign dst_rdy_o 	 = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30));
    assign src_rdy_o 	 = src_rdy_i & ~((state==0) | (state==1) | (state==30));
    
-   localparam HDR_WIDTH  = 16 + 4;  // 16 bits plus flags
+   localparam HDR_WIDTH  = 16 + 6;  // 16 bits plus flags
    localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
    
    // Store header values in a small dual-port (distributed) ram
    reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
    wire [HDR_WIDTH-1:0] header_word;
-   reg [15:0]  chk_precompute;
-   
+
+   reg [1:0] 		port_sel;
+   reg [31:0] 		per_port_data[0:3];
+   reg [15:0] 		udp_src_port, udp_dst_port, chk_precompute;
+
+   always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16];
+   always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0];
+
    always @(posedge clk)
      if(set_stb & ((set_addr & 8'hE0) == BASE))
-       begin
-	  header_ram[set_addr[4:0]] <= set_data;
-	  if(set_data[18])
-	    chk_precompute <= set_data[15:0];
-       end
+       header_ram[set_addr[4:0]] <= set_data;
+
+   always @(posedge clk)
+     if(set_stb & (set_addr == (BASE + 14)))
+       chk_precompute <= set_data[15:0];
+
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hFC) == (BASE+24)))
+       per_port_data[set_addr[1:0]] <= set_data;
    
-   assign header_word = header_ram[state];
+   wire do_udp_src_port = header_word[21];
+   wire do_udp_dst_port = header_word[20];
+   wire last_hdr_line   = header_word[19];
+   wire do_ip_chk       = header_word[18];
+   wire do_ip_len       = header_word[17];
+   wire do_udp_len      = header_word[16];
 
-   wire last_hdr_line  = header_word[19];
-   wire ip_chk 	       = header_word[18];
-   wire ip_len 	       = header_word[17];
-   wire udp_len        = header_word[16];
+   assign header_word = header_ram[state];
    
    // Protocol State Machine
    reg [15:0] length;
@@ -75,6 +89,7 @@ module prot_eng_tx
 	   0 :
 	     begin
 		fast_path <= datain[0];
+		port_sel <= datain[2:1];
 		state <= 1;
 	     end
 	   1 :
@@ -113,15 +128,18 @@ module prot_eng_tx
      checksum_reg <= checksum;
    
    always @*
-     if(ip_chk)
-       //dataout_int 	<= header_word[15:0] ^ ip_length;
+     if(do_payload)
+       dataout_int 	<= datain[15:0];
+     else if(do_ip_chk)
        dataout_int 	<= 16'hFFFF ^ checksum_reg;
-     else if(ip_len)
+     else if(do_ip_len)
        dataout_int 	<= ip_length;
-     else if(udp_len)
+     else if(do_udp_len)
        dataout_int 	<= udp_length;
-     else if(do_payload)
-       dataout_int 	<= datain[15:0];
+     else if(do_udp_src_port)
+       dataout_int      <= udp_src_port;
+     else if(do_udp_dst_port)
+       dataout_int      <= udp_dst_port;
      else
        dataout_int 	<= header_word[15:0];
    
diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v
index e7ffeb5e1..c8fffe605 100644
--- a/fpga/usrp2/udp/prot_eng_tx_tb.v
+++ b/fpga/usrp2/udp/prot_eng_tx_tb.v
@@ -80,7 +80,7 @@ module prot_eng_tx_tb();
       begin
 	 count 	      <= 4;
 	 src_rdy_f36i <= 1;
-	 f36_data     <= 32'h0001_000c;
+	 f36_data     <= 32'h0003_000c;
 	 f36_sof      <= 1;
 	 f36_eof      <= 0;
 	 f36_occ      <= 0;
@@ -140,16 +140,23 @@ module prot_eng_tx_tb();
 	@(negedge rst);
 	@(posedge clk);
 	WriteSREG(BASE, {12'b0, 4'h0, 16'h0000});
-	WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000});
-	WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD});
-	WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234});
-	WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678});
-	WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD});
-	WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD});
-	WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD});
-	WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD});
-	WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000});
+	WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD});
+	WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234});
+	WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678});
+	WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D});
+	WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF});
+	WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA});
+	WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321});
+	WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD});
+	WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD});
 	@(posedge clk);
+	
+	WriteSREG(BASE+24, 16'h6666);
+	WriteSREG(BASE+25, 16'h7777);
+	WriteSREG(BASE+26, 16'h8888);
+	WriteSREG(BASE+27, 16'h9999);
+	
 	PutPacketInFIFO36(32'hA0B0C0D0,16);
 	@(posedge clk);
 	@(posedge clk);
diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v
index 44bb7b548..cc34cceed 100644
--- a/fpga/usrp2/vrt/gen_context_pkt.v
+++ b/fpga/usrp2/vrt/gen_context_pkt.v
@@ -1,7 +1,8 @@
 
 
 module gen_context_pkt
-  #(parameter PROT_ENG_FLAGS=1)
+  #(parameter PROT_ENG_FLAGS=1,
+    parameter DSP_NUMBER=0)
    (input clk, input reset, input clear,
     input trigger, output sent,
     input [31:0] streamid,
@@ -67,10 +68,10 @@ module gen_context_pkt
        endcase // case (ctxt_state)
 
    assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) );
-   
+
    always @*
      case(ctxt_state)
-       CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 };
+       CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3
        CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
        CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v
index 2ec78189b..6f567668d 100644
--- a/fpga/usrp2/vrt/vita_tx_chain.v
+++ b/fpga/usrp2/vrt/vita_tx_chain.v
@@ -5,7 +5,8 @@ module vita_tx_chain
     parameter REPORT_ERROR=0,
     parameter DO_FLOW_CONTROL=0,
     parameter PROT_ENG_FLAGS=0,
-    parameter USE_TRANS_HEADER=0)
+    parameter USE_TRANS_HEADER=0,
+    parameter DSP_NUMBER=0)
    (input clk, input reset,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input [63:0] vita_time,
@@ -71,7 +72,7 @@ module vita_tx_chain
    wire [35:0] 		flow_data, err_data_int;
    wire 		flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int;
    
-   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt
+   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(32'd0),
@@ -82,7 +83,7 @@ module vita_tx_chain
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .packet_consumed(packet_consumed), .trigger(trigger));
    
-   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(message),
diff --git a/host/docs/transport.rst b/host/docs/transport.rst
index d9abd4923..018f909c1 100644
--- a/host/docs/transport.rst
+++ b/host/docs/transport.rst
@@ -36,7 +36,7 @@ The following parameters can be used to alter the transport's default behavior:
 * **num_send_frames:** The number of send buffers to allocate
 * **concurrency_hint:** The number of threads to run the IO service
 
-**Note:** num_send_frames and concurrency_hint will not have an effect
+**Note:** num_send_frames will not have an effect
 as the asynchronous send implementation is currently disabled.
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst
index 8e5743102..3031a0075 100644
--- a/host/docs/usrp2.rst
+++ b/host/docs/usrp2.rst
@@ -101,7 +101,7 @@ On some systems, the firewall will block UDP broadcast packets.
 It is recommended that you change or disable your firewall settings.
 
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-Multiple device configuration
+Multiple devices per host
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 For maximum throughput, one ethernet interface per USRP2 is recommended,
 although multiple devices may be connected via a gigabit ethernet switch.
@@ -210,6 +210,66 @@ Example device address string representation for 2 USRP2s with IPv4 addresses 19
     addr0=192.168.10.2, addr1=192.168.20.2
 
 ------------------------------------------------------------------------
+Using the MIMO Cable
+------------------------------------------------------------------------
+The MIMO cable allows two USRP devices to share reference clocks,
+time synchronization, and the ethernet interface.
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Shared ethernet mode
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+In shared ethernet mode,
+only one device in the configuration can be attached to the ethernet.
+This device will be referred to as the master, and the other device, the slave.
+
+* The master provides reference clock and time synchronization to the slave.
+* All data passing between the host and the slave is routed over the MIMO cable.
+* Both master and slave must have different IPv4 addresses in the same subnet.
+* The master and slave may be used individually or in a multi-device configuration.
+* External clocking is optional, and should only be supplied to the master device.
+* The role of slave and master may be switched with the "mimo_mode" device address (see dual ethernet mode).
+
+Example device address string representation for 2 USRP2s with IPv4 addresses 192.168.10.2 (master) and 192.168.10.3 (slave)
+::
+
+    -- Multi-device example --
+
+    addr0=192.168.10.2, addr1=192.168.10.3
+
+    -- Two single devices example --
+
+    addr=192.168.10.2
+
+    addr=192.168.10.3
+
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Dual ethernet mode
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+In dual ethernet mode,
+both devices in the configuration must be attached to the ethernet.
+One of the devices in the configuration will be configured to provide synchronization.
+This device will be referred to as the master, and the other device, the slave.
+
+* The master provides reference clock and time synchronization to the slave.
+* The devices require the special device address argument "mimo_mode" set.
+* Both master and slave must have different IPv4 addresses in different subnets.
+* The master and slave may be used individually or in a multi-device configuration.
+* External clocking is optional, and should only be supplied to the master device.
+
+Example device address string representation for 2 USRP2s with IPv4 addresses 192.168.10.2 (master) and 192.168.20.2 (slave)
+::
+
+    -- Multi-device example --
+
+    addr0=192.168.10.2, mimo_mode0=master, addr1=192.168.20.2, mimo_mode1=slave
+
+    -- Two single devices example --
+
+    addr=192.168.10.2, mimo_mode=master
+
+    addr=192.168.20.2, mimo_mode=slave
+
+------------------------------------------------------------------------
 Hardware setup notes
 ------------------------------------------------------------------------
 
@@ -220,7 +280,7 @@ The LEDs on the front panel can be useful in debugging hardware and software iss
 The LEDs reveal the following about the state of the device:
 
 * **LED A:** transmitting
-* **LED B:** serdes link
+* **LED B:** mimo cable link
 * **LED C:** receiving
 * **LED D:** firmware loaded
 * **LED E:** reference lock
diff --git a/host/include/uhd/transport/CMakeLists.txt b/host/include/uhd/transport/CMakeLists.txt
index 2c84c0724..ec3b7b113 100644
--- a/host/include/uhd/transport/CMakeLists.txt
+++ b/host/include/uhd/transport/CMakeLists.txt
@@ -17,8 +17,6 @@
 
 
 INSTALL(FILES
-    alignment_buffer.hpp
-    alignment_buffer.ipp
     bounded_buffer.hpp
     bounded_buffer.ipp
     convert_types.hpp
diff --git a/host/include/uhd/transport/alignment_buffer.hpp b/host/include/uhd/transport/alignment_buffer.hpp
deleted file mode 100644
index f44a037f8..000000000
--- a/host/include/uhd/transport/alignment_buffer.hpp
+++ /dev/null
@@ -1,69 +0,0 @@
-//
-// Copyright 2010 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-#ifndef INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_HPP
-#define INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_HPP
-
-#include <uhd/config.hpp>
-#include <uhd/transport/bounded_buffer.hpp> //time_duration_t
-#include <boost/shared_ptr.hpp>
-#include <vector>
-
-namespace uhd{ namespace transport{
-
-    /*!
-     * Implement a templated alignment buffer:
-     * Used for aligning asynchronously pushed elements with matching ids.
-     */
-    template <typename elem_type, typename seq_type> class alignment_buffer{
-    public:
-        typedef boost::shared_ptr<alignment_buffer<elem_type, seq_type> > sptr;
-
-        /*!
-         * Make a new alignment buffer object.
-         * \param capacity the maximum elements per index
-         * \param width the number of elements to align
-         */
-        static sptr make(size_t capacity, size_t width);
-
-        /*!
-         * Push an element with sequence id into the buffer at index.
-         * \param elem the element to push
-         * \param seq the sequence identifier
-         * \param index the buffer index
-         * \return true if the element fit without popping for space
-         */
-        virtual bool push_with_pop_on_full(
-            const elem_type &elem, const seq_type &seq, size_t index
-        ) = 0;
-
-        /*!
-         * Pop an aligned set of elements from this alignment buffer.
-         * \param elems a collection to store the aligned elements
-         * \param timeout the timeout in seconds
-         * \return false when the operation times out
-         */
-        virtual bool pop_elems_with_timed_wait(
-            std::vector<elem_type> &elems, double timeout
-        ) = 0;
-    };
-
-}} //namespace
-
-#include <uhd/transport/alignment_buffer.ipp>
-
-#endif /* INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_HPP */
diff --git a/host/include/uhd/transport/alignment_buffer.ipp b/host/include/uhd/transport/alignment_buffer.ipp
deleted file mode 100644
index 833b5d399..000000000
--- a/host/include/uhd/transport/alignment_buffer.ipp
+++ /dev/null
@@ -1,144 +0,0 @@
-//
-// Copyright 2010 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-#ifndef INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_IPP
-#define INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_IPP
-
-#include <uhd/transport/bounded_buffer.hpp>
-#include <boost/thread/condition_variable.hpp>
-#include <utility>
-
-namespace uhd{ namespace transport{ namespace{ /*anon*/
-
-    /*!
-     * Imlement a templated alignment buffer:
-     * Used for aligning asynchronously pushed elements with matching ids.
-     */
-    template <typename elem_type, typename seq_type>
-    class alignment_buffer_impl : public alignment_buffer<elem_type, seq_type>{
-    public:
-
-        alignment_buffer_impl(size_t capacity, size_t width) : _last_seqs(width){
-            for (size_t i = 0; i < width; i++){
-                _buffs.push_back(bounded_buffer<buff_contents_type>::make(capacity));
-                _all_indexes.push_back(i);
-            }
-            _there_was_a_clear = false;
-        }
-
-        UHD_INLINE bool push_with_pop_on_full(
-            const elem_type &elem, const seq_type &seq, size_t index
-        ){
-            //clear the buffer for this index if the seqs are mis-ordered
-            if (seq < _last_seqs[index]){
-                _buffs[index]->clear();
-                _there_was_a_clear = true;
-            } _last_seqs[index] = seq;
-            return _buffs[index]->push_with_pop_on_full(buff_contents_type(elem, seq));
-        }
-
-        UHD_INLINE bool pop_elems_with_timed_wait(
-            std::vector<elem_type> &elems, double timeout
-        ){
-            boost::system_time exit_time = boost::get_system_time() + to_time_dur(timeout);
-            buff_contents_type buff_contents_tmp;
-            std::list<size_t> indexes_to_do(_all_indexes);
-
-            //do an initial pop to load an initial sequence id
-            size_t index = indexes_to_do.front();
-            if (not _buffs[index]->pop_with_timed_wait(
-                buff_contents_tmp, from_time_dur(exit_time - boost::get_system_time())
-            )) return false;
-            elems[index] = buff_contents_tmp.first;
-            seq_type expected_seq_id = buff_contents_tmp.second;
-            indexes_to_do.pop_front();
-
-            //get an aligned set of elements from the buffers:
-            while(indexes_to_do.size() != 0){
-
-                //respond to a clear by starting from scratch
-                if(_there_was_a_clear){
-                    _there_was_a_clear = false;
-                    indexes_to_do = _all_indexes;
-                    index = indexes_to_do.front();
-                    if (not _buffs[index]->pop_with_timed_wait(
-                        buff_contents_tmp, from_time_dur(exit_time - boost::get_system_time())
-                    )) return false;
-                    elems[index] = buff_contents_tmp.first;
-                    expected_seq_id = buff_contents_tmp.second;
-                    indexes_to_do.pop_front();
-                }
-
-                //pop an element off for this index
-                index = indexes_to_do.front();
-                if (not _buffs[index]->pop_with_timed_wait(
-                    buff_contents_tmp, from_time_dur(exit_time - boost::get_system_time())
-                )) return false;
-
-                //if the sequence id matches:
-                //  store the popped element into the output,
-                //  remove this index from the list and continue
-                if (buff_contents_tmp.second == expected_seq_id){
-                    elems[index] = buff_contents_tmp.first;
-                    indexes_to_do.pop_front();
-                    continue;
-                }
-
-                //if the sequence id is older:
-                //  continue with the same index to try again
-                if (buff_contents_tmp.second < expected_seq_id){
-                    continue;
-                }
-
-                //if the sequence id is newer:
-                //  store the popped element into the output,
-                //  add all other indexes back into the list
-                if (buff_contents_tmp.second > expected_seq_id){
-                    elems[index] = buff_contents_tmp.first;
-                    expected_seq_id = buff_contents_tmp.second;
-                    indexes_to_do = _all_indexes;
-                    indexes_to_do.remove(index);
-                    continue;
-                }
-            }
-            return true;
-        }
-
-    private:
-        //a vector of bounded buffers for each index
-        typedef std::pair<elem_type, seq_type> buff_contents_type;
-        std::vector<typename bounded_buffer<buff_contents_type>::sptr> _buffs;
-        std::vector<seq_type> _last_seqs;
-        std::list<size_t> _all_indexes;
-        bool _there_was_a_clear;
-    };
-
-}}} //namespace
-
-namespace uhd{ namespace transport{
-
-    template <typename elem_type, typename seq_type>
-    typename alignment_buffer<elem_type, seq_type>::sptr
-    alignment_buffer<elem_type, seq_type>::make(size_t capacity, size_t width){
-        return typename alignment_buffer<elem_type, seq_type>::sptr(
-            new alignment_buffer_impl<elem_type, seq_type>(capacity, width)
-        );
-    }
-
-}} //namespace
-
-#endif /* INCLUDED_UHD_TRANSPORT_ALIGNMENT_BUFFER_IPP */
diff --git a/host/include/uhd/transport/bounded_buffer.ipp b/host/include/uhd/transport/bounded_buffer.ipp
index edc7faa06..f7915d866 100644
--- a/host/include/uhd/transport/bounded_buffer.ipp
+++ b/host/include/uhd/transport/bounded_buffer.ipp
@@ -26,14 +26,6 @@
 
 namespace uhd{ namespace transport{ namespace{ /*anon*/
 
-    static UHD_INLINE boost::posix_time::time_duration to_time_dur(double timeout){
-        return boost::posix_time::microseconds(long(timeout*1e6));
-    }
-
-    static UHD_INLINE double from_time_dur(const boost::posix_time::time_duration &time_dur){
-        return 1e-6*time_dur.total_microseconds();
-    }
-
     template <typename elem_type>
     class bounded_buffer_impl : public bounded_buffer<elem_type>{
     public:
@@ -127,6 +119,11 @@ namespace uhd{ namespace transport{ namespace{ /*anon*/
             _buffer.pop_back();
             return elem;
         }
+
+        static UHD_INLINE boost::posix_time::time_duration to_time_dur(double timeout){
+            return boost::posix_time::microseconds(long(timeout*1e6));
+        }
+
     };
 }}} //namespace
 
diff --git a/host/include/uhd/types/clock_config.hpp b/host/include/uhd/types/clock_config.hpp
index 9342fbb7b..5966dcf3a 100644
--- a/host/include/uhd/types/clock_config.hpp
+++ b/host/include/uhd/types/clock_config.hpp
@@ -32,12 +32,10 @@ namespace uhd{
             REF_AUTO = 'a', //automatic (device specific)
             REF_INT  = 'i', //internal reference
             REF_SMA  = 's', //external sma port
-            REF_MIMO = 'm'  //mimo cable (usrp2 only)
         } ref_source;
         enum pps_source_t {
             PPS_INT  = 'i', //there is no internal
             PPS_SMA  = 's', //external sma port
-            PPS_MIMO = 'm'  //mimo cable (usrp2 only)
         } pps_source;
         enum pps_polarity_t {
             PPS_NEG = 'n', //negative edge
diff --git a/host/lib/transport/udp_zero_copy_asio.cpp b/host/lib/transport/udp_zero_copy_asio.cpp
index c758fa894..bbd63836c 100644
--- a/host/lib/transport/udp_zero_copy_asio.cpp
+++ b/host/lib/transport/udp_zero_copy_asio.cpp
@@ -37,14 +37,15 @@ namespace asio = boost::asio;
  **********************************************************************/
 //Define this to the the boost async io calls to perform receive.
 //Otherwise, get_recv_buff uses a blocking receive with timeout.
-//#define USE_ASIO_ASYNC_RECV
+#define USE_ASIO_ASYNC_RECV
 
 //Define this to the the boost async io calls to perform send.
 //Otherwise, the commit callback uses a blocking send.
 //#define USE_ASIO_ASYNC_SEND
 
-//enough buffering for half a second of samples at full rate on usrp2
-static const size_t MIN_RECV_SOCK_BUFF_SIZE = size_t(4 * 25e6 * 0.5);
+//By default, this buffer is sized insufficiently small.
+//For peformance, this buffer should be 10s of megabytes.
+static const size_t MIN_RECV_SOCK_BUFF_SIZE = size_t(10e3);
 
 //Large buffers cause more underflow at high rates.
 //Perhaps this is due to the kernel scheduling,
diff --git a/host/lib/transport/vrt_packet_handler.hpp b/host/lib/transport/vrt_packet_handler.hpp
index 278bcfeaa..7f8d84308 100644
--- a/host/lib/transport/vrt_packet_handler.hpp
+++ b/host/lib/transport/vrt_packet_handler.hpp
@@ -91,6 +91,7 @@ template <typename T> UHD_INLINE T get_context_code(
         //vrt unpack each managed buffer
         uhd::transport::vrt::if_packet_info_t if_packet_info;
         for (size_t i = 0; i < state.width; i++){
+            if (state.managed_buffs[i].get() == NULL) continue; //better have a message packet coming up...
 
             //extract packet words and check thats its enough to move on
             size_t num_packet_words32 = state.managed_buffs[i]->size()/sizeof(boost::uint32_t);
diff --git a/host/lib/usrp/usrp2/CMakeLists.txt b/host/lib/usrp/usrp2/CMakeLists.txt
index 527669852..d83c82063 100644
--- a/host/lib/usrp/usrp2/CMakeLists.txt
+++ b/host/lib/usrp/usrp2/CMakeLists.txt
@@ -38,8 +38,6 @@ IF(ENABLE_USRP2)
         ${CMAKE_CURRENT_SOURCE_DIR}/gps_ctrl.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/io_impl.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/mboard_impl.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/serdes_ctrl.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/serdes_ctrl.hpp
         ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_iface.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_iface.hpp
         ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_impl.cpp
diff --git a/host/lib/usrp/usrp2/clock_ctrl.cpp b/host/lib/usrp/usrp2/clock_ctrl.cpp
index 428d5539b..27ccefb2b 100644
--- a/host/lib/usrp/usrp2/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp2/clock_ctrl.cpp
@@ -22,10 +22,13 @@
 #include <uhd/utils/assert.hpp>
 #include <boost/cstdint.hpp>
 #include <boost/lexical_cast.hpp>
+#include <boost/math/special_functions/round.hpp>
 #include <iostream>
 
 using namespace uhd;
 
+static const bool enb_test_clk = false;
+
 /*!
  * A usrp2 clock control specific to the ad9510 ic.
  */
@@ -66,13 +69,12 @@ public:
         this->enable_external_ref(false);
         this->enable_rx_dboard_clock(false);
         this->enable_tx_dboard_clock(false);
+        this->enable_mimo_clock_out(false);
 
         /* private clock enables, must be set here */
         this->enable_dac_clock(true);
         this->enable_adc_clock(true);
-
-        /* always driving the mimo reference */
-        this->enable_mimo_clock_out(true);
+        this->enable_test_clock(enb_test_clk);
     }
 
     ~usrp2_clock_ctrl_impl(void){
@@ -83,6 +85,7 @@ public:
         this->enable_dac_clock(false);
         this->enable_adc_clock(false);
         this->enable_mimo_clock_out(false);
+        this->enable_test_clock(false);
     }
 
     void enable_mimo_clock_out(bool enb){
@@ -246,6 +249,54 @@ public:
     double get_master_clock_rate(void){
         return 100e6;
     }
+    
+    void set_mimo_clock_delay(double delay) {
+        //delay_val is a 5-bit value (0-31) for fine control
+        //the equations below determine delay for a given ramp current, # of caps and fine delay register
+        //delay range:
+        //range_ns = 200*((caps+3)/i_ramp_ua)*1.3286
+        //offset (zero delay):
+        //offset_ns = 0.34 + (1600 - i_ramp_ua)*1e-4 + ((caps-1)/ramp)*6
+        //delay_ns = offset_ns + range_ns * delay / 31
+
+        int delay_val = boost::math::iround(delay/9.744e-9*31);
+
+        if(delay_val == 0) {
+            switch(clk_regs.exp) {
+            case 5:
+                _ad9510_regs.delay_control_out5 = 1;
+                break;
+            case 6:
+                _ad9510_regs.delay_control_out6 = 1;
+                break;
+            default:
+                break; //delay not supported on U2 rev 3
+            }
+        } else {
+            switch(clk_regs.exp) {
+            case 5:
+                _ad9510_regs.delay_control_out5 = 0;
+                _ad9510_regs.ramp_current_out5 = ad9510_regs_t::RAMP_CURRENT_OUT5_200UA;
+                _ad9510_regs.ramp_capacitor_out5 = ad9510_regs_t::RAMP_CAPACITOR_OUT5_4CAPS;
+                _ad9510_regs.delay_fine_adjust_out5 = delay_val;
+                this->write_reg(0x34);
+                this->write_reg(0x35);
+                this->write_reg(0x36);
+                break;
+            case 6:
+                _ad9510_regs.delay_control_out6 = 0;
+                _ad9510_regs.ramp_current_out6 = ad9510_regs_t::RAMP_CURRENT_OUT6_200UA;
+                _ad9510_regs.ramp_capacitor_out6 = ad9510_regs_t::RAMP_CAPACITOR_OUT6_4CAPS;
+                _ad9510_regs.delay_fine_adjust_out6 = delay_val;
+                this->write_reg(0x38);
+                this->write_reg(0x39);
+                this->write_reg(0x3A);
+                break;
+            default:
+                break;
+            }
+        }
+    }
 
 private:
     /*!
diff --git a/host/lib/usrp/usrp2/clock_ctrl.hpp b/host/lib/usrp/usrp2/clock_ctrl.hpp
index db6c52c83..9ccbc959e 100644
--- a/host/lib/usrp/usrp2/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp2/clock_ctrl.hpp
@@ -91,8 +91,18 @@ public:
     virtual void enable_test_clock(bool enb) = 0;
 
     /*!
-     * TODO other clock control api here....
+     * Enable/disable the ref clock output over the serdes cable.
+     * \param enb true to enable
+     */
+    virtual void enable_mimo_clock_out(bool enb) = 0;
+    
+    /*!
+     * Set the output delay of the mimo clock
+     * Used to synchronise daisy-chained USRPs over the MIMO cable
+     * Can also be used to adjust delay for uneven reference cable lengths
+     * \param delay the clock delay in seconds
      */
+    virtual void set_mimo_clock_delay(double delay) = 0;
 
 };
 
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index a9c39e650..ee7fc3882 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -33,8 +33,8 @@ extern "C" {
 #endif
 
 //fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 3
-#define USRP2_FW_COMPAT_NUM 7
+#define USRP2_FPGA_COMPAT_NUM 4
+#define USRP2_FW_COMPAT_NUM 8
 
 //used to differentiate control packets over data port
 #define USRP2_INVALID_VRT_HEADER 0
@@ -42,7 +42,9 @@ extern "C" {
 // udp ports for the usrp2 communication
 // Dynamic and/or private ports: 49152-65535
 #define USRP2_UDP_CTRL_PORT 49152
-#define USRP2_UDP_DATA_PORT 49153
+//#define USRP2_UDP_UPDATE_PORT 49154
+#define USRP2_UDP_DATA_PORT 49156
+#define USRP2_UDP_ERR0_PORT 49157
 
 ////////////////////////////////////////////////////////////////////////
 // I2C addresses
diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index cbc0a0817..5a6c0983c 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -21,11 +21,13 @@
 #include <uhd/utils/byteswap.hpp>
 #include <uhd/utils/thread_priority.hpp>
 #include <uhd/transport/convert_types.hpp>
-#include <uhd/transport/alignment_buffer.hpp>
+#include <uhd/transport/bounded_buffer.hpp>
 #include <boost/format.hpp>
 #include <boost/bind.hpp>
 #include <boost/thread.hpp>
+#include <boost/date_time/posix_time/posix_time_types.hpp>
 #include <iostream>
+#include <list>
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -108,16 +110,24 @@ private:
  * - vrt packet handler states
  **********************************************************************/
 struct usrp2_impl::io_impl{
-    typedef alignment_buffer<managed_recv_buffer::sptr, time_spec_t> alignment_buffer_type;
 
-    io_impl(size_t num_recv_frames, size_t send_frame_size, size_t width):
+    io_impl(size_t send_frame_size, size_t width):
         packet_handler_recv_state(width),
-        recv_pirate_booty(alignment_buffer_type::make(num_recv_frames-3, width)),
         async_msg_fifo(bounded_buffer<async_metadata_t>::make(100/*messages deep*/))
     {
-        for (size_t i = 0; i < width; i++) fc_mons.push_back(
-            flow_control_monitor::sptr(new flow_control_monitor(usrp2_impl::sram_bytes/send_frame_size))
-        );
+        for (size_t i = 0; i < width; i++){
+            fc_mons.push_back(flow_control_monitor::sptr(
+                new flow_control_monitor(usrp2_impl::sram_bytes/send_frame_size)
+            ));
+            //init empty packet infos
+            vrt::if_packet_info_t packet_info;
+            packet_info.packet_count = 0xf;
+            packet_info.has_tsi = true;
+            packet_info.tsi = 0;
+            packet_info.has_tsf = true;
+            packet_info.tsf = 0;
+            prev_infos.push_back(packet_info);
+        }
     }
 
     ~io_impl(void){
@@ -126,11 +136,6 @@ struct usrp2_impl::io_impl{
         recv_pirate_crew.join_all();
     }
 
-    bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, double timeout){
-        boost::this_thread::disable_interruption di; //disable because the wait can throw
-        return recv_pirate_booty->pop_elems_with_timed_wait(buffs, timeout);
-    }
-
     bool get_send_buffs(
         const std::vector<zero_copy_if::sptr> &trans,
         vrt_packet_handler::managed_send_buffs_t &buffs,
@@ -151,6 +156,15 @@ struct usrp2_impl::io_impl{
         return true;
     }
 
+    bool get_recv_buffs(
+        const std::vector<zero_copy_if::sptr> &xports,
+        vrt_packet_handler::managed_recv_buffs_t &buffs,
+        double timeout
+    );
+
+    //previous state for each buffer
+    std::vector<vrt::if_packet_info_t> prev_infos;
+
     //flow control monitors
     std::vector<flow_control_monitor::sptr> fc_mons;
 
@@ -162,29 +176,28 @@ struct usrp2_impl::io_impl{
     void recv_pirate_loop(zero_copy_if::sptr, usrp2_mboard_impl::sptr, size_t);
     boost::thread_group recv_pirate_crew;
     bool recv_pirate_crew_raiding;
-    alignment_buffer_type::sptr recv_pirate_booty;
     bounded_buffer<async_metadata_t>::sptr async_msg_fifo;
     boost::mutex spawn_mutex;
 };
 
 /***********************************************************************
  * Receive Pirate Loop
- * - while raiding, loot for recv buffers
- * - put booty into the alignment buffer
+ * - while raiding, loot for message packet
+ * - update flow control condition count
+ * - put async message packets into queue
  **********************************************************************/
 void usrp2_impl::io_impl::recv_pirate_loop(
-    zero_copy_if::sptr zc_if,
+    zero_copy_if::sptr zc_if_err0,
     usrp2_mboard_impl::sptr mboard,
     size_t index
 ){
     set_thread_priority_safe();
     recv_pirate_crew_raiding = true;
-    size_t next_packet_seq = 0;
 
     spawn_mutex.unlock();
 
     while(recv_pirate_crew_raiding){
-        managed_recv_buffer::sptr buff = zc_if->get_recv_buff();
+        managed_recv_buffer::sptr buff = zc_if_err0->get_recv_buff();
         if (not buff.get()) continue; //ignore timeout/error buffers
 
         try{
@@ -194,26 +207,6 @@ void usrp2_impl::io_impl::recv_pirate_loop(
             const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
             vrt::if_hdr_unpack_be(vrt_hdr, if_packet_info);
 
-            //handle the rx data stream
-            if (if_packet_info.sid == usrp2_impl::RECV_SID){
-                //handle the packet count / sequence number
-                if (if_packet_info.packet_count != next_packet_seq){
-                    //std::cerr << "S" << (if_packet_info.packet_count - next_packet_seq)%16;
-                    std::cerr << "O" << std::flush; //report overflow (drops in the kernel)
-                }
-                next_packet_seq = (if_packet_info.packet_count+1)%16;
-
-                //extract the timespec and round to the nearest packet
-                UHD_ASSERT_THROW(if_packet_info.has_tsi and if_packet_info.has_tsf);
-                time_spec_t time(
-                    time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), mboard->get_master_clock_freq()
-                );
-
-                //push the packet into the buffer with the new time
-                recv_pirate_booty->push_with_pop_on_full(buff, time, index);
-                continue;
-            }
-
             //handle a tx async report message
             if (if_packet_info.sid == usrp2_impl::ASYNC_SID and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){
 
@@ -253,11 +246,10 @@ void usrp2_impl::io_impl::recv_pirate_loop(
 void usrp2_impl::io_init(void){
 
     //the assumption is that all data transports should be identical
-    const size_t num_recv_frames = _data_transports.front()->get_num_recv_frames();
     const size_t send_frame_size = _data_transports.front()->get_send_frame_size();
 
     //create new io impl
-    _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size()));
+    _io_impl = UHD_PIMPL_MAKE(io_impl, (send_frame_size, _data_transports.size()));
 
     //TODO temporary fix for weird power up state, remove when FPGA fixed
     {
@@ -276,7 +268,7 @@ void usrp2_impl::io_init(void){
         //spawn a new pirate to plunder the recv booty
         _io_impl->recv_pirate_crew.create_thread(boost::bind(
             &usrp2_impl::io_impl::recv_pirate_loop,
-            _io_impl.get(), _data_transports.at(i),
+            _io_impl.get(), _err0_transports.at(i),
             _mboards.at(i), i
         ));
         //block here until the spawned thread unlocks
@@ -328,6 +320,133 @@ size_t usrp2_impl::send(
 }
 
 /***********************************************************************
+ * Alignment logic on receive
+ **********************************************************************/
+static UHD_INLINE boost::posix_time::time_duration to_time_dur(double timeout){
+    return boost::posix_time::microseconds(long(timeout*1e6));
+}
+
+static UHD_INLINE double from_time_dur(const boost::posix_time::time_duration &time_dur){
+    return 1e-6*time_dur.total_microseconds();
+}
+
+static UHD_INLINE time_spec_t extract_time_spec(
+    const vrt::if_packet_info_t &packet_info
+){
+    return time_spec_t( //assumes has_tsi and has_tsf are true
+        time_t(packet_info.tsi), size_t(packet_info.tsf),
+        100e6 //tick rate does not have to be correct for comparison purposes
+    );
+}
+
+static UHD_INLINE void extract_packet_info(
+    managed_recv_buffer::sptr &buff,
+    vrt::if_packet_info_t &prev_info,
+    time_spec_t &time, bool &clear, bool &msg
+){
+    //extract packet info
+    vrt::if_packet_info_t next_info;
+    next_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
+    vrt::if_hdr_unpack_be(buff->cast<const boost::uint32_t *>(), next_info);
+
+    //handle the packet count / sequence number
+    if ((prev_info.packet_count+1)%16 != next_info.packet_count){
+        std::cerr << "O" << std::flush; //report overflow (drops in the kernel)
+    }
+
+    time = extract_time_spec(next_info);
+    clear = extract_time_spec(prev_info) > time;
+    msg = next_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA;
+    prev_info = next_info;
+}
+
+static UHD_INLINE bool handle_msg_packet(
+    vrt_packet_handler::managed_recv_buffs_t &buffs, size_t index
+){
+    for (size_t i = 0; i < buffs.size(); i++){
+        if (i == index) continue;
+        buffs[i].reset(); //set NULL
+    }
+    return true;
+}
+
+UHD_INLINE bool usrp2_impl::io_impl::get_recv_buffs(
+    const std::vector<zero_copy_if::sptr> &xports,
+    vrt_packet_handler::managed_recv_buffs_t &buffs,
+    double timeout
+){
+    if (buffs.size() == 1){
+        buffs[0] = xports[0]->get_recv_buff(timeout);
+        if (buffs[0].get() == NULL) return false;
+        bool clear, msg; time_spec_t time; //unused variables
+        //call extract_packet_info to handle printing the overflows
+        extract_packet_info(buffs[0], this->prev_infos[0], time, clear, msg);
+        return true;
+    }
+    //-------------------- begin alignment logic ---------------------//
+    boost::system_time exit_time = boost::get_system_time() + to_time_dur(timeout);
+    managed_recv_buffer::sptr buff_tmp;
+    std::list<size_t> _all_indexes, indexes_to_do;
+    for (size_t i = 0; i < buffs.size(); i++) _all_indexes.push_back(i);
+    bool clear, msg;
+    time_spec_t expected_time;
+
+    //respond to a clear by starting from scratch
+    got_clear:
+    indexes_to_do = _all_indexes;
+    clear = false;
+
+    //do an initial pop to load an initial sequence id
+    size_t index = indexes_to_do.front();
+    buff_tmp = xports[index]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
+    if (buff_tmp.get() == NULL) return false;
+    extract_packet_info(buff_tmp, this->prev_infos[index], expected_time, clear, msg);
+    if (clear) goto got_clear;
+    buffs[index] = buff_tmp;
+    if (msg) return handle_msg_packet(buffs, index);
+    indexes_to_do.pop_front();
+
+    //get an aligned set of elements from the buffers:
+    while(indexes_to_do.size() != 0){
+
+        //pop an element off for this index
+        index = indexes_to_do.front();
+        buff_tmp = xports[index]->get_recv_buff(from_time_dur(exit_time - boost::get_system_time()));
+        if (buff_tmp.get() == NULL) return false;
+        time_spec_t this_time;
+        extract_packet_info(buff_tmp, this->prev_infos[index], this_time, clear, msg);
+        if (clear) goto got_clear;
+        buffs[index] = buff_tmp;
+        if (msg) return handle_msg_packet(buffs, index);
+
+        //if the sequence id matches:
+        //  remove this index from the list and continue
+        if (this_time == expected_time){
+            indexes_to_do.pop_front();
+            continue;
+        }
+
+        //if the sequence id is older:
+        //  continue with the same index to try again
+        else if (this_time < expected_time){
+            continue;
+        }
+
+        //if the sequence id is newer:
+        //  use the new expected time for comparison
+        //  add all other indexes back into the list
+        else{
+            expected_time = this_time;
+            indexes_to_do = _all_indexes;
+            indexes_to_do.remove(index);
+            continue;
+        }
+    }
+    return true;
+    //-------------------- end alignment logic -----------------------//
+}
+
+/***********************************************************************
  * Receive Data
  **********************************************************************/
 size_t usrp2_impl::get_max_recv_samps_per_packet(void) const{
@@ -357,7 +476,7 @@ size_t usrp2_impl::recv(
         io_type, _rx_otw_type,                     //input and output types to convert
         _mboards.front()->get_master_clock_freq(), //master clock tick rate
         uhd::transport::vrt::if_hdr_unpack_be,
-        boost::bind(&usrp2_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout),
+        boost::bind(&usrp2_impl::io_impl::get_recv_buffs, _io_impl.get(), _data_transports, _1, timeout),
         boost::bind(&handle_overflow, _mboards, _1)
     );
 }
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 766ea993c..4dcc45fd3 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -27,6 +27,10 @@
 #include <iostream>
 #include <boost/date_time/posix_time/posix_time.hpp>
 
+static const double mimo_clock_delay_usrp2_rev4 = 4.18e-9;
+static const double mimo_clock_delay_usrp_n2xx = 0; //TODO
+static const int mimo_clock_sync_delay_cycles = 134;
+
 using namespace uhd;
 using namespace uhd::usrp;
 using namespace boost::posix_time;
@@ -38,8 +42,9 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     size_t index,
     transport::udp_simple::sptr ctrl_transport,
     transport::zero_copy_if::sptr data_transport,
-    size_t recv_samps_per_packet,
-    const device_addr_t &flow_control_hints
+    transport::zero_copy_if::sptr err0_transport,
+    const device_addr_t &device_args,
+    size_t recv_samps_per_packet
 ):
     _index(index),
     _iface(usrp2_iface::make(ctrl_transport))
@@ -47,18 +52,21 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     //Send a small data packet so the usrp2 knows the udp source port.
     //This setup must happen before further initialization occurs
     //or the async update packets will cause ICMP destination unreachable.
-    transport::managed_send_buffer::sptr send_buff = data_transport->get_send_buff();
+    transport::managed_send_buffer::sptr send_buff;
     static const boost::uint32_t data[2] = {
         uhd::htonx(boost::uint32_t(0 /* don't care seq num */)),
         uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER))
     };
+    send_buff = data_transport->get_send_buff();
+    std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
+    send_buff->commit(sizeof(data));
+    send_buff = err0_transport->get_send_buff();
     std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
     send_buff->commit(sizeof(data));
 
     //contruct the interfaces to mboard perifs
     _clock_ctrl = usrp2_clock_ctrl::make(_iface);
     _codec_ctrl = usrp2_codec_ctrl::make(_iface);
-    _serdes_ctrl = usrp2_serdes_ctrl::make(_iface);
     //_gps_ctrl = usrp2_gps_ctrl::make(_iface);
 
     //if(_gps_ctrl->gps_detected()) std::cout << "GPS time: " << _gps_ctrl->get_time() << std::endl;
@@ -98,14 +106,14 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     _iface->poke32(_iface->regs.tx_ctrl_policy, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
 
     //setting the cycles per update (disabled by default)
-    const double ups_per_sec = flow_control_hints.cast<double>("ups_per_sec", 0.0);
+    const double ups_per_sec = device_args.cast<double>("ups_per_sec", 0.0);
     if (ups_per_sec > 0.0){
         const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec);
         _iface->poke32(_iface->regs.tx_ctrl_cycles_per_up, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up);
     }
 
     //setting the packets per update (enabled by default)
-    const double ups_per_fifo = flow_control_hints.cast<double>("ups_per_fifo", 8.0);
+    const double ups_per_fifo = device_args.cast<double>("ups_per_fifo", 8.0);
     if (ups_per_fifo > 0.0){
         const size_t packets_per_up = size_t(usrp2_impl::sram_bytes/ups_per_fifo/data_transport->get_send_frame_size());
         _iface->poke32(_iface->regs.tx_ctrl_packets_per_up, U2_FLAG_TX_CTRL_UP_ENB | packets_per_up);
@@ -118,6 +126,22 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     init_duc_config();
 
     //initialize the clock configuration
+    if (device_args.has_key("mimo_mode")){
+        if (device_args["mimo_mode"] == "master"){
+            _mimo_clocking_mode_is_master = true;
+        }
+        else if (device_args["mimo_mode"] == "slave"){
+            _mimo_clocking_mode_is_master = false;
+        }
+        else throw std::runtime_error(
+            "mimo_mode must be set to master or slave"
+        );
+    }
+    else {
+        _mimo_clocking_mode_is_master = bool(_iface->peek32(_iface->regs.status) & (1 << 8));
+    }
+    std::cout << boost::format("mboard%d MIMO %s") % _index %
+        (_mimo_clocking_mode_is_master?"master":"slave") << std::endl;
     init_clock_config();
 
     //init the codec before the dboard
@@ -155,7 +179,6 @@ void usrp2_mboard_impl::update_clock_config(void){
     //translate pps source enums
     switch(_clock_config.pps_source){
     case clock_config_t::PPS_SMA:  pps_flags |= U2_FLAG_TIME64_PPS_SMA;  break;
-    case clock_config_t::PPS_MIMO: pps_flags |= U2_FLAG_TIME64_PPS_MIMO; break;
     default: throw std::runtime_error("unhandled clock configuration pps source");
     }
 
@@ -176,7 +199,6 @@ void usrp2_mboard_impl::update_clock_config(void){
         switch(_clock_config.ref_source){
         case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x12); break;
         case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break;
-        case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break;
         default: throw std::runtime_error("unhandled clock configuration reference source");
         }
         _clock_ctrl->enable_external_ref(true); //USRP2P has an internal 10MHz TCXO
@@ -187,7 +209,6 @@ void usrp2_mboard_impl::update_clock_config(void){
         switch(_clock_config.ref_source){
         case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break;
         case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break;
-        case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break;
         default: throw std::runtime_error("unhandled clock configuration reference source");
         }
         _clock_ctrl->enable_external_ref(_clock_config.ref_source != clock_config_t::REF_INT);
@@ -195,6 +216,36 @@ void usrp2_mboard_impl::update_clock_config(void){
 
     case usrp2_iface::USRP_NXXX: break;
     }
+
+    //Handle the serdes clocking based on master/slave mode:
+    //   - Masters always drive the clock over serdes.
+    //   - Slaves always lock to this serdes clock.
+    //   - Slaves lock their time over the serdes.
+    if (_mimo_clocking_mode_is_master){
+        _clock_ctrl->enable_mimo_clock_out(true);
+        switch(_iface->get_rev()){
+        case usrp2_iface::USRP_N200:
+        case usrp2_iface::USRP_N210:
+            _clock_ctrl->set_mimo_clock_delay(mimo_clock_delay_usrp_n2xx);
+            break;
+
+        case usrp2_iface::USRP2_REV4:
+            _clock_ctrl->set_mimo_clock_delay(mimo_clock_delay_usrp2_rev4);
+            break;
+
+        default: break; //not handled
+        }
+        _iface->poke32(_iface->regs.time64_mimo_sync, 0);
+    }
+    else{
+        _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15);
+        _clock_ctrl->enable_external_ref(true);
+        _clock_ctrl->enable_mimo_clock_out(false);
+        _iface->poke32(_iface->regs.time64_mimo_sync,
+            (1 << 8) | (mimo_clock_sync_delay_cycles & 0xff)
+        );
+    }
+
 }
 
 void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){
diff --git a/host/lib/usrp/usrp2/serdes_ctrl.cpp b/host/lib/usrp/usrp2/serdes_ctrl.cpp
deleted file mode 100644
index 1cda22f45..000000000
--- a/host/lib/usrp/usrp2/serdes_ctrl.cpp
+++ /dev/null
@@ -1,46 +0,0 @@
-//
-// Copyright 2010 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-#include "serdes_ctrl.hpp"
-#include "usrp2_regs.hpp"
-
-using namespace uhd;
-
-/*!
- * A usrp2 serdes control implementation
- */
-class usrp2_serdes_ctrl_impl : public usrp2_serdes_ctrl{
-public:
-    usrp2_serdes_ctrl_impl(usrp2_iface::sptr iface){
-        _iface = iface;
-        _iface->poke32(_iface->regs.misc_ctrl_serdes, U2_FLAG_MISC_CTRL_SERDES_ENABLE | U2_FLAG_MISC_CTRL_SERDES_RXEN);
-    }
-
-    ~usrp2_serdes_ctrl_impl(void){
-        _iface->poke32(_iface->regs.misc_ctrl_serdes, 0); //power-down
-    }
-
-private:
-    usrp2_iface::sptr _iface;
-};
-
-/***********************************************************************
- * Public make function for the usrp2 serdes control
- **********************************************************************/
-usrp2_serdes_ctrl::sptr usrp2_serdes_ctrl::make(usrp2_iface::sptr iface){
-    return sptr(new usrp2_serdes_ctrl_impl(iface));
-}
diff --git a/host/lib/usrp/usrp2/serdes_ctrl.hpp b/host/lib/usrp/usrp2/serdes_ctrl.hpp
deleted file mode 100644
index 3c909c531..000000000
--- a/host/lib/usrp/usrp2/serdes_ctrl.hpp
+++ /dev/null
@@ -1,40 +0,0 @@
-//
-// Copyright 2010 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-#ifndef INCLUDED_SERDES_CTRL_HPP
-#define INCLUDED_SERDES_CTRL_HPP
-
-#include "usrp2_iface.hpp"
-#include <boost/shared_ptr.hpp>
-#include <boost/utility.hpp>
-
-class usrp2_serdes_ctrl : boost::noncopyable{
-public:
-    typedef boost::shared_ptr<usrp2_serdes_ctrl> sptr;
-
-    /*!
-     * Make a serdes control object for the usrp2 serdes port.
-     * \param _iface a pointer to the usrp2 interface object
-     * \return a new serdes control object
-     */
-    static sptr make(usrp2_iface::sptr iface);
-
-    //TODO fill me in with virtual methods
-
-};
-
-#endif /* INCLUDED_SERDES_CTRL_HPP */
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index c3bbe4d65..f910999d4 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -197,24 +197,36 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
  * Make
  **********************************************************************/
 static device::sptr usrp2_make(const device_addr_t &device_addr){
-sep_indexed_dev_addrs(device_addr);
+
+    //setup the dsp transport hints (default to a large recv buff)
+    device_addr_t dsp_xport_hints = device_addr;
+    if (not dsp_xport_hints.has_key("recv_buff_size")){
+        //set to half-a-second of buffering at max rate
+        dsp_xport_hints["recv_buff_size"] = "50e6";
+    }
+
     //create a ctrl and data transport for each address
     std::vector<udp_simple::sptr> ctrl_transports;
     std::vector<zero_copy_if::sptr> data_transports;
+    std::vector<zero_copy_if::sptr> err0_transports;
+    const device_addrs_t device_addrs = sep_indexed_dev_addrs(device_addr);
 
-    BOOST_FOREACH(const device_addr_t &dev_addr_i, sep_indexed_dev_addrs(device_addr)){
+    BOOST_FOREACH(const device_addr_t &dev_addr_i, device_addrs){
         ctrl_transports.push_back(udp_simple::make_connected(
             dev_addr_i["addr"], num2str(USRP2_UDP_CTRL_PORT)
         ));
         data_transports.push_back(udp_zero_copy::make(
-            dev_addr_i["addr"], num2str(USRP2_UDP_DATA_PORT), device_addr
+            dev_addr_i["addr"], num2str(USRP2_UDP_DATA_PORT), dsp_xport_hints
+        ));
+        err0_transports.push_back(udp_zero_copy::make(
+            dev_addr_i["addr"], num2str(USRP2_UDP_ERR0_PORT), device_addr_t()
         ));
     }
 
     //create the usrp2 implementation guts
-    return device::sptr(
-        new usrp2_impl(ctrl_transports, data_transports, device_addr)
-    );
+    return device::sptr(new usrp2_impl(
+        ctrl_transports, data_transports, err0_transports, device_addrs
+    ));
 }
 
 UHD_STATIC_BLOCK(register_usrp2_device){
@@ -227,9 +239,11 @@ UHD_STATIC_BLOCK(register_usrp2_device){
 usrp2_impl::usrp2_impl(
     std::vector<udp_simple::sptr> ctrl_transports,
     std::vector<zero_copy_if::sptr> data_transports,
-    const device_addr_t &flow_control_hints
+    std::vector<zero_copy_if::sptr> err0_transports,
+    const device_addrs_t &device_args
 ):
-    _data_transports(data_transports)
+    _data_transports(data_transports),
+    _err0_transports(err0_transports)
 {
     //setup rx otw type
     _rx_otw_type.width = 16;
@@ -244,11 +258,11 @@ usrp2_impl::usrp2_impl(
     //!!!!! set the otw type here before continuing, its used below
 
     //create a new mboard handler for each control transport
-    for(size_t i = 0; i < ctrl_transports.size(); i++){
+    for(size_t i = 0; i < device_args.size(); i++){
         _mboards.push_back(usrp2_mboard_impl::sptr(new usrp2_mboard_impl(
             i, ctrl_transports[i], data_transports[i],
-            this->get_max_recv_samps_per_packet(),
-            flow_control_hints
+            err0_transports[i], device_args[i],
+            this->get_max_recv_samps_per_packet()
         )));
         //use an empty name when there is only one mboard
         std::string name = (ctrl_transports.size() > 1)? boost::lexical_cast<std::string>(i) : "";
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index aa8eb0155..9cd27ee41 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -22,7 +22,6 @@
 #include "clock_ctrl.hpp"
 #include "codec_ctrl.hpp"
 #include "gps_ctrl.hpp"
-#include "serdes_ctrl.hpp"
 #include <uhd/device.hpp>
 #include <uhd/utils/pimpl.hpp>
 #include <uhd/types/dict.hpp>
@@ -86,8 +85,9 @@ public:
         size_t index,
         uhd::transport::udp_simple::sptr,
         uhd::transport::zero_copy_if::sptr,
-        size_t recv_samps_per_packet,
-        const uhd::device_addr_t &flow_control_hints
+        uhd::transport::zero_copy_if::sptr,
+        const uhd::device_addr_t &device_args,
+        size_t recv_samps_per_packet
     );
     ~usrp2_mboard_impl(void);
 
@@ -100,12 +100,12 @@ public:
 private:
     size_t _index;
     bool _continuous_streaming;
+    bool _mimo_clocking_mode_is_master;
 
     //interfaces
     usrp2_iface::sptr _iface;
     usrp2_clock_ctrl::sptr _clock_ctrl;
     usrp2_codec_ctrl::sptr _codec_ctrl;
-    usrp2_serdes_ctrl::sptr _serdes_ctrl;
     usrp2_gps_ctrl::sptr _gps_ctrl;
 
     //properties for this mboard
@@ -187,12 +187,14 @@ public:
      * Create a new usrp2 impl base.
      * \param ctrl_transports the udp transports for control
      * \param data_transports the udp transports for data
-     * \param flow_control_hints optional flow control params
+     * \param err0_transports the udp transports for error
+     * \param device_args optional misc device parameters
      */
     usrp2_impl(
         std::vector<uhd::transport::udp_simple::sptr> ctrl_transports,
         std::vector<uhd::transport::zero_copy_if::sptr> data_transports,
-        const uhd::device_addr_t &flow_control_hints
+        std::vector<uhd::transport::zero_copy_if::sptr> err0_transports,
+        const uhd::device_addrs_t &device_args
     );
 
     ~usrp2_impl(void);
@@ -223,6 +225,7 @@ private:
 
     //io impl methods and members
     std::vector<uhd::transport::zero_copy_if::sptr> _data_transports;
+    std::vector<uhd::transport::zero_copy_if::sptr> _err0_transports;
     uhd::otw_type_t _rx_otw_type, _tx_otw_type;
     UHD_PIMPL_DECL(io_impl) _io_impl;
     void io_init(void);
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index dd0433816..82ad30f08 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -57,6 +57,8 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.time64_flags = sr_addr(misc_output_base, x.sr_time64 + 2);
   x.time64_imm = sr_addr(misc_output_base, x.sr_time64 + 3);
   x.time64_tps = sr_addr(misc_output_base, x.sr_time64 + 4);
+  x.time64_mimo_sync = sr_addr(misc_output_base, x.sr_time64 + 5);
+  x.status = bp_base + 4*8;
   x.time64_secs_rb = bp_base + 4*10;
   x.time64_ticks_rb = bp_base + 4*11;
   x.compat_num_rb = bp_base + 4*12;
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 9936d634a..56e64029e 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -25,10 +25,10 @@
 #define USRP2_ATR_BASE          0xE400
 #define USRP2_BP_STATUS_BASE    0xCC00
 
-#define USRP2P_MISC_OUTPUT_BASE 0x2000
-#define USRP2P_GPIO_BASE        0x3200
-#define USRP2P_ATR_BASE         0x3800
-#define USRP2P_BP_STATUS_BASE   0x3300
+#define USRP2P_MISC_OUTPUT_BASE 0x5000
+#define USRP2P_GPIO_BASE        0x6200
+#define USRP2P_ATR_BASE         0x6800
+#define USRP2P_BP_STATUS_BASE   0x6300
 
 typedef struct {
     int sr_misc;
@@ -57,6 +57,8 @@ typedef struct {
     int time64_flags; // flags -- see chart below
     int time64_imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0)
     int time64_tps; // ticks per second rollover count
+    int time64_mimo_sync;
+    int status;
     int time64_secs_rb;
     int time64_ticks_rb;
     int compat_num_rb;
diff --git a/host/test/buffer_test.cpp b/host/test/buffer_test.cpp
index 8445412e7..e7bc88699 100644
--- a/host/test/buffer_test.cpp
+++ b/host/test/buffer_test.cpp
@@ -17,7 +17,6 @@
 
 #include <boost/test/unit_test.hpp>
 #include <uhd/transport/bounded_buffer.hpp>
-#include <uhd/transport/alignment_buffer.hpp>
 #include <boost/assign/list_of.hpp>
 
 using namespace boost::assign;
@@ -63,53 +62,3 @@ BOOST_AUTO_TEST_CASE(test_bounded_buffer_with_pop_on_full){
     BOOST_CHECK(bb->pop_with_timed_wait(val, timeout));
     BOOST_CHECK_EQUAL(val, 3);
 }
-
-BOOST_AUTO_TEST_CASE(test_alignment_buffer){
-    alignment_buffer<int, size_t>::sptr ab(alignment_buffer<int, size_t>::make(7, 3));
-    //load index 0 with all good seq numbers
-    BOOST_CHECK(ab->push_with_pop_on_full(0, 0, 0));
-    BOOST_CHECK(ab->push_with_pop_on_full(1, 1, 0));
-    BOOST_CHECK(ab->push_with_pop_on_full(2, 2, 0));
-    BOOST_CHECK(ab->push_with_pop_on_full(3, 3, 0));
-    BOOST_CHECK(ab->push_with_pop_on_full(4, 4, 0));
-
-    //load index 1 with some skipped seq numbers
-    BOOST_CHECK(ab->push_with_pop_on_full(10, 0, 1));
-    BOOST_CHECK(ab->push_with_pop_on_full(11, 1, 1));
-    BOOST_CHECK(ab->push_with_pop_on_full(14, 4, 1));
-    BOOST_CHECK(ab->push_with_pop_on_full(15, 5, 1));
-    BOOST_CHECK(ab->push_with_pop_on_full(16, 6, 1));
-
-    //load index 2 with all good seq numbers
-    BOOST_CHECK(ab->push_with_pop_on_full(20, 0, 2));
-    BOOST_CHECK(ab->push_with_pop_on_full(21, 1, 2));
-    BOOST_CHECK(ab->push_with_pop_on_full(22, 2, 2));
-    BOOST_CHECK(ab->push_with_pop_on_full(23, 3, 2));
-    BOOST_CHECK(ab->push_with_pop_on_full(24, 4, 2));
-
-    //readback aligned values
-    std::vector<int> aligned_elems(3);
-
-    static const std::vector<int> expected_elems0 = list_of(0)(10)(20);
-    BOOST_CHECK(ab->pop_elems_with_timed_wait(aligned_elems, timeout));
-    BOOST_CHECK_EQUAL_COLLECTIONS(
-        aligned_elems.begin(), aligned_elems.end(),
-        expected_elems0.begin(), expected_elems0.end()
-    );
-
-    static const std::vector<int> expected_elems1 = list_of(1)(11)(21);
-    BOOST_CHECK(ab->pop_elems_with_timed_wait(aligned_elems, timeout));
-    BOOST_CHECK_EQUAL_COLLECTIONS(
-        aligned_elems.begin(), aligned_elems.end(),
-        expected_elems1.begin(), expected_elems1.end()
-    );
-
-    //there was a skip now find 4
-
-    static const std::vector<int> expected_elems4 = list_of(4)(14)(24);
-    BOOST_CHECK(ab->pop_elems_with_timed_wait(aligned_elems, timeout));
-    BOOST_CHECK_EQUAL_COLLECTIONS(
-        aligned_elems.begin(), aligned_elems.end(),
-        expected_elems4.begin(), expected_elems4.end()
-    );
-}
diff --git a/images/Makefile b/images/Makefile
index 27390427d..332379200 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -37,8 +37,8 @@ ifeq ($(shell sdcc --help > /dev/null 2>&1 && echo $$?),0)
 	HAS_SDCC=1
 endif
 
-ifeq ($(shell mb-gcc --help > /dev/null 2>&1 && echo $$?),0)
-	HAS_MB_GCC=1
+ifeq ($(shell zpu-elf-gcc --help > /dev/null 2>&1 && echo $$?),0)
+	HAS_ZPU_GCC=1
 endif
 
 ifeq ($(shell xtclsh -h > /dev/null 2>&1 && echo $$?),0)
@@ -78,22 +78,22 @@ $(_usrp1_fpga_4rx_rbf):
 	cp $(_usrp1_fpga_dir)/std_4rx_0tx.rbf $@
 
 ########################################################################
-# USRP2 and USRP-N2XX firmware
+# USRP2 and N Series firmware
 ########################################################################
-ifdef HAS_MB_GCC
+ifdef HAS_ZPU_GCC
 
-_usrp2_fw_dir = $(TOP_FW_DIR)/microblaze
+_usrp2_fw_dir = $(TOP_FW_DIR)/zpu
 _usrp2_fw_bin = $(BUILT_IMAGES_DIR)/usrp2_fw.bin
 _usrp_n2xx_fw_bin = $(BUILT_IMAGES_DIR)/usrp_n2xx_fw.bin
 IMAGES_LIST += $(_usrp2_fw_bin)
 
 $(_usrp2_fw_bin) $(_usrp_n2xx_fw_bin):
-	cd $(_usrp2_fw_dir) && ./bootstrap
-	cd $(_usrp2_fw_dir) && ./configure --host=mb
-	make -C $(_usrp2_fw_dir) clean
-	make -C $(_usrp2_fw_dir) all
-	cp $(_usrp2_fw_dir)/usrp2/usrp2_txrx_uhd.bin $(_usrp2_fw_bin)
-	cp $(_usrp2_fw_dir)/usrp2p/usrp2p_txrx_uhd.bin $(_usrp_n2xx_fw_bin)
+	cd $(_usrp2_fw_dir) && rm -rf build
+	cd $(_usrp2_fw_dir) && mkdir build
+	cd $(_usrp2_fw_dir)/build && cmake ../
+	cd $(_usrp2_fw_dir)/build && make
+	cp $(_usrp2_fw_dir)/build/usrp2/usrp2_txrx_uhd.bin $(_usrp2_fw_bin)
+	cp $(_usrp2_fw_dir)/build/usrp2p/usrp2p_txrx_uhd.bin $(_usrp_n2xx_fw_bin)
 
 endif