diff options
| -rw-r--r-- | usrp2/gpif/gpif.v | 58 | ||||
| -rw-r--r-- | usrp2/gpif/gpif_rd.v | 19 | ||||
| -rw-r--r-- | usrp2/gpif/gpif_wr.v | 8 |
3 files changed, 47 insertions, 38 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index bcb33eb4d..af698c24a 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -3,7 +3,7 @@ module gpif #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) (// GPIF signals - input gpif_clk, + input gpif_clk, input gpif_rst, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, input [2:0] gpif_misc, @@ -29,23 +29,22 @@ module gpif assign gpif_rdy = { CF, CE, DF, DE }; - wire [15:0] gpif_dat_out; - assign gpif_dat = OE ? gpif_dat_out : 16'bz; + wire [15:0] gpif_d_out; + assign gpif_d = OE ? gpif_d_out : 16'bz; wire [15:0] gpif_d_copy = gpif_d; - - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; - assign debug1 = 32'd0; + + wire [31:0] debug_rd, debug_wr; // //////////////////////////////////////////////////////////////////// // TX Side - wire [18:0] tx19_data; - wire tx19_src_rdy, tx19_dst_rdy; + wire [17:0] tx18_data; + wire tx18_src_rdy, tx18_dst_rdy; wire [35:0] tx36_data; wire tx36_src_rdy, tx36_dst_rdy; - wire [18:0] ctrl; + wire [17:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; gpif_wr gpif_wr @@ -54,13 +53,13 @@ module gpif .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), - .ctrl_o(ctrl), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), - .debug() ); + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), + .debug(debug_wr) ); - fifo19_to_fifo36 #(.LE(1)) f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), + .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 @@ -73,9 +72,9 @@ module gpif wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; - wire [18:0] rx19_data; - wire rx19_src_rdy, rx19_dst_rdy; - wire [18:0] resp_data; + wire [17:0] rx18_data; + wire rx18_src_rdy, rx18_dst_rdy; + wire [17:0] resp_data; wire resp_src_rdy, resp_dst_rdy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -83,20 +82,20 @@ module gpif .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? + fifo36_to_fifo19 #(.LE(1)) f36_to_f18 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); + .f19_dataout(rx18_data), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), - .gpif_data(gpif_dat_out), .gpif_rd(RD), .gpif_ep(EP), + .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), .gpif_empty_d(DE), .gpif_empty_c(CE), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), - .resp_i(resp), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), - .debug() ); + .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), + .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), + .debug(debug_rd) ); // //////////////////////////////////////////////////////////////////// // FIFO to Wishbone interface @@ -110,13 +109,22 @@ module gpif .debug0(), .debug1()); */ + // //////////////////////////////////////////// + // DEBUG + // Loopback for testing - assign resp = ctrl; + assign resp_data = ctrl_data; assign resp_src_rdy = ctrl_src_rdy; - assign ctrl_dst_rdy = resp_src_rdy; + assign ctrl_dst_rdy = resp_dst_rdy; //assign rx_data_i = tx_data_o; //assign rx_src_rdy_i = tx_src_rdy_o; //assign tx_dst_rdy_i = rx_dst_rdy_o; + assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; + assign debug1 = { { debug_rd[15:8] }, + { debug_rd[7:0] }, + { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, resp_src_rdy, resp_dst_rdy}, + { tx_src_rdy_o, tx_dst_rdy_i, tx18_src_rdy, tx18_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 7581592cb..c6e503fce 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -5,13 +5,13 @@ module gpif_rd output reg gpif_empty_d, output reg gpif_empty_c, input sys_clk, input sys_rst, - input [18:0] data_i, input src_rdy_i, output dst_rdy_o, - input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input [17:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, output [31:0] debug ); - wire [17:0] data_o; - wire rx_full; + wire [17:0] data_o, resp_o; + wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix reg [8:0] read_count; @@ -37,7 +37,7 @@ module gpif_rd fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .dataout(data_o), .src_rdy_o(), .dst_rdy_i(send_data_line), .occupied()); + .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); reg [7:0] packet_count; always @(negedge gpif_clk) @@ -62,12 +62,11 @@ module gpif_rd // Response Path wire [15:0] resp_fifolevel; wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - wire [17:0] resp_o; - + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), - .src_rdy_o(), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), + .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), .arst(sys_rst)); // FIXME -- handle short packets @@ -80,5 +79,9 @@ module gpif_rd // Output Mux assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; + + assign debug = { { 16'd0 }, + { data_int[17:16], data_o[17:16], packet_count[3:0] }, + { 2'b0,final_rdy_data, final_rdy_resp, send_data_line, send_resp_line, src_rdy_int, dst_rdy_int} }; endmodule // gpif_rd diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index 4c6ee9efc..813e27290 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -5,8 +5,8 @@ module gpif_wr output reg gpif_full_d, output reg gpif_full_c, input sys_clk, input sys_rst, - output [18:0] data_o, output src_rdy_o, input dst_rdy_i, - output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + output [17:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, output [31:0] debug ); reg wr_reg, ep_reg; @@ -57,8 +57,6 @@ module gpif_wr .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); - assign data_o[18] = 0; - // Control Path wire [15:0] ctrl_fifo_space; always @(posedge gpif_clk) @@ -74,6 +72,6 @@ module gpif_wr .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), .arst(sys_rst)); - assign ctrl_o[18] = 0; + assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]}; endmodule // gpif_wr |