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-rw-r--r--fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm3
-rw-r--r--fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm135
-rw-r--r--fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh9
-rw-r--r--fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh4
-rw-r--r--fpga/usrp3/top/x400/x4xx.v4
-rw-r--r--fpga/usrp3/top/x400/x4xx_gpio_spi.v12
6 files changed, 156 insertions, 11 deletions
diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm
index 0a101710e..d53fc9e3b 100644
--- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm
+++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_left.htm
@@ -281,7 +281,8 @@
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG" onclick="a('DIG_IFC_REGMAP|SPI_SLAVE_CONFIG');">SPI_SLAVE_CONFIG</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG" onclick="a('DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG');">SPI_TRANSACTION_CONFIG</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_TRANSACTION_GO" onclick="a('DIG_IFC_REGMAP|SPI_TRANSACTION_GO');">SPI_TRANSACTION_GO</span></p>
- <p><span class="register" id="a_DIG_IFC_REGMAP|SPI_STATUS" onclick="a('DIG_IFC_REGMAP|SPI_STATUS');">SPI_STATUS</span></p>
+ <p><span class="register" id="a_DIG_IFC_REGMAP|SPI_STATUS" onclick="a('DIG_IFC_REGMAP|SPI_STATUS');">SPI_STATUS</span></p>
+ <p><span class="register" id="a_DIG_IFC_REGMAP|CONTROLLER_INFO" onclick="a('DIG_IFC_REGMAP|CONTROLLER_INFO');">CONTROLLER_INFO</span></p>
</div>
</div>
<p>
diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
index 0d8ec1cb1..ec5c99380 100644
--- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
+++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
@@ -3713,6 +3713,129 @@ Contains the status of the SPI engine.
</div>
+ <div class="register">
+ <a name="DIG_IFC_REGMAP|CONTROLLER_INFO"></a>
+
+<h3 class="register">Offset 0x001C: CONTROLLER_INFO Register (R)</h3>
+
+ <a class="sh_addrs" href="javascript:sa('DIG_IFC_REGMAP|CONTROLLER_INFO_in')">(<span id="show_DIG_IFC_REGMAP|CONTROLLER_INFO_in">show</span> extended info)</a>
+ <div class="sh_addrs" id="div_DIG_IFC_REGMAP|CONTROLLER_INFO_in">
+
+ <table class="extended_info">
+
+<tr>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+ <tr><td class="offset_info" align="right"><a href="#RADIO_CTRLPORT_REGMAP|DIO_WINDOW">RADIO_CTRLPORT_REGMAP|DIO_WINDOW</a></td></tr>
+ <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x00C000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+ <tr><td class="offset_info" align="right"><a href="#RADIO_DIO_REGMAP|DIGITAL_IFC_REGS">RADIO_DIO_REGMAP|DIGITAL_IFC_REGS</a></td></tr>
+ <tr><td class="offset_info" align="right">&nbsp;&nbsp;0x002000</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+ <tr><td class="offset_info" align="right">CONTROLLER_INFO</td></tr>
+ <tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x001C</td></tr>
+</table>
+
+</td>
+
+<td class="outercell" rowspan="1">
+
+<table border="0" cellspacing="0" cellpadding="0">
+
+<tr><td class="offset_info">
+
+
+Total Offset =</td></tr>
+<tr><td class="offset_info">&nbsp;&nbsp;0x00E01C
+
+</td></tr>
+</table>
+
+</td>
+
+</tr>
+
+</table><p/>
+
+<p class="reg_info">Initial Value not specified
+</p>
+
+<p class="reg_info">This register is defined in HDL source file x4xx_gpio_spi.v.</p>
+
+</div>
+
+<div class="info">
+
+Contains information pertaining this SPI controller block.
+
+</div>
+
+ <table class="bitfields" border="0" cellspacing="0" cellpadding="0">
+ <tr class="header"><td class="bits">Bits</td><td>Name</td></tr>
+
+ <tr valign="top">
+ <td class="bits">31..24</td>
+ <td>
+ <p><span class="name">Reserved</span><span class="attr"> </span></p>
+ <p></p>
+
+ </td>
+ </tr>
+
+ <tr class='byte' valign="top">
+ <td class="bits">23..16</td>
+ <td>
+ <p><span class="name">Reserved</span><span class="attr"> </span></p>
+ <p></p>
+
+ </td>
+ </tr>
+
+ <tr class='byte' valign="top">
+ <td class="bits">15..8</td>
+ <td>
+ <p><span class="name">Reserved</span><span class="attr"> </span></p>
+ <p></p>
+
+ </td>
+ </tr>
+
+ <tr class='byte' valign="top">
+ <td class="bits">7..4</td>
+ <td>
+ <p><span class="name">Reserved</span><span class="attr"> </span></p>
+ <p></p>
+
+ </td>
+ </tr>
+
+ <tr valign="top">
+ <td class="bits">3..0</td>
+ <td>
+ <p><span class="name"><a name="DIG_IFC_REGMAP|CONTROLLER_INFO|SLAVE_COUNT"></a>SLAVE_COUNT</span><span class="attr"> </span></p>
+ <p>Indicates the number SPI slaves configurable by the controller.</p>
+
+ </td>
+ </tr>
+
+</table>
+
+</div>
+
</div>
</div>
@@ -24092,12 +24215,12 @@ FPGA version.<BR/>
<tr valign="top">
- <td class='value'>6</td>
+ <td class='value'>7</td>
- <td class='l'>0x00000006</td>
+ <td class='l'>0x00000007</td>
<td class="l" style="text-align: left;">
- <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
+ <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MAJOR'></a>FPGA_CURRENT_VERSION_MAJOR</p>
</td>
@@ -24110,7 +24233,7 @@ FPGA version.<BR/>
<td class='l'>0x00000007</td>
<td class="l" style="text-align: left;">
- <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MAJOR'></a>FPGA_CURRENT_VERSION_MAJOR</p>
+ <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
</td>
@@ -24131,9 +24254,9 @@ FPGA version.<BR/>
<tr valign="top">
- <td class='value'>570565649</td>
+ <td class='value'>570622482</td>
- <td class='l'>0x22022411</td>
+ <td class='l'>0x22030212</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
diff --git a/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh
index bca2c4da8..21ce45360 100644
--- a/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh
+++ b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh
@@ -15,6 +15,7 @@
// SPI_TRANSACTION_CONFIG : 0x10 (x4xx_gpio_spi.v)
// SPI_TRANSACTION_GO : 0x14 (x4xx_gpio_spi.v)
// SPI_STATUS : 0x18 (x4xx_gpio_spi.v)
+ // CONTROLLER_INFO : 0x1C (x4xx_gpio_spi.v)
//===============================================================================
// RegTypes
@@ -82,6 +83,14 @@
localparam SPI_READY_MSB = 24; //SPI_STATUS:SPI_READY
localparam SPI_READY = 24; //SPI_STATUS:SPI_READY
+ // CONTROLLER_INFO Register (from x4xx_gpio_spi.v)
+ localparam CONTROLLER_INFO = 'h1C; // Register Offset
+ localparam CONTROLLER_INFO_SIZE = 32; // register width in bits
+ localparam CONTROLLER_INFO_MASK = 32'hF;
+ localparam SLAVE_COUNT_SIZE = 4; //CONTROLLER_INFO:SLAVE_COUNT
+ localparam SLAVE_COUNT_MSB = 3; //CONTROLLER_INFO:SLAVE_COUNT
+ localparam SLAVE_COUNT = 0; //CONTROLLER_INFO:SLAVE_COUNT
+
// Return the offset of an element of register array SPI_SLAVE_CONFIG
function integer SPI_SLAVE_CONFIG (input integer i);
SPI_SLAVE_CONFIG = (i * 'h4) + 'h0;
diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
index 8928f06f3..84a5dd7b6 100644
--- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
+++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
@@ -82,10 +82,10 @@
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
- localparam FPGA_CURRENT_VERSION_MINOR = 'h6; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
+ localparam FPGA_CURRENT_VERSION_MINOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
- localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22022411; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+ localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22030212; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
diff --git a/fpga/usrp3/top/x400/x4xx.v b/fpga/usrp3/top/x400/x4xx.v
index c16f551d5..07022a3fc 100644
--- a/fpga/usrp3/top/x400/x4xx.v
+++ b/fpga/usrp3/top/x400/x4xx.v
@@ -2284,12 +2284,12 @@ endmodule
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="7"/>
-// <value name="FPGA_CURRENT_VERSION_MINOR" integer="6"/>
+// <value name="FPGA_CURRENT_VERSION_MINOR" integer="7"/>
// <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
-// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x22022411"/>
+// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x22030212"/>
// </enumeratedtype>
// </group>
//</regmap>
diff --git a/fpga/usrp3/top/x400/x4xx_gpio_spi.v b/fpga/usrp3/top/x400/x4xx_gpio_spi.v
index a037ae158..314fda77d 100644
--- a/fpga/usrp3/top/x400/x4xx_gpio_spi.v
+++ b/fpga/usrp3/top/x400/x4xx_gpio_spi.v
@@ -228,6 +228,10 @@ module x4xx_gpio_spi #(
s_ctrlport_resp_data[SPI_RESPONSE_MSB:SPI_RESPONSE] <= readback[SPI_RESPONSE_MSB:SPI_RESPONSE];
end
+ BASE_ADDRESS + CONTROLLER_INFO: begin
+ s_ctrlport_resp_data[SLAVE_COUNT_MSB:SLAVE_COUNT] <= NUM_SLAVES;
+ end
+
// No register implementation for provided address
default: begin
// Acknowledge and provide error status if address is in range
@@ -534,6 +538,14 @@ endmodule
// <info> Records the response of the last completed SPI transaction. </info>
// </bitfield>
// </register>
+// <register name="CONTROLLER_INFO" offset="0x1C" size="32" writable="false">
+// <info>
+// Contains information pertaining this SPI controller block.
+// </info>
+// <bitfield name="SLAVE_COUNT" range="3..0">
+// <info> Indicates the number SPI slaves configurable by the controller. </info>
+// </bitfield>
+// </register>
// </group>
//</regmap>
//XmlParse xml_off
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-10 22:30:49 +0000