diff options
| -rw-r--r-- | usrp2/control_lib/Makefile.srcs | 1 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_readback_mux_16LE.v | 73 | ||||
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 20 |
3 files changed, 90 insertions, 4 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs index d3bb7e2c8..751b40828 100644 --- a/usrp2/control_lib/Makefile.srcs +++ b/usrp2/control_lib/Makefile.srcs @@ -30,6 +30,7 @@ srl.v \ system_control.v \ wb_1master.v \ wb_readback_mux.v \ +wb_readback_mux_16LE.v \ quad_uart.v \ simple_uart.v \ simple_uart_tx.v \ diff --git a/usrp2/control_lib/wb_readback_mux_16LE.v b/usrp2/control_lib/wb_readback_mux_16LE.v new file mode 100644 index 000000000..2b01898c1 --- /dev/null +++ b/usrp2/control_lib/wb_readback_mux_16LE.v @@ -0,0 +1,73 @@ + + +// Note -- clocks must be synchronous (derived from the same source) +// Assumes alt_clk is running at a multiple of wb_clk + +// Note -- assumes that the lower-16 bits will be requested first, +// and that the upper-16 bit request will come immediately after. + +module wb_readback_mux_16LE + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input [15:0] wb_adr_i, + output [15:0] wb_dat_o, + output reg wb_ack_o, + + input [31:0] word00, + input [31:0] word01, + input [31:0] word02, + input [31:0] word03, + input [31:0] word04, + input [31:0] word05, + input [31:0] word06, + input [31:0] word07, + input [31:0] word08, + input [31:0] word09, + input [31:0] word10, + input [31:0] word11, + input [31:0] word12, + input [31:0] word13, + input [31:0] word14, + input [31:0] word15 + ); + + wire ack_next = wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + wb_ack_o <= 0; + else + wb_ack_o <= ack_next; + + reg [31:0] data; + assign wb_dat_o = data[15:0]; + + always @(posedge wb_clk_i) + if (wb_adr_i[1] & ack_next) begin //upper half + data[15:0] <= data[31:16]; + end + else if (~wb_adr_i[1] & ack_next) begin //lower half + case(wb_adr_i[5:2]) + 0 : data <= word00; + 1 : data <= word01; + 2 : data <= word02; + 3 : data <= word03; + 4 : data <= word04; + 5 : data <= word05; + 6 : data <= word06; + 7 : data <= word07; + 8 : data <= word08; + 9 : data <= word09; + 10: data <= word10; + 11: data <= word11; + 12: data <= word12; + 13: data <= word13; + 14: data <= word14; + 15: data <= word15; + endcase // case(wb_adr_i[5:2]) + end + +endmodule // wb_readback_mux + + diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e7e798b34..d590b4fb1 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,13 +36,13 @@ module u1e_core localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - wire [7:0] COMPAT_NUM = 8'd2; + wire [7:0] COMPAT_NUM = 8'd3; wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; wire pps_int; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; wire [7:0] set_addr; @@ -299,7 +299,6 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -427,13 +426,26 @@ module u1e_core .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]),.word03(vita_time_pps[31:0]), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), + .word08(32'b0),.word09(32'b0),.word10(32'b0),.word11(32'b0), + .word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) + ); // ///////////////////////////////////////////////////////////////////////// // VITA Timing time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry |