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-rwxr-xr-xmegacells/fifo_4k_18.v186
-rw-r--r--models/fifo.v3
-rw-r--r--models/fifo_4k_18.v26
-rwxr-xr-xrbf/rev2/std_2rxhb_2tx.rbfbin181070 -> 181358 bytes
-rwxr-xr-xrbf/rev4/std_2rxhb_2tx.rbfbin181070 -> 181358 bytes
-rw-r--r--sdr_lib/tx_buffer.v198
-rw-r--r--toplevel/usrp_std/usrp_std.qsf2
-rw-r--r--toplevel/usrp_std/usrp_std.v18
8 files changed, 339 insertions, 94 deletions
diff --git a/megacells/fifo_4k_18.v b/megacells/fifo_4k_18.v
new file mode 100755
index 000000000..ad76121bb
--- /dev/null
+++ b/megacells/fifo_4k_18.v
@@ -0,0 +1,186 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_4k_18.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4k_18 (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdusedw,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [17:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [17:0] q;
+ output rdempty;
+ output [11:0] rdusedw;
+ output wrfull;
+ output [11:0] wrusedw;
+
+ wire sub_wire0;
+ wire [11:0] sub_wire1;
+ wire sub_wire2;
+ wire [17:0] sub_wire3;
+ wire [11:0] sub_wire4;
+ wire rdempty = sub_wire0;
+ wire [11:0] wrusedw = sub_wire1[11:0];
+ wire wrfull = sub_wire2;
+ wire [17:0] q = sub_wire3[17:0];
+ wire [11:0] rdusedw = sub_wire4[11:0];
+
+ dcfifo dcfifo_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdempty (sub_wire0),
+ .wrusedw (sub_wire1),
+ .wrfull (sub_wire2),
+ .q (sub_wire3),
+ .rdusedw (sub_wire4)
+ // synopsys translate_off
+ ,
+ .rdfull (),
+ .wrempty ()
+ // synopsys translate_on
+ );
+ defparam
+ dcfifo_component.add_ram_output_register = "OFF",
+ dcfifo_component.clocks_are_synchronized = "FALSE",
+ dcfifo_component.intended_device_family = "Cyclone",
+ dcfifo_component.lpm_numwords = 4096,
+ dcfifo_component.lpm_showahead = "ON",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 18,
+ dcfifo_component.lpm_widthu = 12,
+ dcfifo_component.overflow_checking = "OFF",
+ dcfifo_component.underflow_checking = "OFF",
+ dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "18"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "18"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
+// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
+// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/models/fifo.v b/models/fifo.v
index a04e7da6c..0ade49e9c 100644
--- a/models/fifo.v
+++ b/models/fifo.v
@@ -77,5 +77,6 @@ module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
assign rdempty = (rdusedw == 0);
assign rdfull = (rdusedw == depth-1);
-endmodule // fifo_1c_1k
+endmodule // fifo
+
diff --git a/models/fifo_4k_18.v b/models/fifo_4k_18.v
new file mode 100644
index 000000000..3efbf74f0
--- /dev/null
+++ b/models/fifo_4k_18.v
@@ -0,0 +1,26 @@
+
+
+module fifo_4k_18
+ (input [17:0] data,
+ input wrreq,
+ input wrclk,
+ output wrfull,
+ output wrempty,
+ output [11:0] wrusedw,
+
+ output [17:0] q,
+ input rdreq,
+ input rdclk,
+ output rdfull,
+ output rdempty,
+ output [11:0] rdusedw,
+
+ input aclr );
+
+fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k
+ ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+ rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+endmodule // fifo_4k_18
+
+
diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf
index 06d1a33fc..32c931b52 100755
--- a/rbf/rev2/std_2rxhb_2tx.rbf
+++ b/rbf/rev2/std_2rxhb_2tx.rbf
Binary files differ
diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf
index 06d1a33fc..32c931b52 100755
--- a/rbf/rev4/std_2rxhb_2tx.rbf
+++ b/rbf/rev4/std_2rxhb_2tx.rbf
Binary files differ
diff --git a/sdr_lib/tx_buffer.v b/sdr_lib/tx_buffer.v
index 63202c9df..58642229d 100644
--- a/sdr_lib/tx_buffer.v
+++ b/sdr_lib/tx_buffer.v
@@ -24,115 +24,147 @@
// Fifo has 1024 or 2048 lines
module tx_buffer
- ( input usbclk,
+ ( // USB Side
+ input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
- input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
- output wire have_space,
+ output reg have_space,
output reg tx_underrun,
+ input clear_status,
+
+ // DSP Side
+ input txclk,
+ input reset, // standard DSP-side reset
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
- output reg [15:0] tx_i_2,
- output reg [15:0] tx_q_2,
- output reg [15:0] tx_i_3,
- output reg [15:0] tx_q_3,
- input txclk,
input txstrobe,
- input clear_status,
output wire tx_empty,
- output [11:0] debugbus
+ output [31:0] debugbus
);
- wire [11:0] txfifolevel;
- reg [8:0] write_count;
- wire tx_full;
- wire [15:0] fifodata;
- wire rdreq;
-
- reg [3:0] load_next;
-
- // DAC Side of FIFO
- assign rdreq = ((load_next != channels) & !tx_empty);
+ wire [11:0] txfifolevel;
+ wire [15:0] fifodata;
+ wire rdreq;
+ reg [3:0] phase;
+ wire sop_f, iq_f;
+ reg sop;
+
+ // USB Side of FIFO
+ reg [15:0] usbdata_reg;
+ reg wr_reg;
+ reg [8:0] write_count;
+ always @(posedge usbclk)
+ have_space <= (txfifolevel < (4092-256)); // be extra conservative
+
+ always @(posedge usbclk)
+ begin
+ wr_reg <= WR;
+ usbdata_reg <= usbdata;
+ end
+
+ always @(posedge usbclk)
+ if(bus_reset)
+ write_count <= 0;
+ else if(wr_reg)
+ write_count <= write_count + 1;
+ else
+ write_count <= 0;
+
+ always @(posedge usbclk)
+ sop <= WR & ~wr_reg; // Edge detect
+
+ // FIFO
+ fifo_4k_18 txfifo
+ ( // USB Write Side
+ .data ( {sop,write_count[0],usbdata_reg} ),
+ .wrreq ( wr_reg & ~write_count[8] ),
+ .wrclk ( usbclk ),
+ .wrfull ( ),
+ .wrempty ( ),
+ .wrusedw ( txfifolevel ),
+ // DSP Read Side
+ .q ( {sop_f, iq_f, fifodata} ),
+ .rdreq ( rdreq ),
+ .rdclk ( txclk ),
+ .rdfull ( ),
+ .rdempty ( tx_empty ),
+ .rdusedw ( ),
+ // Async, shared
+ .aclr ( reset ) );
+
+ // DAC Side of FIFO
always @(posedge txclk)
if(reset)
begin
- {tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
- <= #1 128'h0;
- load_next <= #1 4'd0;
+ {tx_i_0,tx_q_0,tx_i_1,tx_q_1} <= 64'h0;
+ phase <= 4'd0;
+ end
+ else if(phase == channels)
+ begin
+ if(txstrobe)
+ phase <= 4'd0;
end
else
- if(load_next != channels)
- begin
- load_next <= #1 load_next + 4'd1;
- case(load_next)
- 4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
- 4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
- endcase // case(load_next)
- end // if (load_next != channels)
- else if(txstrobe & (load_next == channels))
+ if(~tx_empty)
begin
- load_next <= #1 4'd0;
+ case(phase)
+ 4'd0 : tx_i_0 <= fifodata;
+ 4'd1 : tx_q_0 <= fifodata;
+ 4'd2 : tx_i_1 <= fifodata;
+ 4'd3 : tx_q_1 <= fifodata;
+ endcase // case(phase)
+ phase <= phase + 4'd1;
end
-
- // USB Side of FIFO
- assign have_space = (txfifolevel <= (4095-256));
+
+ assign rdreq = ((phase != channels) & ~tx_empty);
+
+ // Detect Underruns, cross clock domains
+ reg clear_status_dsp, tx_underrun_dsp;
+ always @(posedge txclk)
+ clear_status_dsp <= clear_status;
always @(posedge usbclk)
- if(bus_reset) // Use bus reset because this is on usbclk
- write_count <= #1 0;
- else if(WR & ~write_count[8])
- write_count <= #1 write_count + 9'd1;
- else
- write_count <= #1 WR ? write_count : 9'b0;
-
- // Detect Underruns
+ tx_underrun <= tx_underrun_dsp;
+
always @(posedge txclk)
if(reset)
- tx_underrun <= 1'b0;
- else if(txstrobe & (load_next != channels))
- tx_underrun <= 1'b1;
- else if(clear_status)
- tx_underrun <= 1'b0;
+ tx_underrun_dsp <= 1'b0;
+ else if(txstrobe & (phase != channels))
+ tx_underrun_dsp <= 1'b1;
+ else if(clear_status_dsp)
+ tx_underrun_dsp <= 1'b0;
- // FIFO
- fifo_4k txfifo
- ( .data ( usbdata ),
- .wrreq ( WR & ~write_count[8] ),
- .wrclk ( usbclk ),
-
- .q ( fifodata ),
- .rdreq ( rdreq ),
- .rdclk ( txclk ),
-
- .aclr ( reset ), // asynch, so we can use either
-
- .rdempty ( tx_empty ),
- .rdusedw ( ),
- .wrfull ( tx_full ),
- .wrusedw ( txfifolevel )
- );
-
- // Debugging Aids
- assign debugbus[0] = WR;
- assign debugbus[1] = have_space;
- assign debugbus[2] = tx_empty;
- assign debugbus[3] = tx_full;
- assign debugbus[4] = tx_underrun;
- assign debugbus[5] = write_count[8];
- assign debugbus[6] = txstrobe;
- assign debugbus[7] = rdreq;
- assign debugbus[11:8] = load_next;
+ // TX debug bus
+ //
+ // 15:0 txclk domain => TXA [15:0]
+ // 31:16 usbclk domain => RXA [15:0]
+ assign debugbus[0] = reset;
+ assign debugbus[1] = txstrobe;
+ assign debugbus[2] = rdreq;
+ assign debugbus[6:3] = phase;
+ assign debugbus[7] = tx_empty;
+ assign debugbus[8] = tx_underrun_dsp;
+ assign debugbus[9] = iq_f;
+ assign debugbus[10] = sop_f;
+ assign debugbus[14:11] = 0;
+ assign debugbus[15] = txclk;
+
+ assign debugbus[16] = bus_reset;
+ assign debugbus[17] = WR;
+ assign debugbus[18] = wr_reg;
+ assign debugbus[19] = have_space;
+ assign debugbus[20] = write_count[8];
+ assign debugbus[21] = write_count[0];
+ assign debugbus[22] = sop;
+ assign debugbus[23] = tx_underrun;
+ assign debugbus[30:24] = 0;
+ assign debugbus[31] = usbclk;
+
endmodule // tx_buffer
diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf
index 269d3c8f8..e0bac4893 100644
--- a/toplevel/usrp_std/usrp_std.qsf
+++ b/toplevel/usrp_std/usrp_std.qsf
@@ -370,6 +370,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
@@ -381,7 +382,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
diff --git a/toplevel/usrp_std/usrp_std.v b/toplevel/usrp_std/usrp_std.v
index 870f43769..4b92cfb16 100644
--- a/toplevel/usrp_std/usrp_std.v
+++ b/toplevel/usrp_std/usrp_std.v
@@ -93,7 +93,8 @@ module usrp_std
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
- wire [15:0] tx_debugbus, rx_debugbus;
+ wire [15:0] rx_debugbus;
+ wire [31:0] tx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
@@ -130,18 +131,17 @@ module usrp_std
assign bb_tx_q1 = ch3tx;
tx_buffer tx_buffer
- ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
- .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
+ ( .usbclk(usbclk), .bus_reset(tx_bus_reset),
+ .usbdata(usbdata),.WR(WR), .have_space(have_space),
+ .tx_underrun(tx_underrun), .clear_status(clear_status),
+ .txclk(clk64), .reset(tx_dsp_reset),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
- .tx_i_2(),.tx_q_2(),
- .tx_i_3(),.tx_q_3(),
- .txclk(clk64),.txstrobe(strobe_interp),
- .clear_status(clear_status),
+ .txstrobe(strobe_interp),
.tx_empty(tx_empty),
.debugbus(tx_debugbus) );
-
+
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
@@ -317,7 +317,7 @@ module usrp_std
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+ .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 15:50:57 +0000