diff options
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 11 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 25 |
2 files changed, 10 insertions, 26 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index b40083201..61c1df04c 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -205,7 +205,7 @@ module u1plus_core .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0), .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1), .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX @@ -297,7 +297,8 @@ module u1plus_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign s5_ack = 0; + assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// @@ -410,10 +411,10 @@ module u1plus_core // only have 64 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); - + // ///////////////////////////////////////////////////////////////////////// // ATR Controller -- Slave #6 @@ -457,7 +458,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry - assign debug_clk = { gpif_clk, clk_fpga }; + assign debug_clk = 2'b00; // { gpif_clk, clk_fpga }; assign debug = 0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 20dd98a36..e1bb50890 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -489,26 +489,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry - assign debug_clk = { EM_CLK, clk_fpga }; - -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, - { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, - { EM_D } }; - -*/ - assign debug = debug_gpmc; - - assign debug_gpio_0 = { {run_tx, 2'b0, strobe_rx0, tx_i[11:0]}, - {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; - - assign debug_gpio_1 = debug_vt; + assign debug_clk = 2'b00; //{ EM_CLK, clk_fpga }; + assign debug = 0; + assign debug_gpio_0 = 0; + assign debug_gpio_1 = 0; -/* - assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, - {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, - {2'b0, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {2'b0, bus_error, debug_gpmc[4:0] }, - {misc_gpio[7:0]} }; - */ endmodule // u1e_core |