diff options
| -rw-r--r-- | fpga/usrp2/top/B100/B100.v | 8 | ||||
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/E1x0.v | 11 | 
3 files changed, 15 insertions, 6 deletions
| diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v index 59bed6066..d26d0a0d0 100644 --- a/fpga/usrp2/top/B100/B100.v +++ b/fpga/usrp2/top/B100/B100.v @@ -147,13 +147,13 @@ module B100     always @(posedge clk_fpga)       if(rxsync_0)         begin -	  rx_i <= rx_b; -	  rx_q <= rx_a; +	  rx_i <= ~rx_b; +	  rx_q <= ~rx_a;         end       else         begin -	  rx_i <= rx_a; -	  rx_q <= rx_b; +	  rx_i <= ~rx_a; +	  rx_q <= ~rx_b;         end     // ///////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index ef0ce51f7..423282153 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -71,7 +71,7 @@ module u1plus_core      localparam SR_GPIO         = 224;     // 5      //compatibility number -> increment when the fpga has been sufficiently altered -    localparam compat_num = {16'd11, 16'd0}; //major, minor +    localparam compat_num = {16'd11, 16'd1}; //major, minor      //assign run signals used for ATR logic      wire [NUM_RX_DSPS-1:0] run_rx_n; diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v index e7b0a4e00..8efb056e9 100644 --- a/fpga/usrp2/top/E1x0/E1x0.v +++ b/fpga/usrp2/top/E1x0/E1x0.v @@ -133,6 +133,15 @@ module E1x0  		.S(1'b0));      // 1-bit set input     // ///////////////////////////////////////////////////////////////////////// +   // RX ADC -- handles inversion + +    reg [11:0] rx_i, rx_q; +    always @(posedge clk_fpga) begin +        rx_i <= ~DA; +        rx_q <= ~DB; +    end + +   // /////////////////////////////////////////////////////////////////////////     // Main Core     wire [35:0] rx_data, tx_data, ctrl_data, resp_data;     wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy; @@ -166,7 +175,7 @@ module E1x0           .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),           .io_tx(io_tx), .io_rx(io_rx),           .tx_i(tx_i), .tx_q(tx_q), -         .rx_i(DA), .rx_q(DB), +         .rx_i(rx_i), .rx_q(rx_q),           .pps_in(PPS_IN) );     // ///////////////////////////////////////////////////////////////////////// | 
