diff options
| -rw-r--r-- | usrp2/top/safe_u1plus/Makefile | 131 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.ucf | 170 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.v | 359 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/u1plus.ucf | 168 |
4 files changed, 185 insertions, 643 deletions
diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile index 2f000df0f..33a2a51c7 100644 --- a/usrp2/top/safe_u1plus/Makefile +++ b/usrp2/top/safe_u1plus/Makefile @@ -37,8 +37,8 @@ export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise # Project Properties ################################################## export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3s1400a \ +family "Spartan3A" \ +device XC3S1400A \ package ft256 \ speed -4 \ top_level_module_type "HDL" \ @@ -53,136 +53,13 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## export SOURCE_ROOT := ../../../ export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/safe_u2plus/u1plus.ucf \ -top/safe_u2plus/safe_u1plus.v +top/safe_u1plus/safe_u1plus.ucf \ +top/safe_u1plus/safe_u1plus.v ################################################## # Process Properties ################################################## export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ diff --git a/usrp2/top/safe_u1plus/safe_u1plus.ucf b/usrp2/top/safe_u1plus/safe_u1plus.ucf new file mode 100644 index 000000000..1a078a9cc --- /dev/null +++ b/usrp2/top/safe_u1plus/safe_u1plus.ucf @@ -0,0 +1,170 @@ +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; +NET "reset_n" LOC = "D5" ; +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + + +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; +#NET "GPIF_D07" LOC = "N12" ; +#NET "GPIF_D06" LOC = "P13" ; +#NET "GPIF_D05" LOC = "P11" ; +#NET "GPIF_RDY3" LOC = "N11" ; +#NET "GPIF_RDY2" LOC = "T10" ; +#NET "GPIF_RDY1" LOC = "T4" ; +#NET "GPIF_RDY0" LOC = "R5" ; +#NET "cgen_st_status" LOC = "P6" ; +#NET "GPIF_CTL3" LOC = "N5" ; +#NET "GPIF_CTL2" LOC = "M11" ; +#NET "GPIF_CTL1" LOC = "M9" ; +#NET "GPIF_CTL0" LOC = "M7" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "T15" ; +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "SDA_FPGA" LOC = "T13" ; +#NET "SCL_FPGA" LOC = "R13" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; +#NET "FX2_PA7_FLAGD" LOC = "P12" ; +#NET "mystery_bus_2" LOC = "T11" ; +#NET "FX2_PA6_PKTEND" LOC = "R11" ; +#NET "FX2_PA2_SLOE" LOC = "P10" ; +#NET "GPIF_D15" LOC = "P7" ; +#NET "GPIF_D14" LOC = "N8" ; +#NET "GPIF_D13" LOC = "T5" ; +#NET "GPIF_D12" LOC = "T6" ; +#NET "GPIF_D11" LOC = "N6" ; +#NET "GPIF_D10" LOC = "P5" ; +#NET "GPIF_D09" LOC = "R3" ; +#NET "GPIF_D08" LOC = "T3" ; +#NET "cgen_ref_sel" LOC = "T2" ; +#NET "GPIF_D04" LOC = "R9" ; +#NET "GPIF_D03" LOC = "T9" ; +#NET "GPIF_D02" LOC = "N9" ; +#NET "GPIF_D01" LOC = "P9" ; +#NET "GPIF_D00" LOC = "P8" ; +#NET "IFCLK" LOC = "T8" ; +#NET "cgen_sync_b" LOC = "H15" ; +#NET "FPGA_TXD" LOC = "H16" ; +#NET "debug_00" LOC = "K16" ; +#NET "debug_01" LOC = "J16" ; +#NET "debug_clk0" LOC = "K15" ; +#NET "debug_clk1" LOC = "K14" ; +#NET "debug_02" LOC = "C16" ; +#NET "debug_03" LOC = "C15" ; +#NET "debug_04" LOC = "E13" ; +#NET "debug_05" LOC = "D14" ; +#NET "debug_06" LOC = "D16" ; +#NET "debug_07" LOC = "D15" ; +#NET "debug_08" LOC = "E14" ; +#NET "debug_09" LOC = "F13" ; +#NET "debug_10" LOC = "G13" ; +#NET "debug_11" LOC = "F14" ; +#NET "debug_12" LOC = "E16" ; +#NET "debug_13" LOC = "F15" ; +#NET "debug_14" LOC = "H13" ; +#NET "debug_15" LOC = "G14" ; +#NET "debug_16" LOC = "G16" ; +#NET "debug_17" LOC = "F16" ; +#NET "debug_18" LOC = "J12" ; +#NET "debug_19" LOC = "J13" ; +#NET "debug_20" LOC = "L14" ; +#NET "debug_21" LOC = "L16" ; +#NET "debug_22" LOC = "M15" ; +#NET "debug_23" LOC = "M16" ; +#NET "debug_24" LOC = "L13" ; +#NET "debug_25" LOC = "K13" ; +#NET "debug_26" LOC = "P16" ; +#NET "debug_27" LOC = "N16" ; +#NET "debug_28" LOC = "R15" ; +#NET "debug_29" LOC = "P15" ; +#NET "debug_30" LOC = "N13" ; +#NET "debug_31" LOC = "N14" ; +#NET "PPS_IN" LOC = "M14" ; +#NET "cgen_st_ld" LOC = "M13" ; +#NET "cgen_st_refmon" LOC = "J14" ; +#NET "FPGA_RXD" LOC = "H12" ; +#NET "DA10" LOC = "A8" ; +#NET "DA09" LOC = "B8" ; +#NET "DA08" LOC = "C8" ; +#NET "DA07" LOC = "D8" ; +#NET "DA06" LOC = "C9" ; +#NET "DA05" LOC = "A9" ; +#NET "DA04" LOC = "C10" ; +#NET "DA03" LOC = "D9" ; +#NET "SCLK_CODEC" LOC = "K3" ; +#NET "TXBLANK" LOC = "K1" ; +#NET "TXSYNC" LOC = "J2" ; +#NET "TX00" LOC = "J1" ; +#NET "TX01" LOC = "H3" ; +#NET "TX02" LOC = "J3" ; +#NET "TX03" LOC = "G2" ; +#NET "TX04" LOC = "H1" ; +#NET "TX05" LOC = "N3" ; +#NET "TX06" LOC = "M4" ; +#NET "TX07" LOC = "R1" ; +#NET "TX08" LOC = "P2" ; +#NET "TX09" LOC = "P1" ; +#NET "TX10" LOC = "M1" ; +#NET "TX11" LOC = "N1" ; +#NET "TX12" LOC = "M3" ; +#NET "TX13" LOC = "L4" ; +#NET "io_tx_00" LOC = "K4" ; +#NET "io_tx_01" LOC = "L3" ; +#NET "io_tx_02" LOC = "L2" ; +#NET "io_tx_03" LOC = "F1" ; +#NET "io_tx_04" LOC = "F3" ; +#NET "io_tx_05" LOC = "G3" ; +#NET "io_tx_06" LOC = "E3" ; +#NET "io_tx_07" LOC = "E2" ; +#NET "io_tx_08" LOC = "E4" ; +#NET "io_tx_09" LOC = "F4" ; +#NET "io_tx_10" LOC = "D1" ; +#NET "io_tx_11" LOC = "E1" ; +#NET "io_tx_12" LOC = "D4" ; +#NET "io_tx_13" LOC = "D3" ; +#NET "io_tx_14" LOC = "C2" ; +#NET "io_tx_15" LOC = "C1" ; +#NET "MISO_AUX" LOC = "J5" ; +#NET "MISO_CODEC" LOC = "G4" ; +#NET "MISO_TX_DB" LOC = "J4" ; +#NET "SEN_TX_DB" LOC = "N2" ; +#NET "MOSI_TX_DB" LOC = "L1" ; +#NET "SCLK_TX_DB" LOC = "G1" ; +#NET "DA02" LOC = "A3" ; +#NET "DA01" LOC = "B3" ; +#NET "DA00" LOC = "A4" ; +#NET "SEN_RX_DB" LOC = "B4" ; +#NET "MOSI_RX_DB" LOC = "A5" ; +#NET "SCLK_RX_DB" LOC = "C5" ; +#NET "io_rx_00" LOC = "D7" ; +#NET "io_rx_01" LOC = "C6" ; +#NET "io_rx_02" LOC = "A6" ; +#NET "io_rx_03" LOC = "B6" ; +#NET "io_rx_04" LOC = "E9" ; +#NET "io_rx_05" LOC = "A7" ; +#NET "io_rx_06" LOC = "C7" ; +#NET "io_rx_07" LOC = "B10" ; +#NET "io_rx_08" LOC = "A10" ; +#NET "io_rx_09" LOC = "C11" ; +#NET "io_rx_10" LOC = "A11" ; +#NET "io_rx_11" LOC = "D11" ; +#NET "io_rx_12" LOC = "B12" ; +#NET "io_rx_13" LOC = "A12" ; +#NET "io_rx_14" LOC = "A14" ; +#NET "io_rx_15" LOC = "A13" ; +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "reset_codec" LOC = "B14" ; +#NET "SEN_CODEC" LOC = "D13" ; +#NET "MOSI_CODEC" LOC = "C13" ; +#NET "MISO_RX_DB" LOC = "E6" ; +#NET "mystery_bus_1" LOC = "C4" ; +#NET "mystery_bus_0" LOC = "E7" ; +#NET "RXSYNC" LOC = "D10" ; +#NET "DA11" LOC = "B15" ; + diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v index 38b276000..108364833 100644 --- a/usrp2/top/safe_u1plus/safe_u1plus.v +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -1,362 +1,25 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, - output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso +module safe_u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, + input reset_n, + output [2:0] debug_led // LED4 is shared w/INIT_B ); - + // FPGA-specific pins connections wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - + reg [31:0] ctr; - + always @(posedge clk_fpga) ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; - - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; + assign debug_led[1:0] = ~ctr[26:25]; - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end + assign debug_led[2] = ~reset_n; - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ -endmodule // safe_u2plus +endmodule // safe_u1plus diff --git a/usrp2/top/safe_u1plus/u1plus.ucf b/usrp2/top/safe_u1plus/u1plus.ucf deleted file mode 100644 index c3b20b76f..000000000 --- a/usrp2/top/safe_u1plus/u1plus.ucf +++ /dev/null @@ -1,168 +0,0 @@ -NET "TMS" LOC = "B2" ; -NET "TDO" LOC = "B16" ; -NET "TDI" LOC = "B1" ; -NET "TCK" LOC = "A15" ; -NET "GPIF_D07" LOC = "N12" ; -NET "GPIF_D06" LOC = "P13" ; -NET "GPIF_D05" LOC = "P11" ; -NET "GPIF_RDY3" LOC = "N11" ; -NET "GPIF_RDY2" LOC = "T10" ; -NET "GPIF_RDY1" LOC = "T4" ; -NET "GPIF_RDY0" LOC = "R5" ; -NET "cgen_st_status" LOC = "P6" ; -NET "GPIF_CTL3" LOC = "N5" ; -NET "GPIF_CTL2" LOC = "M11" ; -NET "GPIF_CTL1" LOC = "M9" ; -NET "GPIF_CTL0" LOC = "M7" ; -NET "fpga_cfg_prog_b" LOC = "A2" ; -NET "fpga_cfg_done" LOC = "T15" ; -NET "reset_n" LOC = "D5" ; -NET "fpga_cfg_din" LOC = "T14" ; -NET "fpga_cfg_cclk" LOC = "R14" ; -NET "SDA_FPGA" LOC = "T13" ; -NET "SCL_FPGA" LOC = "R13" ; -NET "fpga_cfg_init_b" LOC = "T12" ; -NET "FX2_PA7_FLAGD" LOC = "P12" ; -NET "mystery_bus_2" LOC = "T11" ; -NET "FX2_PA6_PKTEND" LOC = "R11" ; -NET "FX2_PA2_SLOE" LOC = "P10" ; -NET "GPIF_D15" LOC = "P7" ; -NET "GPIF_D14" LOC = "N8" ; -NET "GPIF_D13" LOC = "T5" ; -NET "GPIF_D12" LOC = "T6" ; -NET "GPIF_D11" LOC = "N6" ; -NET "GPIF_D10" LOC = "P5" ; -NET "GPIF_D09" LOC = "R3" ; -NET "GPIF_D08" LOC = "T3" ; -NET "debug_led2" LOC = "R2" ; -NET "cgen_ref_sel" LOC = "T2" ; -NET "debug_led1" LOC = "N4" ; -NET "debug_led0" LOC = "P4" ; -NET "GPIF_D04" LOC = "R9" ; -NET "GPIF_D03" LOC = "T9" ; -NET "GPIF_D02" LOC = "N9" ; -NET "GPIF_D01" LOC = "P9" ; -NET "GPIF_D00" LOC = "P8" ; -NET "IFCLK" LOC = "T8" ; -NET "CLK_FPGA_P" LOC = "R7" ; -NET "CLK_FPGA_N" LOC = "T7" ; -NET "cgen_sync_b" LOC = "H15" ; -NET "FPGA_TXD" LOC = "H16" ; -NET "debug_00" LOC = "K16" ; -NET "debug_01" LOC = "J16" ; -NET "debug_clk0" LOC = "K15" ; -NET "debug_clk1" LOC = "K14" ; -NET "debug_02" LOC = "C16" ; -NET "debug_03" LOC = "C15" ; -NET "debug_04" LOC = "E13" ; -NET "debug_05" LOC = "D14" ; -NET "debug_06" LOC = "D16" ; -NET "debug_07" LOC = "D15" ; -NET "debug_08" LOC = "E14" ; -NET "debug_09" LOC = "F13" ; -NET "debug_10" LOC = "G13" ; -NET "debug_11" LOC = "F14" ; -NET "debug_12" LOC = "E16" ; -NET "debug_13" LOC = "F15" ; -NET "debug_14" LOC = "H13" ; -NET "debug_15" LOC = "G14" ; -NET "debug_16" LOC = "G16" ; -NET "debug_17" LOC = "F16" ; -NET "debug_18" LOC = "J12" ; -NET "debug_19" LOC = "J13" ; -NET "debug_20" LOC = "L14" ; -NET "debug_21" LOC = "L16" ; -NET "debug_22" LOC = "M15" ; -NET "debug_23" LOC = "M16" ; -NET "debug_24" LOC = "L13" ; -NET "debug_25" LOC = "K13" ; -NET "debug_26" LOC = "P16" ; -NET "debug_27" LOC = "N16" ; -NET "debug_28" LOC = "R15" ; -NET "debug_29" LOC = "P15" ; -NET "debug_30" LOC = "N13" ; -NET "debug_31" LOC = "N14" ; -NET "PPS_IN" LOC = "M14" ; -NET "cgen_st_ld" LOC = "M13" ; -NET "cgen_st_refmon" LOC = "J14" ; -NET "FPGA_RXD" LOC = "H12" ; -NET "DA10" LOC = "A8" ; -NET "DA09" LOC = "B8" ; -NET "DA08" LOC = "C8" ; -NET "DA07" LOC = "D8" ; -NET "DA06" LOC = "C9" ; -NET "DA05" LOC = "A9" ; -NET "DA04" LOC = "C10" ; -NET "DA03" LOC = "D9" ; -NET "SCLK_CODEC" LOC = "K3" ; -NET "TXBLANK" LOC = "K1" ; -NET "TXSYNC" LOC = "J2" ; -NET "TX00" LOC = "J1" ; -NET "TX01" LOC = "H3" ; -NET "TX02" LOC = "J3" ; -NET "TX03" LOC = "G2" ; -NET "TX04" LOC = "H1" ; -NET "TX05" LOC = "N3" ; -NET "TX06" LOC = "M4" ; -NET "TX07" LOC = "R1" ; -NET "TX08" LOC = "P2" ; -NET "TX09" LOC = "P1" ; -NET "TX10" LOC = "M1" ; -NET "TX11" LOC = "N1" ; -NET "TX12" LOC = "M3" ; -NET "TX13" LOC = "L4" ; -NET "io_tx_00" LOC = "K4" ; -NET "io_tx_01" LOC = "L3" ; -NET "io_tx_02" LOC = "L2" ; -NET "io_tx_03" LOC = "F1" ; -NET "io_tx_04" LOC = "F3" ; -NET "io_tx_05" LOC = "G3" ; -NET "io_tx_06" LOC = "E3" ; -NET "io_tx_07" LOC = "E2" ; -NET "io_tx_08" LOC = "E4" ; -NET "io_tx_09" LOC = "F4" ; -NET "io_tx_10" LOC = "D1" ; -NET "io_tx_11" LOC = "E1" ; -NET "io_tx_12" LOC = "D4" ; -NET "io_tx_13" LOC = "D3" ; -NET "io_tx_14" LOC = "C2" ; -NET "io_tx_15" LOC = "C1" ; -NET "MISO_AUX" LOC = "J5" ; -NET "MISO_CODEC" LOC = "G4" ; -NET "MISO_TX_DB" LOC = "J4" ; -NET "SEN_TX_DB" LOC = "N2" ; -NET "MOSI_TX_DB" LOC = "L1" ; -NET "SCLK_TX_DB" LOC = "G1" ; -NET "DA02" LOC = "A3" ; -NET "DA01" LOC = "B3" ; -NET "DA00" LOC = "A4" ; -NET "SEN_RX_DB" LOC = "B4" ; -NET "MOSI_RX_DB" LOC = "A5" ; -NET "SCLK_RX_DB" LOC = "C5" ; -NET "io_rx_00" LOC = "D7" ; -NET "io_rx_01" LOC = "C6" ; -NET "io_rx_02" LOC = "A6" ; -NET "io_rx_03" LOC = "B6" ; -NET "io_rx_04" LOC = "E9" ; -NET "io_rx_05" LOC = "A7" ; -NET "io_rx_06" LOC = "C7" ; -NET "io_rx_07" LOC = "B10" ; -NET "io_rx_08" LOC = "A10" ; -NET "io_rx_09" LOC = "C11" ; -NET "io_rx_10" LOC = "A11" ; -NET "io_rx_11" LOC = "D11" ; -NET "io_rx_12" LOC = "B12" ; -NET "io_rx_13" LOC = "A12" ; -NET "io_rx_14" LOC = "A14" ; -NET "io_rx_15" LOC = "A13" ; -NET "SEN_AUX" LOC = "C12" ; -NET "SCLK_AUX" LOC = "D12" ; -NET "reset_codec" LOC = "B14" ; -NET "SEN_CODEC" LOC = "D13" ; -NET "MOSI_CODEC" LOC = "C13" ; -NET "MISO_RX_DB" LOC = "E6" ; -NET "mystery_bus_1" LOC = "C4" ; -NET "mystery_bus_0" LOC = "E7" ; -NET "RXSYNC" LOC = "D10" ; -NET "DA11" LOC = "B15" ; - |