diff options
| -rw-r--r-- | usrp2/gpmc/gpmc_async.v | 12 | ||||
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 10 |
2 files changed, 13 insertions, 9 deletions
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 895b68a9f..7d38c66cb 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -25,6 +25,7 @@ module gpmc_async input [15:0] tx_frame_len, output [15:0] rx_frame_len, output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug ); @@ -143,9 +144,10 @@ module gpmc_async wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; wire [31:0] total, crc_err, seq_err, len_err; - wire [7:0] rx_rate, tx_rate; - wire rx_enable, tx_enable; - wire sel_testtx, sel_loopbacktx; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; fifo36_mux rx_test_mux_lvl_1 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), @@ -183,7 +185,7 @@ module gpmc_async // Fixed rate TX traffic consumer fifo_pacer tx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), .underrun(tx_underrun), .overrun()); @@ -200,7 +202,7 @@ module gpmc_async .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); fifo_pacer rx_pacer - (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable), + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), .underrun(), .overrun(rx_overrun)); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c0e92ec6c..174a2a3f8 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -44,6 +44,8 @@ module u1e_core wire pps_int; wire [63:0] vita_time, vita_time_pps; reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; wire [7:0] set_addr; wire [31:0] set_data; @@ -78,7 +80,6 @@ module u1e_core tx_err_src_rdy, tx_err_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; - wire [7:0] rate; wire bus_error; wire clear_tx, clear_rx; @@ -111,6 +112,8 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), .debug(debug_gpmc)); wire rx_sof = rx_data[32]; @@ -285,9 +288,8 @@ module u1e_core xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) - assign tx_enable = xfer_rate[15]; - assign rx_enable = xfer_rate[14]; - assign rate = xfer_rate[7:0]; + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; |