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-rw-r--r--README.txt31
-rw-r--r--usrp2/sdr_lib/ddc_chain.v24
-rw-r--r--usrp2/sdr_lib/duc_chain.v17
-rw-r--r--usrp2/top/USRP2/u2_core.v22
-rw-r--r--usrp2/vrt/vita_rx_chain.v2
-rw-r--r--usrp2/vrt/vita_tx_chain.v2
6 files changed, 66 insertions, 32 deletions
diff --git a/README.txt b/README.txt
new file mode 100644
index 000000000..bfdf317c1
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,31 @@
+########################################################################
+## Welcome to the USRP FPGA source code tree
+########################################################################
+
+usrp1/
+
+ Description: generation 1 products
+
+ Devices: USRP classic only
+
+ Tools: Quartus from Altera
+
+ Project file: usrp1/toplevel/usrp_std/
+
+usrp2/
+
+ Description: generation 2 products
+
+ Devices: USRP2, N2XX, B100, E1XX
+
+ Tools: ISE from Xilinx, GNU make
+
+ Build Instructions:
+ 1) ensure that xtclsh is in the $PATH
+ 2) cd usrp2/top/<project-directory>
+ 3) make -f Makefile.<device> bin
+ 4) bin file in build-<device>/*.bin
+
+ Customize the DSP:
+ Implement design in usrp2/custom/custom_*.v
+ Instructions are included in the module.
diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 7f51d2865..647ec212b 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -18,13 +18,15 @@
//! The USRP digital down-conversion chain
module ddc_chain
- #(parameter BASE = 160)
+ #(parameter BASE = 0, parameter DSPNO = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
- input [23:0] adc_i,
- input [23:0] adc_q,
-
+ // From RX frontend
+ input [23:0] rx_fe_i,
+ input [23:0] rx_fe_q,
+
+ // To RX control
output [31:0] sample,
input run,
output strobe,
@@ -44,7 +46,7 @@ module ddc_chain
wire enable_hb1, enable_hb2;
wire [7:0] cic_decim_rate;
- reg [23:0] adc_i_mux, adc_q_mux;
+ reg [23:0] rx_fe_i_mux, rx_fe_q_mux;
wire realmode;
wire swap_iq;
@@ -71,13 +73,13 @@ module ddc_chain
always @(posedge clk)
if(swap_iq)
begin
- adc_i_mux <= adc_q;
- adc_q_mux <= realmode ? 24'd0 : adc_i;
+ rx_fe_i_mux <= rx_fe_q;
+ rx_fe_q_mux <= realmode ? 24'd0 : rx_fe_i;
end
else
begin
- adc_i_mux <= adc_i;
- adc_q_mux <= realmode ? 24'd0 : adc_q;
+ rx_fe_i_mux <= rx_fe_i;
+ rx_fe_q_mux <= realmode ? 24'd0 : rx_fe_q;
end
// NCO
@@ -92,7 +94,7 @@ module ddc_chain
// CORDIC 24-bit I/O
cordic_z24 #(.bitwidth(25))
cordic(.clock(clk), .reset(rst), .enable(run),
- .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]),
+ .xi({rx_fe_i_mux[23],rx_fe_i_mux}),. yi({rx_fe_q_mux[23],rx_fe_q_mux}), .zi(phase[31:8]),
.xo(i_cordic),.yo(q_cordic),.zo() );
clip_reg #(.bits_in(25), .bits_out(24)) clip_i
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index 248870a69..f1c32a1b2 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -18,14 +18,15 @@
//! The USRP digital up-conversion chain
module duc_chain
- #(parameter BASE=0)
+ #(parameter BASE = 0, parameter DSPNO = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
- output [23:0] dac_i,
- output [23:0] dac_q,
+ // From TX frontend
+ output [23:0] tx_fe_i,
+ output [23:0] tx_fe_q,
- // To tx_control
+ // To TX control
input [31:0] sample,
input run,
output strobe,
@@ -36,7 +37,7 @@ module duc_chain
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
- wire [3:0] dacmux_a, dacmux_b;
+ wire [3:0] tx_femux_a, tx_femux_b;
wire enable_hb1, enable_hb2;
wire rate_change;
@@ -147,8 +148,8 @@ module duc_chain
.R(rst) // Synchronous reset input
);
- assign tx_i = prod_i[28:5];
- assign tx_q = prod_q[28:5];
+ assign tx_fe_i = prod_i[28:5];
+ assign tx_fe_q = prod_q[28:5];
assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index da12371bb..2315b41c7 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -547,14 +547,14 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// ADC Frontend
- wire [23:0] adc_i, adc_q;
+ wire [23:0] rx_fe_i, rx_fe_q;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
.adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
- .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+ .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
// /////////////////////////////////////////////////////////////////////////
// DSP RX 0
@@ -564,10 +564,10 @@ module u2_core
always @(posedge dsp_clk)
run_rx0_d1 <= run_rx0;
- ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0
+ ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_q(adc_q),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
.debug() );
@@ -592,10 +592,10 @@ module u2_core
always @(posedge dsp_clk)
run_rx1_d1 <= run_rx1;
- ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1
+ ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .adc_i(adc_i),.adc_q(adc_q),
+ .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
.sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
.debug() );
@@ -647,7 +647,7 @@ module u2_core
.debug(debug_extfifo),
.debug2(debug_extfifo2) );
- wire [23:0] tx_i, tx_q;
+ wire [23:0] tx_fe_i, tx_fe_q;
wire [31:0] sample_tx;
wire strobe_tx;
@@ -665,17 +665,17 @@ module u2_core
.underrun(underrun), .run(run_tx),
.debug(debug_vt));
- duc_chain #(.BASE(SR_TX_DSP)) duc_chain
+ duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .dac_i(tx_i),.dac_q(tx_q),
+ .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug() );
tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .tx_i(tx_i), .tx_q(tx_q), .run(1'b1),
+ .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
.dac_a(dac_a), .dac_b(dac_b));
// ///////////////////////////////////////////////////////////////////////////////////
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index 332fdce37..13defdbc6 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 5c211c51e..1db16de63 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 11:03:04 +0000