diff options
| -rw-r--r-- | usrp2/gpmc/gpmc.v | 39 | ||||
| -rw-r--r-- | usrp2/gpmc/gpmc_to_fifo.v | 8 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 2 |
3 files changed, 6 insertions, 43 deletions
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 8ecae4daf..a5d4db466 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -49,18 +49,6 @@ module gpmc wire [15:0] EM_D_fifo; wire [15:0] EM_D_wb; - // these registers are used for the GPMC-to-FIFO interface - reg [15:0] em_d_reg; - reg [ADDR_WIDTH:1] em_a_reg; - reg [1:0] em_nbe_reg; - reg em_wait0_reg; - reg em_ncs4_reg; - reg em_ncs6_reg; - reg em_nwe_reg; - reg em_noe_reg; - - - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; // CS4 is RAM_2PORT for DATA PATH (high-speed data) @@ -75,34 +63,9 @@ module gpmc wire [35:0] tx_data, txb_data; wire tx_src_rdy, tx_dst_rdy; wire txb_src_rdy, txb_dst_rdy; - - // Register signals to prevent Sequence errors (S-errors) from occuring - always @(negedge EM_CLK or posedge arst) begin - if (arst) begin - - em_d_reg <= 0; - em_a_reg <= 0; - em_nbe_reg <= 0; - em_wait0_reg <= 0; - em_ncs4_reg <= 0; - em_ncs6_reg <= 0; - em_nwe_reg <= 0; - em_noe_reg <= 0; - end - else begin - em_d_reg <= EM_D; - em_a_reg <= EM_A; - em_nbe_reg <= EM_NBE; - em_wait0_reg <= EM_WAIT0; - em_ncs4_reg <= EM_NCS4; - em_ncs6_reg <= EM_NCS6; - em_nwe_reg <= EM_NWE; - em_noe_reg <= EM_NOE; - end - end gpmc_to_fifo #(.ADDR_WIDTH(ADDR_WIDTH)) gpmc_to_fifo - (.EM_D(em_d_reg), .EM_A(em_a_reg), .EM_CLK(EM_CLK), .EM_WE(~em_ncs4_reg & ~em_nwe_reg), + (.EM_D(EM_D), .EM_A(EM_A), .EM_CLK(EM_CLK), .EM_WE(~EM_NCS4 & ~EM_NWE), .clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .arst(fifo_rst | clear_tx | arst), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), .have_space(tx_have_space)); diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v index 4aa55953a..cfc5aaa8b 100644 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -70,9 +70,9 @@ module gpmc_to_fifo case(gpmc_state) GPMC_STATE_START: begin - if (EM_A == 0) begin + if (EM_A == 2) begin gpmc_state <= GPMC_STATE_FILL; - last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1; + last_addr <= {EM_D[ADDR_WIDTH-2:0], 1'b0} - 1'b1 + 2; next_gpmc_ptr <= gpmc_ptr + 1; end end @@ -116,14 +116,14 @@ module gpmc_to_fifo if (reset | clear) begin fifo_state <= FIFO_STATE_CLAIM; fifo_ptr <= 0; - counter <= 0; + counter <= 2; end else begin case(fifo_state) FIFO_STATE_CLAIM: begin if (bram_available_to_empty) fifo_state <= FIFO_STATE_EMPTY; - counter <= 0; + counter <= 2; end FIFO_STATE_EMPTY: begin diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 77be1bfb0..fef988e62 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd10, 16'd1}; //major, minor + localparam compat_num = {16'd10, 16'd2}; //major, minor wire [31:0] reg_test32; |