diff options
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus_core.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 2 | ||||
| -rw-r--r-- | host/lib/usrp/cores/rx_dsp_core_200.cpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/multi_usrp.cpp | 4 |
7 files changed, 10 insertions, 12 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 09b7e11f1..c1d6767d1 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd2}; //major, minor + localparam compat_num = {16'd9, 16'd3}; //major, minor wire [31:0] reg_test32; diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index ee27af939..a98e1de34 100644 --- a/fpga/usrp2/top/E1x0/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -454,7 +454,7 @@ module u1e_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd9, 16'd1}; //major, minor wire [31:0] reg_test32; diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index 369f01183..abc32406e 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -436,8 +436,8 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor - wire [31:0] churn = status; //tweak churn until timing meets! + localparam compat_num = {16'd9, 16'd1}; //major, minor + wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index 6bf60fe58..93064254f 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -442,7 +442,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd0}; //major, minor + localparam compat_num = {16'd9, 16'd1}; //major, minor wire [31:0] churn = 0; //tweak churn until timing meets! wb_readback_mux buff_pool_status diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index 4b60f111c..cf8db1927 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -38,13 +38,12 @@ #define REG_RX_CTRL_STREAM_CMD _ctrl_base + 0 #define REG_RX_CTRL_TIME_HI _ctrl_base + 4 #define REG_RX_CTRL_TIME_LO _ctrl_base + 8 -#define REG_RX_CTRL_CLEAR _ctrl_base + 12 +#define REG_RX_CTRL_FORMAT _ctrl_base + 12 #define REG_RX_CTRL_VRT_HDR _ctrl_base + 16 #define REG_RX_CTRL_VRT_SID _ctrl_base + 20 #define REG_RX_CTRL_VRT_TLR _ctrl_base + 24 #define REG_RX_CTRL_NSAMPS_PP _ctrl_base + 28 #define REG_RX_CTRL_NCHANNELS _ctrl_base + 32 -#define REG_RX_CTRL_FORMAT REG_RX_CTRL_CLEAR //re-use clear address template <class T> T ceil_log2(T num){ return std::ceil(std::log(num)/std::log(T(2))); @@ -78,8 +77,7 @@ public: } void clear(void){ - _iface->poke32(REG_RX_CTRL_CLEAR, 1); //reset - _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); + _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); //also reset _iface->poke32(REG_RX_CTRL_VRT_HDR, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer diff --git a/host/lib/usrp/multi_usrp.cpp b/host/lib/usrp/multi_usrp.cpp index c6ff9d437..39f9cb490 100644 --- a/host/lib/usrp/multi_usrp.cpp +++ b/host/lib/usrp/multi_usrp.cpp @@ -425,8 +425,8 @@ public: std::string clock_source; switch(clock_config.ref_source){ case clock_config_t::REF_INT: clock_source = "internal"; break; - case clock_config_t::PPS_SMA: clock_source = "external"; break; - case clock_config_t::PPS_MIMO: clock_source = "mimo"; break; + case clock_config_t::REF_SMA: clock_source = "external"; break; + case clock_config_t::REF_MIMO: clock_source = "mimo"; break; default: clock_source = "unknown"; } this->set_clock_source(clock_source, mboard); |