diff options
| -rw-r--r-- | usrp2/fifo/fifo36_mux.v | 3 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 6 |
2 files changed, 4 insertions, 5 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 2b454abaf..7f0f803ff 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -74,5 +74,4 @@ module fifo36_mux (.clk(clk), .reset(reset), .clear(clear), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); - -endmodule // fifo36_mux +endmodule // fifo36_demux diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 73d9b87fd..4c0cef50d 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -191,9 +191,9 @@ module vita_rx_control assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & not_empty_ctrl; - assign debug_rx = { { 8'd0 }, + assign debug_rx = { { ibs_state[2:0], command_queue_len }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, overrun, ~not_empty_ctrl }, - { ibs_state[2:0], chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, + { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // vita_rx_control |