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-rw-r--r--usrp2/fifo/Makefile.srcs1
-rw-r--r--usrp2/fifo/fifo19_mux.v77
-rw-r--r--usrp2/fifo/fifo36_mux.v3
-rw-r--r--usrp2/gpif/gpif.v26
-rw-r--r--usrp2/top/u1plus/u1plus_core.v17
5 files changed, 106 insertions, 18 deletions
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index 7e6a231ae..02c567049 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -23,6 +23,7 @@ fifo19_to_ll8.v \
ll8_to_fifo19.v \
fifo36_to_fifo19.v \
fifo19_to_fifo36.v \
+fifo19_mux.v \
fifo36_mux.v \
fifo36_demux.v \
packet_router.v \
diff --git a/usrp2/fifo/fifo19_mux.v b/usrp2/fifo/fifo19_mux.v
new file mode 100644
index 000000000..ebf961678
--- /dev/null
+++ b/usrp2/fifo/fifo19_mux.v
@@ -0,0 +1,77 @@
+
+// Mux packets from multiple FIFO interfaces onto a single one.
+// Can alternate or give priority to one port (port 0)
+// In prio mode, port 1 will never get access if port 0 is always busy
+
+module fifo19_mux
+ #(parameter prio = 0)
+ (input clk, input reset, input clear,
+ input [18:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+ input [18:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+ output [18:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ wire [18:0] data0_int, data1_int;
+ wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
+
+ fifo_short #(.WIDTH(19)) mux_fifo_in0
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o),
+ .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
+
+ fifo_short #(.WIDTH(19)) mux_fifo_in1
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o),
+ .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
+
+ localparam MUX_IDLE0 = 0;
+ localparam MUX_DATA0 = 1;
+ localparam MUX_IDLE1 = 2;
+ localparam MUX_DATA1 = 3;
+
+ reg [1:0] state;
+
+ wire eof0 = data0_int[17];
+ wire eof1 = data1_int[17];
+
+ wire [18:0] data_int;
+ wire src_rdy_int, dst_rdy_int;
+
+ always @(posedge clk)
+ if(reset | clear)
+ state <= MUX_IDLE0;
+ else
+ case(state)
+ MUX_IDLE0 :
+ if(src0_rdy_int)
+ state <= MUX_DATA0;
+ else if(src1_rdy_int)
+ state <= MUX_DATA1;
+
+ MUX_DATA0 :
+ if(src0_rdy_int & dst_rdy_int & eof0)
+ state <= prio ? MUX_IDLE0 : MUX_IDLE1;
+
+ MUX_IDLE1 :
+ if(src1_rdy_int)
+ state <= MUX_DATA1;
+ else if(src0_rdy_int)
+ state <= MUX_DATA0;
+
+ MUX_DATA1 :
+ if(src1_rdy_int & dst_rdy_int & eof1)
+ state <= MUX_IDLE0;
+
+ default :
+ state <= MUX_IDLE0;
+ endcase // case (state)
+
+ assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
+ assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
+ assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
+ assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
+
+ fifo_short #(.WIDTH(19)) mux_fifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+ .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+endmodule // fifo19_mux
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index 7f0f803ff..2b454abaf 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -74,4 +74,5 @@ module fifo36_mux
(.clk(clk), .reset(reset), .clear(clear),
.datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
.dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
-endmodule // fifo36_demux
+
+endmodule // fifo36_mux
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index e72490b17..8cac8b466 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -17,7 +17,8 @@ module gpif
input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-
+ input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
+
output tx_underrun, output rx_overrun,
input [7:0] test_rate, input [3:0] test_ctrl,
output [31:0] debug0, output [31:0] debug1
@@ -77,8 +78,9 @@ module gpif
wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
wire [18:0] rx19_data;
wire rx19_src_rdy, rx19_dst_rdy;
- wire [18:0] resp_data, resp_int;
- wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int;
+ wire [18:0] resp_data, resp_int1, resp_int2;
+ wire resp_src_rdy, resp_dst_rdy;
+ wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
@@ -106,15 +108,29 @@ module gpif
fifo_to_wb fifo_to_wb
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
- .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
+ .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1),
.wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o),
.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
.triggers(triggers),
.debug0(), .debug1());
+ wire [18:0] tx_err19_data;
+ wire tx_err19_src_rdy, tx_err19_dst_rdy;
+
+ fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o),
+ .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) );
+
+ fifo19_mux #(.prio(0)) mux_err_stream
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1),
+ .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy),
+ .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2));
+
fifo19_pad #(.LENGTH(16)) fifo19_pad
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int),
+ .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2),
.data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
// ////////////////////////////////////////////////////////////////////
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index 75845e8f4..5b10b3260 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -104,7 +104,8 @@ module u1plus_core
.fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
.tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
.rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-
+ .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy),
+
.tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
.test_rate(test_rate), .test_ctrl(test_ctrl),
@@ -123,8 +124,6 @@ module u1plus_core
wire rx1_dst_rdy, rx1_src_rdy;
wire [100:0] rx1_data;
wire run_rx;
- wire [35:0] vita_rx_data;
- wire vita_rx_src_rdy, vita_rx_dst_rdy;
dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
(.clk(wb_clk),.rst(wb_rst),
@@ -145,15 +144,9 @@ module u1plus_core
(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
- .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
+ .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy),
.debug_rx(vrf_debug) );
- fifo36_mux #(.prio(0)) mux_err_stream
- (.clk(wb_clk), .reset(wb_rst), .clear(0),
- .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy),
- .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
- .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
@@ -161,8 +154,8 @@ module u1plus_core
wire run_tx;
vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
- .REPORT_ERROR(0), .DO_FLOW_CONTROL(0),
- .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
+ .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
+ .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
vita_tx_chain
(.clk(wb_clk), .reset(wb_rst),
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 03:39:31 +0000