diff options
| -rw-r--r-- | usrp2/top/safe_u1plus/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/Makefile | 245 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/safe_u1plus.v | 362 | ||||
| -rw-r--r-- | usrp2/top/safe_u1plus/u1plus.ucf | 168 | ||||
| -rw-r--r-- | usrp2/top/u1_core/.gitignore | 44 | ||||
| -rwxr-xr-x | usrp2/top/u1_core/u1_core.v | 455 | ||||
| -rw-r--r-- | usrp2/top/u1plus/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/top/u1plus/Makefile | 232 | ||||
| -rw-r--r-- | usrp2/top/u1plus/timing.ucf | 2 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus.ucf | 203 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus.v | 141 |
11 files changed, 1854 insertions, 0 deletions
diff --git a/usrp2/top/safe_u1plus/.gitignore b/usrp2/top/safe_u1plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/safe_u1plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/safe_u1plus/Makefile b/usrp2/top/safe_u1plus/Makefile new file mode 100644 index 000000000..2f000df0f --- /dev/null +++ b/usrp2/top/safe_u1plus/Makefile @@ -0,0 +1,245 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3s1400a \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/safe_u2plus/u1plus.ucf \ +top/safe_u2plus/safe_u1plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/safe_u1plus/safe_u1plus.v b/usrp2/top/safe_u1plus/safe_u1plus.v new file mode 100644 index 000000000..38b276000 --- /dev/null +++ b/usrp2/top/safe_u1plus/safe_u1plus.v @@ -0,0 +1,362 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + //input ADC_clkout_p, //input ADC_clkout_n, + //input ADCA_12_p, //input ADCA_12_n, + //input ADCA_10_p, //input ADCA_10_n, + //input ADCA_8_p, //input ADCA_8_n, + //input ADCA_6_p, //input ADCA_6_n, + //input ADCA_4_p, //input ADCA_4_n, + //input ADCA_2_p, //input ADCA_2_n, + //input ADCA_0_p, //input ADCA_0_n, + //input ADCB_12_p, //input ADCB_12_n, + //input ADCB_10_p, //input ADCB_10_n, + //input ADCB_8_p, //input ADCB_8_n, + //input ADCB_6_p, //input ADCB_6_n, + //input ADCB_4_p, //input ADCB_4_n, + //input ADCB_2_p, //input ADCB_2_n, + //input ADCB_0_p, //input ADCB_0_n, + + // DAC + //output [15:0] DACA, + //output [15:0] DACB, + //input DAC_LOCK, // unused for now + + // DB IO Pins + //inout [15:0] io_tx, + //inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + //input FPGA_RESET, + //output [1:0] debug_clk, + //output [31:0] debug, + //output [3:1] TXD, //input [3:1] RXD, // UARTs + ////input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + //output [1:0] clk_en, + //output [1:0] clk_sel, + //input CLK_FUNC, // FIXME is an //input to control the 9510 + //input CLK_STATUS, + + //inout SCL, //inout SDA, // I2C + + // PPS + //input PPS_IN, //input PPS2_IN, + + // SPI + //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, + //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, + //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, + //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, + //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, + //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, + //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, + //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, + //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, + + // GigE PHY + //input CLK_TO_MAC, + + //output reg [7:0] GMII_TXD, + //output reg GMII_TX_EN, + //output reg GMII_TX_ER, + //output GMII_GTX_CLK, + //input GMII_TX_CLK, // 100mbps clk + + //input GMII_RX_CLK, + //input [7:0] GMII_RXD, + //input GMII_RX_DV, + //input GMII_RX_ER, + //input GMII_COL, + //input GMII_CRS, + + //input PHY_INTn, // open drain + //inout MDIO, + //output MDC, + //output PHY_RESETn, + output ETH_LED + + //input POR, + + // Expansion + //input exp_time_in_p, //input exp_time_in_n, // Diff + //output exp_time_out_p, //output exp_time_out_n, // Diff + //input exp_user_in_p, //input exp_user_in_n, // Diff + //output exp_user_out_p, //output exp_user_out_n, // Diff + + // SERDES + //output ser_enable, + //output ser_prbsen, + //output ser_loopen, + //output ser_rx_en, + + //output ser_tx_clk, + //output reg [15:0] ser_t, + //output reg ser_tklsb, + //output reg ser_tkmsb, + + //input ser_rx_clk, + //input [15:0] ser_r, + //input ser_rklsb, + //input ser_rkmsb, + + // SRAM + //inout [35:0] RAM_D, + //output [20:0] RAM_A, + //output [3:0] RAM_BWn, + //output RAM_ZZ, + //output RAM_LDn, + //output RAM_OEn, + //output RAM_WEn, + //output RAM_CENn, + //output RAM_CLK, + + // SPI Flash + //output flash_cs, + //output flash_clk, + //output flash_mosi, + //input flash_miso + ); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + + +/* + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire dcm_rst = 0; + + wire [13:0] adc_a, adc_b; + + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); +*/ +endmodule // safe_u2plus diff --git a/usrp2/top/safe_u1plus/u1plus.ucf b/usrp2/top/safe_u1plus/u1plus.ucf new file mode 100644 index 000000000..c3b20b76f --- /dev/null +++ b/usrp2/top/safe_u1plus/u1plus.ucf @@ -0,0 +1,168 @@ +NET "TMS" LOC = "B2" ; +NET "TDO" LOC = "B16" ; +NET "TDI" LOC = "B1" ; +NET "TCK" LOC = "A15" ; +NET "GPIF_D07" LOC = "N12" ; +NET "GPIF_D06" LOC = "P13" ; +NET "GPIF_D05" LOC = "P11" ; +NET "GPIF_RDY3" LOC = "N11" ; +NET "GPIF_RDY2" LOC = "T10" ; +NET "GPIF_RDY1" LOC = "T4" ; +NET "GPIF_RDY0" LOC = "R5" ; +NET "cgen_st_status" LOC = "P6" ; +NET "GPIF_CTL3" LOC = "N5" ; +NET "GPIF_CTL2" LOC = "M11" ; +NET "GPIF_CTL1" LOC = "M9" ; +NET "GPIF_CTL0" LOC = "M7" ; +NET "fpga_cfg_prog_b" LOC = "A2" ; +NET "fpga_cfg_done" LOC = "T15" ; +NET "reset_n" LOC = "D5" ; +NET "fpga_cfg_din" LOC = "T14" ; +NET "fpga_cfg_cclk" LOC = "R14" ; +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; +NET "fpga_cfg_init_b" LOC = "T12" ; +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "mystery_bus_2" LOC = "T11" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; +NET "GPIF_D15" LOC = "P7" ; +NET "GPIF_D14" LOC = "N8" ; +NET "GPIF_D13" LOC = "T5" ; +NET "GPIF_D12" LOC = "T6" ; +NET "GPIF_D11" LOC = "N6" ; +NET "GPIF_D10" LOC = "P5" ; +NET "GPIF_D09" LOC = "R3" ; +NET "GPIF_D08" LOC = "T3" ; +NET "debug_led2" LOC = "R2" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "debug_led1" LOC = "N4" ; +NET "debug_led0" LOC = "P4" ; +NET "GPIF_D04" LOC = "R9" ; +NET "GPIF_D03" LOC = "T9" ; +NET "GPIF_D02" LOC = "N9" ; +NET "GPIF_D01" LOC = "P9" ; +NET "GPIF_D00" LOC = "P8" ; +NET "IFCLK" LOC = "T8" ; +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; +NET "cgen_sync_b" LOC = "H15" ; +NET "FPGA_TXD" LOC = "H16" ; +NET "debug_00" LOC = "K16" ; +NET "debug_01" LOC = "J16" ; +NET "debug_clk0" LOC = "K15" ; +NET "debug_clk1" LOC = "K14" ; +NET "debug_02" LOC = "C16" ; +NET "debug_03" LOC = "C15" ; +NET "debug_04" LOC = "E13" ; +NET "debug_05" LOC = "D14" ; +NET "debug_06" LOC = "D16" ; +NET "debug_07" LOC = "D15" ; +NET "debug_08" LOC = "E14" ; +NET "debug_09" LOC = "F13" ; +NET "debug_10" LOC = "G13" ; +NET "debug_11" LOC = "F14" ; +NET "debug_12" LOC = "E16" ; +NET "debug_13" LOC = "F15" ; +NET "debug_14" LOC = "H13" ; +NET "debug_15" LOC = "G14" ; +NET "debug_16" LOC = "G16" ; +NET "debug_17" LOC = "F16" ; +NET "debug_18" LOC = "J12" ; +NET "debug_19" LOC = "J13" ; +NET "debug_20" LOC = "L14" ; +NET "debug_21" LOC = "L16" ; +NET "debug_22" LOC = "M15" ; +NET "debug_23" LOC = "M16" ; +NET "debug_24" LOC = "L13" ; +NET "debug_25" LOC = "K13" ; +NET "debug_26" LOC = "P16" ; +NET "debug_27" LOC = "N16" ; +NET "debug_28" LOC = "R15" ; +NET "debug_29" LOC = "P15" ; +NET "debug_30" LOC = "N13" ; +NET "debug_31" LOC = "N14" ; +NET "PPS_IN" LOC = "M14" ; +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "FPGA_RXD" LOC = "H12" ; +NET "DA10" LOC = "A8" ; +NET "DA09" LOC = "B8" ; +NET "DA08" LOC = "C8" ; +NET "DA07" LOC = "D8" ; +NET "DA06" LOC = "C9" ; +NET "DA05" LOC = "A9" ; +NET "DA04" LOC = "C10" ; +NET "DA03" LOC = "D9" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "TX00" LOC = "J1" ; +NET "TX01" LOC = "H3" ; +NET "TX02" LOC = "J3" ; +NET "TX03" LOC = "G2" ; +NET "TX04" LOC = "H1" ; +NET "TX05" LOC = "N3" ; +NET "TX06" LOC = "M4" ; +NET "TX07" LOC = "R1" ; +NET "TX08" LOC = "P2" ; +NET "TX09" LOC = "P1" ; +NET "TX10" LOC = "M1" ; +NET "TX11" LOC = "N1" ; +NET "TX12" LOC = "M3" ; +NET "TX13" LOC = "L4" ; +NET "io_tx_00" LOC = "K4" ; +NET "io_tx_01" LOC = "L3" ; +NET "io_tx_02" LOC = "L2" ; +NET "io_tx_03" LOC = "F1" ; +NET "io_tx_04" LOC = "F3" ; +NET "io_tx_05" LOC = "G3" ; +NET "io_tx_06" LOC = "E3" ; +NET "io_tx_07" LOC = "E2" ; +NET "io_tx_08" LOC = "E4" ; +NET "io_tx_09" LOC = "F4" ; +NET "io_tx_10" LOC = "D1" ; +NET "io_tx_11" LOC = "E1" ; +NET "io_tx_12" LOC = "D4" ; +NET "io_tx_13" LOC = "D3" ; +NET "io_tx_14" LOC = "C2" ; +NET "io_tx_15" LOC = "C1" ; +NET "MISO_AUX" LOC = "J5" ; +NET "MISO_CODEC" LOC = "G4" ; +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; +NET "DA02" LOC = "A3" ; +NET "DA01" LOC = "B3" ; +NET "DA00" LOC = "A4" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; +NET "io_rx_00" LOC = "D7" ; +NET "io_rx_01" LOC = "C6" ; +NET "io_rx_02" LOC = "A6" ; +NET "io_rx_03" LOC = "B6" ; +NET "io_rx_04" LOC = "E9" ; +NET "io_rx_05" LOC = "A7" ; +NET "io_rx_06" LOC = "C7" ; +NET "io_rx_07" LOC = "B10" ; +NET "io_rx_08" LOC = "A10" ; +NET "io_rx_09" LOC = "C11" ; +NET "io_rx_10" LOC = "A11" ; +NET "io_rx_11" LOC = "D11" ; +NET "io_rx_12" LOC = "B12" ; +NET "io_rx_13" LOC = "A12" ; +NET "io_rx_14" LOC = "A14" ; +NET "io_rx_15" LOC = "A13" ; +NET "SEN_AUX" LOC = "C12" ; +NET "SCLK_AUX" LOC = "D12" ; +NET "reset_codec" LOC = "B14" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_RX_DB" LOC = "E6" ; +NET "mystery_bus_1" LOC = "C4" ; +NET "mystery_bus_0" LOC = "E7" ; +NET "RXSYNC" LOC = "D10" ; +NET "DA11" LOC = "B15" ; + diff --git a/usrp2/top/u1_core/.gitignore b/usrp2/top/u1_core/.gitignore new file mode 100644 index 000000000..9728395c1 --- /dev/null +++ b/usrp2/top/u1_core/.gitignore @@ -0,0 +1,44 @@ +*~ +/xst +/_ngo +/_xmsgs +/*.stx +/*.tspec +/*.xml +/*.gyd +/*.ngr +/*.tim +/*.err +/*.lso +/*.bld +/*.cmd_log +/*.ise_ISE_Backup +/*.mfd +/*.vm6 +/*.syr +/*.xst +/*.csv +/*.html +/*.jed +/*.pad +/*.ng* +/*.pnx +/*.rpt +/*.prj +/*_html +/*_log +/*.lfp +/*.bit +/*.bin +/*.vcd +/*.unroutes +/*.drc +/*_map.* +/*_guide.* +/*.twr +/*.twx +/a.out +/*.xpi +/*_pad.txt +/*.bgn +/*.par diff --git a/usrp2/top/u1_core/u1_core.v b/usrp2/top/u1_core/u1_core.v new file mode 100755 index 000000000..24a57936e --- /dev/null +++ b/usrp2/top/u1_core/u1_core.v @@ -0,0 +1,455 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u1_core + #(parameter RAM_SIZE=16384) + (input sys_clk, input sys_rst, + input wb_clk, input wb_rst, + + output uart_tx_o, input uart_rx_i, output uart_baud_o, + output [2:0] leds, output [31:0] debug, output [1:0] debug_clk, + + input scl_pad_i, output scl_pad_o, output scl_pad_oen_o, + input sda_pad_i, output sda_pad_o, output sda_pad_oen_o, + + input pps, + output reset_codec, + + input gpif_clk, inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + input [2:0] gpif_misc, + + input [11:0] adc, input rxsync, + output [13:0] dac, output txsync, output txblank, + + // Generic SPI + output sclk, + output mosi, + input miso, + output [3:0] sen, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + input sim_mode + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done, ram_loader_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we; + + wb_1master #(.decode_w(6), + .s0_addr(6'b0000_00),.s0_mask(6'b100000), + .s1_addr(6'b1000_00),.s1_mask(6'b110000), + .s2_addr(6'b1100_00),.s2_mask(6'b111111), + .s3_addr(6'b1100_01),.s3_mask(6'b111111), + .s4_addr(6'b1100_10),.s4_mask(6'b111111), + .s5_addr(6'b1100_11),.s5_mask(6'b111111), + .s6_addr(6'b1101_00),.s6_mask(6'b111111), + .s7_addr(6'b1101_01),.s7_mask(6'b111111), + .s8_addr(6'b1101_10),.s8_mask(6'b111111), + .s9_addr(6'b1101_11),.s9_mask(6'b111111), + .sa_addr(6'b1110_00),.sa_mask(6'b111111), + .sb_addr(6'b1110_01),.sb_mask(6'b111111), + .sc_addr(6'b1110_10),.sc_mask(6'b111111), + .sd_addr(6'b1110_11),.sd_mask(6'b111111), + .se_addr(6'b1111_00),.se_mask(6'b111111), + .sf_addr(6'b1111_01),.sf_mask(6'b111111), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) ); + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start_int), + .mode_o(cpld_mode_int), + .done_o(cpld_done_int), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + wire flush_icache; + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), + .flush_icache(flush_icache)); + + setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(flush_icache)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o(sen), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,31'b0}),.word10(32'b0), + .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + // Output control lines + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_hw = 0; + + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {8'b0}, + {6'b0, uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,1'b0,i2c_int,spi_int,timer_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; + always @(negedge dsp_clk) pps_negedge <= pps; + always @(posedge dsp_clk) pps_posedge <= pps; + always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; + always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; + + wire pps_o; + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]), + .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), + .exp_pps_in(),.exp_pps_out(), + .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // ///////////////////////////////////////////////////////////////////////////////////////// + // CODEC Interface + + assign txblank = 0; + + always @(posedge dsp_clk) + if(tx_strobe) + begin + dac <= dac_a; + txsync <= 0; + end + else + begin + dac <= dac_b; + txsync <= 1; + end + + always @(posedge dsp_clk) + if(rxsync) + begin + adc_a_hold <= adc; + rx_strobe <= 0; + end + else + begin + adc_a <= adc_a_hold; + adc_b <= adc; + rx_strobe <= 1; + end + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk[0] = 0; + assign debug_clk[1] = 0; + assign debug = 0; + + +endmodule // u1_core diff --git a/usrp2/top/u1plus/.gitignore b/usrp2/top/u1plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/u1plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/u1plus/Makefile b/usrp2/top/u1plus/Makefile new file mode 100644 index 000000000..8a7c7856d --- /dev/null +++ b/usrp2/top/u1plus/Makefile @@ -0,0 +1,232 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/priority_enc.v \ +control_lib/pic.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u1_core/u1_core.v \ +top/u1plus/u1plus.ucf \ +top/u1plus/timing.ucf \ +top/u1plus/u1plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf new file mode 100644 index 000000000..ca5ebf8e3 --- /dev/null +++ b/usrp2/top/u1plus/timing.ucf @@ -0,0 +1,2 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; diff --git a/usrp2/top/u1plus/u1plus.ucf b/usrp2/top/u1plus/u1plus.ucf new file mode 100644 index 000000000..8a22d0966 --- /dev/null +++ b/usrp2/top/u1plus/u1plus.ucf @@ -0,0 +1,203 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## UART +NET "FPGA_TXD" LOC = "H16" ; +NET "FPGA_RXD" LOC = "H12" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +NET "fpga_cfg_din" LOC = "T14" ; +NET "fpga_cfg_cclk" LOC = "R14" ; +NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +NET "mystery_bus<2>" LOC = "T11" ; +NET "mystery_bus<1>" LOC = "C4" ; +NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +NET "GPIF_RDY<3>" LOC = "N11" ; +NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_RDY<1>" LOC = "T4" ; +NET "GPIF_RDY<0>" LOC = "R5" ; + +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +NET "SEN_AUX" LOC = "C12" ; +NET "SCLK_AUX" LOC = "D12" ; +NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v new file mode 100644 index 000000000..cb5fbdd36 --- /dev/null +++ b/usrp2/top/u1plus/u1plus.v @@ -0,0 +1,141 @@ + +module u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, // Main Clock + output FPGA_TXD, input FPGA_RXD, // UART + inout SDA_FPGA, inout SCL_FPGA, // I2C + + // CGEN + input cgen_st_ld, + input cgen_st_refmon, + input cgen_st_status, + input cgen_ref_sel, + input cgen_sync_b, + + // FPGA Config + input fpga_cfg_din, + input fpga_cfg_cclk, + input fpga_cfg_init_b, + + // MISC + input [2:0] mystery_bus, + input reset_n, + input PPS_IN, + output reset_codec, + + // GPIF + inout [15:0] GPIF_D, + input [3:0] GPIF_CTL, + output [3:0] GPIF_RDY, + input FX2_PA7_FLAGD, + input FX2_PA6_PKTEND, + input FX2_PA2_SLOE, + input IFCLK, + + output [2:0] debug_led, + + // Debug bus + output [1:0] debug_clk, + output [31:0] debug, + + input [11:0] adc, + input RXSYNC, + + output TXBLANK, + output TXSYNC, + output [13:0] dac, + + // TX DB + inout [15:0] io_tx, + inout [15:0] io_rx, + + // SPI + output SEN_AUX, output SCLK_AUX, input MISO_AUX, + output SEN_CODEC, output SCLK_CODEC, output MOSI_CODEC, input MISO_CODEC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB + ); + + wire clk_fpga, sys_clk, wb_clk, dcm_out, clk_div, dcm_locked; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + DCM DCM_INST (.CLKFB(sys_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(dcm_locked), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 15.625; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG sysclk_BUFG (.I(dcm_out), .O(sys_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + wire mosi, miso, sclk; + assign SCLK_AUX = ~SEN_AUX ? sclk : 2'b00; + assign {SCLK_CODEC,MOSI_CODEC} = ~SEN_CODEC ? {sclk,mosi} : 2'b00; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'b00; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'b00; + assign miso = (~SEN_CODEC & MISO_CODEC) | (~SEN_AUX & MISO_AUX) | + (~SEN_RX_DB & MISO_RX_DB) |(~SEN_TX_DB & MISO_TX_DB); + + u1_core u1_core + (.sys_clk(sys_clk), .sys_rst(sys_rst), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .uart_tx_o(FPGA_TXD), .uart_rx_i(FPGA_RXD), .uart_baud_o(), + + .leds(debug_led), .debug(debug), .debug_clk(debug_clk), + + .scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_pad_oen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_pad_oen_o(sda_pad_oen_o), + + .pps(PPS_IN), + .reset_codec(reset_codec), + + // GPIF + .gpif_clk(IFCLK), .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD, FX2_PA6_PKTEND, FX2_PA2_SLOE}), + + .adc(adc), .rxsync(RXSYNC), + + .txblank(TXBLANK), .txsync(TXSYNC), .dac(dac), + + .io_tx(io_tx), .io_rx(io_rx), + + // SPI + .sclk(sclk), .mosi(mosi), .miso(miso), .sen({SEN_AUX, SEN_CODEC, SEN_RX_DB, SEN_TX_DB}), + .sim_mode(0) + ); + +endmodule // u1plus + + |