diff options
| -rw-r--r-- | usrp2/top/B100/timing.ucf | 7 | ||||
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 2 |
2 files changed, 7 insertions, 2 deletions
diff --git a/usrp2/top/B100/timing.ucf b/usrp2/top/B100/timing.ucf index c4404e1d0..7b212a9a6 100644 --- a/usrp2/top/B100/timing.ucf +++ b/usrp2/top/B100/timing.ucf @@ -15,5 +15,10 @@ INST "GPIF_SLOE" TNM = gpif_net_out; INST "GPIF_SLRD" TNM = gpif_net_out; INST "GPIF_PKTEND" TNM = gpif_net_out; -TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING; +TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "IFCLK" RISING; TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING; + +TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; + +NET PPS_IN TIG; +NET debug_led* TIG; diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 423282153..302565101 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -71,7 +71,7 @@ module u1plus_core localparam SR_GPIO = 224; // 5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd1}; //major, minor + localparam compat_num = {16'd11, 16'd2}; //major, minor //assign run signals used for ATR logic wire [NUM_RX_DSPS-1:0] run_rx_n; |