diff options
| -rw-r--r-- | usrp2/timing/time_64bit.v | 8 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 14 |
2 files changed, 11 insertions, 11 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 33eb2b25a..8122cc6ea 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -6,7 +6,9 @@ module time_64bit (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, input pps, - output [63:0] vita_time, output pps_int, + output [63:0] vita_time, + output reg [63:0] vita_time_pps, + output pps_int, input exp_time_in, output exp_time_out, output [31:0] debug ); @@ -74,6 +76,10 @@ module time_64bit pps_del <= {pps_del[0],pps_reg}; assign pps_edge = pps_del[0] & ~pps_del[1]; + + always @(posedge clk) + if(pps_edge) + vita_time_pps <= vita_time; always @(posedge clk) if(rst) diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 30b47b818..0b56636c8 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -180,7 +180,7 @@ module u2_core wire serdes_link_up; wire epoch; wire [31:0] irq; - wire [63:0] vita_time; + wire [63:0] vita_time, vita_time_pps; wire run_rx, run_tx; reg run_rx_d1; @@ -419,13 +419,6 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 - reg [31:0] cycle_count; - always @(posedge wb_clk) - if(wb_rst) - cycle_count <= 0; - else - cycle_count <= cycle_count + 1; - //compatibility number -> increment when the fpga has been sufficiently altered localparam compat_num = 32'd3; @@ -436,7 +429,8 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) ); // ///////////////////////////////////////////////////////////////////////// @@ -724,7 +718,7 @@ module u2_core time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .debug(debug_sync)); |