diff options
| -rw-r--r-- | firmware/fx2/b100/usrp_main.c | 7 | ||||
| -rw-r--r-- | host/lib/usrp/b100/b100_impl.cpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/b100/b100_impl.hpp | 1 |
3 files changed, 13 insertions, 1 deletions
diff --git a/firmware/fx2/b100/usrp_main.c b/firmware/fx2/b100/usrp_main.c index 436bdeb36..d9e09ca34 100644 --- a/firmware/fx2/b100/usrp_main.c +++ b/firmware/fx2/b100/usrp_main.c @@ -65,6 +65,11 @@ xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE]; //void clear_fpga_data_fifo(void); +//use the B100 fpga_config_cclk/ext_reset line to reset the FPGA +void fpga_reset(int level) { + bitALTERA_DCLK = level; +} + static void get_ep0_data (void) { @@ -169,7 +174,7 @@ app_vendor_cmd (void) break; case VRQ_FPGA_SET_RESET: - //fpga_set_reset (wValueL); + fpga_reset(wValueL); break; case VRQ_I2C_WRITE: diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp index 455efa2fe..08a2cdeec 100644 --- a/host/lib/usrp/b100/b100_impl.cpp +++ b/host/lib/usrp/b100/b100_impl.cpp @@ -181,6 +181,8 @@ b100_impl::b100_impl(const device_addr_t &device_addr){ //load FPGA image, gpif is disabled while loading this->enable_gpif(false); _fx2_ctrl->usrp_load_fpga(b100_fpga_image); + this->set_reset_fpga(1); + this->set_reset_fpga(0); this->enable_gpif(true); //create the control transport @@ -525,6 +527,10 @@ void b100_impl::clear_fpga_fifo(void) { _fx2_ctrl->usrp_control_write(VRQ_CLEAR_FPGA_FIFO, 0, 0, 0, 0); } +void b100_impl::set_reset_fpga(const bool en) { + _fx2_ctrl->usrp_control_write(VRQ_FPGA_SET_RESET, en ? 0 : 1, 0, 0, 0); +} + sensor_value_t b100_impl::get_ref_locked(void){ const bool lock = _clock_ctrl->get_locked(); return sensor_value_t("Ref", lock, "locked", "unlocked"); diff --git a/host/lib/usrp/b100/b100_impl.hpp b/host/lib/usrp/b100/b100_impl.hpp index 49a3139f0..b71b65562 100644 --- a/host/lib/usrp/b100/b100_impl.hpp +++ b/host/lib/usrp/b100/b100_impl.hpp @@ -126,6 +126,7 @@ private: void reset_gpif(const boost::uint16_t); void enable_gpif(const bool); void clear_fpga_fifo(void); + void set_reset_fpga(const bool en); void handle_async_message(uhd::transport::managed_recv_buffer::sptr); uhd::sensor_value_t get_ref_locked(void); void set_rx_fe_corrections(const double); |