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-rw-r--r--usrp2/fifo/Makefile.srcs5
-rw-r--r--usrp2/fifo/crossbar36.v40
-rw-r--r--usrp2/fifo/dsp_framer36.v98
-rw-r--r--usrp2/fifo/packet_router.v645
-rw-r--r--usrp2/fifo/splitter36.v68
-rw-r--r--usrp2/fifo/valve36.v28
-rw-r--r--usrp2/simple_gemac/Makefile.srcs1
-rw-r--r--usrp2/simple_gemac/address_filter_promisc.v32
-rw-r--r--usrp2/simple_gemac/eth_tasks_f36.v6
-rw-r--r--usrp2/simple_gemac/simple_gemac_rx.v10
-rw-r--r--usrp2/simple_gemac/simple_gemac_wb.v27
-rwxr-xr-xusrp2/simple_gemac/simple_gemac_wrapper.build2
-rwxr-xr-xusrp2/simple_gemac/simple_gemac_wrapper19.build2
-rw-r--r--usrp2/simple_gemac/simple_gemac_wrapper19_tb.v10
-rw-r--r--usrp2/simple_gemac/simple_gemac_wrapper_tb.v6
-rw-r--r--usrp2/top/u2_rev3/u2_core.v110
16 files changed, 1003 insertions, 87 deletions
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index c66979132..5552fbd51 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -8,6 +8,8 @@
FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \
buffer_int.v \
buffer_pool.v \
+crossbar36.v \
+dsp_framer36.v \
fifo_2clock.v \
fifo_2clock_cascade.v \
ll8_shortfifo.v \
@@ -22,4 +24,7 @@ fifo36_to_fifo19.v \
fifo19_to_fifo36.v \
fifo36_mux.v \
fifo36_demux.v \
+packet_router.v \
+splitter36.v \
+valve36.v \
))
diff --git a/usrp2/fifo/crossbar36.v b/usrp2/fifo/crossbar36.v
new file mode 100644
index 000000000..d90f5659c
--- /dev/null
+++ b/usrp2/fifo/crossbar36.v
@@ -0,0 +1,40 @@
+
+
+module crossbar36
+ (input clk, input reset, input clear,
+ input cross,
+ input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
+ input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
+ output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
+ output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
+
+ reg cross_int, active0, active1;
+
+ assign data0_o = cross_int ? data1_i : data0_i;
+ assign data1_o = cross_int ? data0_i : data1_i;
+
+ assign src0_rdy_o = cross_int ? src1_rdy_i : src0_rdy_i;
+ assign src1_rdy_o = cross_int ? src0_rdy_i : src1_rdy_i;
+
+ assign dst0_rdy_o = cross_int ? dst1_rdy_i : dst0_rdy_i;
+ assign dst1_rdy_o = cross_int ? dst0_rdy_i : dst1_rdy_i;
+
+ always @(posedge clk)
+ if(reset | clear)
+ active0 <= 0;
+ else if(src0_rdy_i & dst0_rdy_o)
+ active0 <= ~data0_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ active1 <= 0;
+ else if(src1_rdy_i & dst1_rdy_o)
+ active1 <= ~data1_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ cross_int <= 0;
+ else if(~active0 & ~active1)
+ cross_int <= cross;
+
+endmodule // crossbar36
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v
new file mode 100644
index 000000000..fbdc9fbd7
--- /dev/null
+++ b/usrp2/fifo/dsp_framer36.v
@@ -0,0 +1,98 @@
+
+// Frame DSP packets with a header line to be handled by the protocol machine
+
+module dsp_framer36
+ #(parameter BUF_SIZE = 9)
+ (
+ input clk, input rst, input clr,
+ input [35:0] inp_data, input inp_valid, output inp_ready,
+ output [35:0] out_data, output out_valid, input out_ready
+ );
+
+ localparam DSP_FRM_STATE_WAIT_SOF = 0;
+ localparam DSP_FRM_STATE_WAIT_EOF = 1;
+ localparam DSP_FRM_STATE_WRITE_HDR = 2;
+ localparam DSP_FRM_STATE_WRITE = 3;
+
+ reg [1:0] dsp_frm_state;
+ reg [BUF_SIZE-1:0] dsp_frm_addr;
+ reg [BUF_SIZE-1:0] dsp_frm_count;
+ wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
+
+ //DSP input stream ready in the following states
+ assign inp_ready =
+ (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : (
+ (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : (
+ 1'b0));
+
+ //DSP framer output data mux (header or BRAM):
+ //The header is generated here from the count.
+ wire [31:0] dsp_frm_data_bram;
+ wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
+ assign out_data =
+ (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
+ (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : (
+ {4'b0000, dsp_frm_data_bram}));
+ assign out_valid = (
+ (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) ||
+ (dsp_frm_state == DSP_FRM_STATE_WRITE)
+ )? 1'b1 : 1'b0;
+
+ RAMB16_S36_S36 dsp_frm_buff(
+ //port A = DSP input interface (writes to BRAM)
+ .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0),
+ .ENA(inp_ready),.SSRA(0),.WEA(inp_ready),
+ //port B = DSP framer interface (reads from BRAM)
+ .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
+ .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
+ );
+
+ always @(posedge clk)
+ if(rst | clr) begin
+ dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+ dsp_frm_addr <= 0;
+ end
+ else begin
+ case(dsp_frm_state)
+ DSP_FRM_STATE_WAIT_SOF: begin
+ if (inp_ready & inp_valid & inp_data[32]) begin
+ dsp_frm_addr <= dsp_frm_addr_next;
+ dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF;
+ end
+ end
+
+ DSP_FRM_STATE_WAIT_EOF: begin
+ if (inp_ready & inp_valid) begin
+ if (inp_data[33]) begin
+ dsp_frm_count <= dsp_frm_addr_next;
+ dsp_frm_addr <= 0;
+ dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR;
+ end
+ else begin
+ dsp_frm_addr <= dsp_frm_addr_next;
+ end
+ end
+ end
+
+ DSP_FRM_STATE_WRITE_HDR: begin
+ if (out_ready & out_valid) begin
+ dsp_frm_addr <= dsp_frm_addr_next;
+ dsp_frm_state <= DSP_FRM_STATE_WRITE;
+ end
+ end
+
+ DSP_FRM_STATE_WRITE: begin
+ if (out_ready & out_valid) begin
+ if (out_data[33]) begin
+ dsp_frm_addr <= 0;
+ dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+ end
+ else begin
+ dsp_frm_addr <= dsp_frm_addr_next;
+ end
+ end
+ end
+ endcase //dsp_frm_state
+ end
+
+endmodule //dsp_framer36
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
new file mode 100644
index 000000000..6cf022b11
--- /dev/null
+++ b/usrp2/fifo/packet_router.v
@@ -0,0 +1,645 @@
+module packet_router
+ #(
+ parameter BUF_SIZE = 9,
+ parameter UDP_BASE = 0,
+ parameter CTRL_BASE = 0
+ )
+ (
+ //wishbone interface for memory mapped CPU frames
+ input wb_clk_i,
+ input wb_rst_i,
+ input wb_we_i,
+ input wb_stb_i,
+ input [15:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ output [31:0] wb_dat_o,
+ output reg wb_ack_o,
+ output wb_err_o,
+ output wb_rty_o,
+
+ //setting register interface
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ input stream_clk,
+ input stream_rst,
+ input stream_clr,
+
+ //output status register
+ output [31:0] status,
+
+ output sys_int_o, //want an interrupt?
+
+ output [31:0] debug,
+
+ // Input Interfaces (in to router)
+ input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready,
+ input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready,
+ input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready,
+ input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready,
+
+ // Output Interfaces (out of router)
+ output [35:0] ser_out_data, output ser_out_valid, input ser_out_ready,
+ output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+ output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready
+ );
+
+ assign wb_err_o = 1'b0; // Unused for now
+ assign wb_rty_o = 1'b0; // Unused for now
+ always @(posedge wb_clk_i)
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+ //which buffer: 0 = CPU read buffer, 1 = CPU write buffer
+ wire which_buf = wb_adr_i[BUF_SIZE+2];
+
+ ////////////////////////////////////////////////////////////////////
+ // CPU interface to this packet router
+ ////////////////////////////////////////////////////////////////////
+ wire [35:0] cpu_inp_data, cpu_out_data;
+ wire cpu_inp_valid, cpu_out_valid;
+ wire cpu_inp_ready, cpu_out_ready;
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication interfaces
+ ////////////////////////////////////////////////////////////////////
+ wire [35:0] com_inp_data, com_out_data, udp_out_data;
+ wire com_inp_valid, com_out_valid, udp_out_valid;
+ wire com_inp_ready, com_out_ready, udp_out_ready;
+
+ ////////////////////////////////////////////////////////////////////
+ // Control signals (setting registers and status signals)
+ // - handshake lines for the CPU communication
+ // - setting registers to program the inspector
+ ////////////////////////////////////////////////////////////////////
+
+ //setting register to misc control
+ wire [31:0] _sreg_misc_ctrl;
+ wire master_mode_flag = _sreg_misc_ctrl[0];
+ setting_reg #(.my_addr(CTRL_BASE+0)) sreg_misc_ctrl(
+ .clk(stream_clk),.rst(stream_rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(_sreg_misc_ctrl),.changed()
+ );
+
+ //setting register to program the IP address
+ wire [31:0] my_ip_addr;
+ setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr(
+ .clk(stream_clk),.rst(stream_rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(my_ip_addr),.changed()
+ );
+
+ //setting register to program the UDP data ports
+ wire [15:0] dsp0_udp_port, dsp1_udp_port;
+ setting_reg #(.my_addr(CTRL_BASE+2)) sreg_udp_ports(
+ .clk(stream_clk),.rst(stream_rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out({dsp1_udp_port, dsp0_udp_port}),.changed()
+ );
+
+ //setting register for CPU output handshake
+ wire [31:0] _sreg_cpu_out_ctrl;
+ wire cpu_out_hs_ctrl = _sreg_cpu_out_ctrl[0];
+ setting_reg #(.my_addr(CTRL_BASE+3)) sreg_cpu_out_ctrl(
+ .clk(stream_clk),.rst(stream_rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(_sreg_cpu_out_ctrl),.changed()
+ );
+
+ //setting register for CPU input handshake
+ wire [31:0] _sreg_cpu_inp_ctrl;
+ wire cpu_inp_hs_ctrl = _sreg_cpu_inp_ctrl[0];
+ wire [BUF_SIZE-1:0] cpu_inp_line_count = _sreg_cpu_inp_ctrl[BUF_SIZE-1+16:0+16];
+ setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_inp_ctrl(
+ .clk(stream_clk),.rst(stream_rst),
+ .strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(_sreg_cpu_inp_ctrl),.changed()
+ );
+
+ //assign status output signals
+ wire cpu_out_hs_stat;
+ assign status[0] = cpu_out_hs_stat;
+ wire [BUF_SIZE-1:0] cpu_out_line_count;
+ assign status[BUF_SIZE-1+16:0+16] = cpu_out_line_count;
+ wire cpu_inp_hs_stat;
+ assign status[1] = cpu_inp_hs_stat;
+ assign status[8] = master_mode_flag; //for the host to readback
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication input source crossbar
+ // When in master mode:
+ // - serdes input -> comm output combiner
+ // - ethernet input -> comm input inspector
+ // When in slave mode:
+ // - serdes input -> comm input inspector
+ // - ethernet input -> null sink
+ ////////////////////////////////////////////////////////////////////
+
+ //streaming signals from the crossbar to the combiner
+ wire [35:0] crs_inp_data;
+ wire crs_inp_valid;
+ wire crs_inp_ready;
+
+ //dummy signals for valve/xbar below
+ wire [35:0] _eth_inp_data;
+ wire _eth_inp_valid;
+ wire _eth_inp_ready;
+
+ valve36 eth_inp_valve (
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag),
+ .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready),
+ .data_o(_eth_inp_data), .src_rdy_o(_eth_inp_valid), .dst_rdy_i(_eth_inp_ready)
+ );
+
+ crossbar36 com_inp_xbar (
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
+ .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready),
+ .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready),
+ .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready),
+ .data1_o(crs_inp_data), .src1_rdy_o(crs_inp_valid), .dst1_rdy_i(crs_inp_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication output sink crossbar
+ // When in master mode:
+ // - comm output -> ethernet output
+ // - insp output -> serdes output
+ // When in slave mode:
+ // - com output -> serdes output
+ // - insp output -> null sink
+ ////////////////////////////////////////////////////////////////////
+
+ //streaming signals from the inspector to the crossbar
+ wire [35:0] crs_out_data;
+ wire crs_out_valid;
+ wire crs_out_ready;
+
+ //dummy signals for valve/xbar below
+ wire [35:0] _eth_out_data;
+ wire _eth_out_valid;
+ wire _eth_out_ready;
+
+ crossbar36 com_out_xbar (
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
+ .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready),
+ .data1_i(crs_out_data), .src1_rdy_i(crs_out_valid), .dst1_rdy_o(crs_out_ready),
+ .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready),
+ .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready)
+ );
+
+ valve36 eth_out_valve (
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag),
+ .data_i(_eth_out_data), .src_rdy_i(_eth_out_valid), .dst_rdy_o(_eth_out_ready),
+ .data_o(eth_out_data), .src_rdy_o(eth_out_valid), .dst_rdy_i(eth_out_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication output source combiner (feeds UDP proto machine)
+ // - DSP framer
+ // - CPU input
+ // - Error input
+ // - Crossbar input
+ ////////////////////////////////////////////////////////////////////
+
+ //streaming signals from the dsp framer to the combiner
+ wire [35:0] dsp_frm_data;
+ wire dsp_frm_valid;
+ wire dsp_frm_ready;
+
+ //dummy signals to join the the muxes below
+ wire [35:0] _combiner0_data, _combiner1_data;
+ wire _combiner0_valid, _combiner1_valid;
+ wire _combiner0_ready, _combiner1_ready;
+
+ fifo36_mux _com_output_combiner0(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready),
+ .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready),
+ .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
+ );
+
+ fifo36_mux _com_output_combiner1(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here
+ .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
+ .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
+ );
+
+ fifo36_mux com_output_source(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
+ .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
+ .data_o(udp_out_data), .src_rdy_o(udp_out_valid), .dst_rdy_i(udp_out_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // Interface CPU output to memory mapped wishbone
+ ////////////////////////////////////////////////////////////////////
+ localparam CPU_OUT_STATE_WAIT_SOF = 0;
+ localparam CPU_OUT_STATE_WAIT_EOF = 1;
+ localparam CPU_OUT_STATE_WAIT_CTRL_HI = 2;
+ localparam CPU_OUT_STATE_WAIT_CTRL_LO = 3;
+
+ reg [1:0] cpu_out_state;
+ reg [BUF_SIZE-1:0] cpu_out_addr;
+ assign cpu_out_line_count = cpu_out_addr;
+ wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1;
+
+ wire cpu_out_reading = (
+ cpu_out_state == CPU_OUT_STATE_WAIT_SOF ||
+ cpu_out_state == CPU_OUT_STATE_WAIT_EOF
+ )? 1'b1 : 1'b0;
+
+ wire cpu_out_we = cpu_out_reading;
+ assign cpu_out_ready = cpu_out_reading;
+ assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
+
+ RAMB16_S36_S36 cpu_out_buff(
+ //port A = wishbone memory mapped address space (output only)
+ .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0),
+ .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i),
+ //port B = packet router interface to CPU (input only)
+ .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0),
+ .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we)
+ );
+
+ always @(posedge stream_clk)
+ if(stream_rst | stream_clr) begin
+ cpu_out_state <= CPU_OUT_STATE_WAIT_SOF;
+ cpu_out_addr <= 0;
+ end
+ else begin
+ case(cpu_out_state)
+ CPU_OUT_STATE_WAIT_SOF: begin
+ if (cpu_out_ready & cpu_out_valid & cpu_out_data[32]) begin
+ cpu_out_state <= CPU_OUT_STATE_WAIT_EOF;
+ cpu_out_addr <= cpu_out_addr_next;
+ end
+ end
+
+ CPU_OUT_STATE_WAIT_EOF: begin
+ if (cpu_out_ready & cpu_out_valid & cpu_out_data[33]) begin
+ cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI;
+ end
+ if (cpu_out_ready & cpu_out_valid) begin
+ cpu_out_addr <= cpu_out_addr_next;
+ end
+ end
+
+ CPU_OUT_STATE_WAIT_CTRL_HI: begin
+ if (cpu_out_hs_ctrl == 1'b1) begin
+ cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO;
+ end
+ end
+
+ CPU_OUT_STATE_WAIT_CTRL_LO: begin
+ if (cpu_out_hs_ctrl == 1'b0) begin
+ cpu_out_state <= CPU_OUT_STATE_WAIT_SOF;
+ end
+ cpu_out_addr <= 0; //reset the address counter
+ end
+
+ endcase //cpu_out_state
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ // Interface CPU input to memory mapped wishbone
+ ////////////////////////////////////////////////////////////////////
+ localparam CPU_INP_STATE_WAIT_CTRL_HI = 0;
+ localparam CPU_INP_STATE_WAIT_CTRL_LO = 1;
+ localparam CPU_INP_STATE_UNLOAD = 2;
+
+ reg [1:0] cpu_inp_state;
+ reg [BUF_SIZE-1:0] cpu_inp_addr;
+ wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1;
+
+ reg [BUF_SIZE-1:0] cpu_inp_line_count_reg;
+
+ assign cpu_inp_data[35:32] =
+ (cpu_inp_addr == 1 )? 4'b0001 : (
+ (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : (
+ 4'b0000));
+
+ assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0;
+ assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
+
+ RAMB16_S36_S36 cpu_inp_buff(
+ //port A = wishbone memory mapped address space (input only)
+ .DOA(),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+ .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i),
+ //port B = packet router interface from CPU (output only)
+ .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0),
+ .ENB(cpu_inp_ready & cpu_inp_valid),.SSRB(0),.WEB(1'b0)
+ );
+
+ always @(posedge stream_clk)
+ if(stream_rst | stream_clr) begin
+ cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI;
+ cpu_inp_addr <= 0;
+ end
+ else begin
+ case(cpu_inp_state)
+ CPU_INP_STATE_WAIT_CTRL_HI: begin
+ if (cpu_inp_hs_ctrl == 1'b1) begin
+ cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO;
+ end
+ cpu_inp_line_count_reg <= cpu_inp_line_count;
+ end
+
+ CPU_INP_STATE_WAIT_CTRL_LO: begin
+ if (cpu_inp_hs_ctrl == 1'b0) begin
+ cpu_inp_state <= CPU_INP_STATE_UNLOAD;
+ cpu_inp_addr <= cpu_inp_addr_next;
+ end
+ end
+
+ CPU_INP_STATE_UNLOAD: begin
+ if (cpu_inp_ready & cpu_inp_valid) begin
+ if (cpu_inp_data[33]) begin
+ cpu_inp_addr <= 0;
+ cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI;
+ end
+ else begin
+ cpu_inp_addr <= cpu_inp_addr_next;
+ end
+ end
+ end
+
+ endcase //cpu_inp_state
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ // Communication input inspector
+ // - inspect com input and send it to CPU, DSP, or COM
+ ////////////////////////////////////////////////////////////////////
+ localparam COM_INSP_STATE_READ_COM_PRE = 0;
+ localparam COM_INSP_STATE_READ_COM = 1;
+ localparam COM_INSP_STATE_WRITE_REGS = 2;
+ localparam COM_INSP_STATE_WRITE_LIVE = 3;
+
+ localparam COM_INSP_DEST_FP_THIS = 0;
+ localparam COM_INSP_DEST_FP_OTHER = 1;
+ localparam COM_INSP_DEST_SP_BOTH = 2;
+
+ localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
+ localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at
+
+ //output inspector interfaces
+ wire [35:0] com_insp_out_fp_this_data;
+ wire com_insp_out_fp_this_valid;
+ wire com_insp_out_fp_this_ready;
+
+ wire [35:0] com_insp_out_fp_other_data;
+ wire com_insp_out_fp_other_valid;
+ wire com_insp_out_fp_other_ready;
+
+ wire [35:0] com_insp_out_sp_both_data;
+ wire com_insp_out_sp_both_valid;
+ wire com_insp_out_sp_both_ready;
+
+ //connect this fast-path signals directly to the DSP out
+ assign dsp_out_data = com_insp_out_fp_this_data;
+ assign dsp_out_valid = com_insp_out_fp_this_valid;
+ assign com_insp_out_fp_this_ready = dsp_out_ready;
+
+ reg [1:0] com_insp_state;
+ reg [1:0] com_insp_dest;
+ reg [3:0] com_insp_dreg_count; //data registers to buffer headers
+ wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1;
+ wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0;
+ reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0];
+
+ //Inspection logic:
+ wire com_inp_dregs_is_data = 1'b1
+ && (com_insp_dregs[3][15:0] == 16'h800) //ethertype IPv4
+ && (com_insp_dregs[6][23:16] == 8'h11) //protocol UDP
+ && (com_insp_dregs[9][15:0] == dsp0_udp_port) //UDP data port
+ && (com_inp_data[15:0] != 16'h0) //VRT packet size
+ ;
+
+ wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0;
+ wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & com_inp_dregs_my_ip_match;
+ wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & ~com_inp_dregs_my_ip_match;
+
+ //Inspector output flags special case:
+ //Inject SOF into flags at first DSP line.
+ wire [3:0] com_insp_out_flags = (
+ (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) &&
+ (com_insp_dest == COM_INSP_DEST_FP_THIS)
+ )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32];
+
+ //The communication inspector ouput data and valid signals:
+ //Mux between com input and data registers based on the state.
+ wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)?
+ {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data
+ ;
+ wire com_insp_out_valid =
+ (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1 : (
+ (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : (
+ 1'b0));
+
+ //The communication inspector ouput ready signal:
+ //Mux between the various destination ready signals.
+ wire com_insp_out_ready =
+ (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_fp_this_ready : (
+ (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_fp_other_ready : (
+ (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_sp_both_ready : (
+ 1'b0)));
+
+ //Always connected output data lines.
+ assign com_insp_out_fp_this_data = com_insp_out_data;
+ assign com_insp_out_fp_other_data = com_insp_out_data;
+ assign com_insp_out_sp_both_data = com_insp_out_data;
+
+ //Destination output valid signals:
+ //Comes from inspector valid when destination is selected, and otherwise low.
+ assign com_insp_out_fp_this_valid = (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_valid : 1'b0;
+ assign com_insp_out_fp_other_valid = (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_valid : 1'b0;
+ assign com_insp_out_sp_both_valid = (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_valid : 1'b0;
+
+ //The communication inspector ouput ready signal:
+ //Always ready when storing to data registers,
+ //comes from inspector ready output when live,
+ //and otherwise low.
+ assign com_inp_ready =
+ (com_insp_state == COM_INSP_STATE_READ_COM_PRE) ? 1'b1 : (
+ (com_insp_state == COM_INSP_STATE_READ_COM) ? 1'b1 : (
+ (com_insp_state == COM_INSP_STATE_WRITE_LIVE) ? com_insp_out_ready : (
+ 1'b0)));
+
+ always @(posedge stream_clk)
+ if(stream_rst | stream_clr) begin
+ com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+ com_insp_dreg_count <= 0;
+ end
+ else begin
+ case(com_insp_state)
+ COM_INSP_STATE_READ_COM_PRE: begin
+ if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
+ com_insp_state <= COM_INSP_STATE_READ_COM;
+ com_insp_dreg_count <= com_insp_dreg_count_next;
+ com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
+ end
+ end
+
+ COM_INSP_STATE_READ_COM: begin
+ if (com_inp_ready & com_inp_valid) begin
+ com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
+ if (com_inp_dregs_is_data_here & com_insp_dreg_counter_done) begin
+ com_insp_dest <= COM_INSP_DEST_FP_THIS;
+ com_insp_state <= COM_INSP_STATE_WRITE_REGS;
+ com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
+ end
+ else if (com_inp_dregs_is_data_there & com_insp_dreg_counter_done) begin
+ com_insp_dest <= COM_INSP_DEST_FP_OTHER;
+ com_insp_state <= COM_INSP_STATE_WRITE_REGS;
+ com_insp_dreg_count <= 0;
+ end
+ else if (com_inp_data[33] | com_insp_dreg_counter_done) begin
+ com_insp_dest <= COM_INSP_DEST_SP_BOTH;
+ com_insp_state <= COM_INSP_STATE_WRITE_REGS;
+ com_insp_dreg_count <= 0;
+ end
+ else begin
+ com_insp_dreg_count <= com_insp_dreg_count_next;
+ end
+ end
+ end
+
+ COM_INSP_STATE_WRITE_REGS: begin
+ if (com_insp_out_ready & com_insp_out_valid) begin
+ if (com_insp_out_data[33]) begin
+ com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+ com_insp_dreg_count <= 0;
+ end
+ else if (com_insp_dreg_counter_done) begin
+ com_insp_state <= COM_INSP_STATE_WRITE_LIVE;
+ com_insp_dreg_count <= 0;
+ end
+ else begin
+ com_insp_dreg_count <= com_insp_dreg_count_next;
+ end
+ end
+ end
+
+ COM_INSP_STATE_WRITE_LIVE: begin
+ if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin
+ com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
+ end
+ end
+
+ endcase //com_insp_state
+ end
+
+ ////////////////////////////////////////////////////////////////////
+ // Serdes crossbar output source
+ // - combine slow-path data with fast-path other data
+ // - slow-path data is duplicated to this and CPU out
+ ////////////////////////////////////////////////////////////////////
+
+ //dummy signals to join the the splitter and mux below
+ wire [35:0] _sp_split_to_mux_data;
+ wire _sp_split_to_mux_valid;
+ wire _sp_split_to_mux_ready;
+
+ splitter36 crs_out_src0(
+ .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+ .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready),
+ .out0_data(_sp_split_to_mux_data), .out0_valid(_sp_split_to_mux_valid), .out0_ready(_sp_split_to_mux_ready),
+ .out1_data(cpu_out_data), .out1_valid(cpu_out_valid), .out1_ready(cpu_out_ready)
+ );
+
+ fifo36_mux crs_out_src1(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready),
+ .data1_i(_sp_split_to_mux_data), .src1_rdy_i(_sp_split_to_mux_valid), .dst1_rdy_o(_sp_split_to_mux_ready),
+ .data_o(crs_out_data), .src_rdy_o(crs_out_valid), .dst_rdy_i(crs_out_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // DSP input framer
+ ////////////////////////////////////////////////////////////////////
+
+ dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36(
+ .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+ .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready),
+ .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // UDP TX Protocol machine
+ ////////////////////////////////////////////////////////////////////
+
+ //dummy signals to connect the components below
+ wire [18:0] _udp_r2s_data, _udp_s2p_data, _udp_p2s_data, _udp_s2r_data;
+ wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid;
+ wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready;
+
+ wire [35:0] _com_out_data;
+ wire _com_out_valid, _com_out_ready;
+
+ fifo36_to_fifo19 udp_fifo36_to_fifo19
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready),
+ .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) );
+
+ fifo_short #(.WIDTH(19)) udp_shortfifo19_inp
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready),
+ .dataout(_udp_s2p_data), .src_rdy_o(_udp_s2p_valid), .dst_rdy_i(_udp_s2p_ready),
+ .space(), .occupied() );
+
+ prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .datain(_udp_s2p_data), .src_rdy_i(_udp_s2p_valid), .dst_rdy_o(_udp_s2p_ready),
+ .dataout(_udp_p2s_data), .src_rdy_o(_udp_p2s_valid), .dst_rdy_i(_udp_p2s_ready) );
+
+ fifo_short #(.WIDTH(19)) udp_shortfifo19_out
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .datain(_udp_p2s_data), .src_rdy_i(_udp_p2s_valid), .dst_rdy_o(_udp_p2s_ready),
+ .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready),
+ .space(), .occupied() );
+
+ fifo19_to_fifo36 udp_fifo19_to_fifo36
+ (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready),
+ .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) );
+
+ fifo36_mux com_out_mux(
+ .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+ .data0_i(crs_inp_data), .src0_rdy_i(crs_inp_valid), .dst0_rdy_o(crs_inp_ready),
+ .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready),
+ .data_o(com_out_data), .src_rdy_o(com_out_valid), .dst_rdy_i(com_out_ready)
+ );
+
+ ////////////////////////////////////////////////////////////////////
+ // Assign debugs
+ ////////////////////////////////////////////////////////////////////
+
+ assign debug = {
+ //inputs to the router (8)
+ dsp_inp_ready, dsp_inp_valid,
+ ser_inp_ready, ser_inp_valid,
+ eth_inp_ready, eth_inp_valid,
+ cpu_inp_ready, cpu_inp_valid,
+
+ //outputs from the router (8)
+ dsp_out_ready, dsp_out_valid,
+ ser_out_ready, ser_out_valid,
+ eth_out_ready, eth_out_valid,
+ cpu_out_ready, cpu_out_valid,
+
+ //inspector interfaces (8)
+ com_inp_ready, com_inp_valid,
+ com_insp_out_fp_this_ready, com_insp_out_fp_this_valid,
+ com_insp_out_fp_other_ready, com_insp_out_fp_other_valid,
+ com_insp_out_sp_both_ready, com_insp_out_sp_both_valid,
+
+ //other interfaces (8)
+ crs_inp_ready, crs_inp_valid,
+ com_out_ready, com_out_valid,
+ crs_out_ready, crs_out_valid,
+ _sp_split_to_mux_ready, _sp_split_to_mux_valid
+ };
+
+endmodule // packet_router
diff --git a/usrp2/fifo/splitter36.v b/usrp2/fifo/splitter36.v
new file mode 100644
index 000000000..ed998b4f5
--- /dev/null
+++ b/usrp2/fifo/splitter36.v
@@ -0,0 +1,68 @@
+
+// Split packets from a fifo based interface so it goes out identically on two interfaces
+
+module splitter36
+ (
+ input clk, input rst, input clr,
+ input [35:0] inp_data, input inp_valid, output inp_ready,
+ output [35:0] out0_data, output out0_valid, input out0_ready,
+ output [35:0] out1_data, output out1_valid, input out1_ready
+ );
+
+ localparam STATE_COPY_BOTH = 0;
+ localparam STATE_COPY_ZERO = 1;
+ localparam STATE_COPY_ONE = 2;
+
+ reg [1:0] state;
+ reg [35:0] data_reg;
+
+ assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+ assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+
+ assign out0_valid =
+ (state == STATE_COPY_BOTH)? inp_valid : (
+ (state == STATE_COPY_ZERO)? 1'b1 : (
+ 1'b0));
+
+ assign out1_valid =
+ (state == STATE_COPY_BOTH)? inp_valid : (
+ (state == STATE_COPY_ONE)? 1'b1 : (
+ 1'b0));
+
+ assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0;
+
+ always @(posedge clk)
+ if (rst | clr) begin
+ state <= STATE_COPY_BOTH;
+ end
+ else begin
+ case (state)
+
+ STATE_COPY_BOTH: begin
+ if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin
+ state <= STATE_COPY_ONE;
+ end
+ else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin
+ state <= STATE_COPY_ZERO;
+ end
+ data_reg <= inp_data;
+ end
+
+ STATE_COPY_ZERO: begin
+ if (out0_valid & out0_ready) begin
+ state <= STATE_COPY_BOTH;
+ end
+ end
+
+ STATE_COPY_ONE: begin
+ if (out1_valid & out1_ready) begin
+ state <= STATE_COPY_BOTH;
+ end
+ end
+
+ endcase //state
+ end
+
+
+
+endmodule //splitter36
diff --git a/usrp2/fifo/valve36.v b/usrp2/fifo/valve36.v
new file mode 100644
index 000000000..b4b23e5a6
--- /dev/null
+++ b/usrp2/fifo/valve36.v
@@ -0,0 +1,28 @@
+
+
+module valve36
+ (input clk, input reset, input clear,
+ input shutoff,
+ input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ reg shutoff_int, active;
+
+ assign data_o = data_i;
+
+ assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i;
+ assign src_rdy_o = shutoff_int ? 1'b0 : src_rdy_i;
+
+ always @(posedge clk)
+ if(reset | clear)
+ active <= 0;
+ else if(src_rdy_i & dst_rdy_o)
+ active <= ~data_i[33];
+
+ always @(posedge clk)
+ if(reset | clear)
+ shutoff_int <= 0;
+ else if(~active)
+ shutoff_int <= shutoff;
+
+endmodule // valve36
diff --git a/usrp2/simple_gemac/Makefile.srcs b/usrp2/simple_gemac/Makefile.srcs
index 6480cd5a4..b82e64208 100644
--- a/usrp2/simple_gemac/Makefile.srcs
+++ b/usrp2/simple_gemac/Makefile.srcs
@@ -17,6 +17,7 @@ delay_line.v \
flow_ctrl_tx.v \
flow_ctrl_rx.v \
address_filter.v \
+address_filter_promisc.v \
ll8_to_txmac.v \
rxmac_to_ll8.v \
miim/eth_miim.v \
diff --git a/usrp2/simple_gemac/address_filter_promisc.v b/usrp2/simple_gemac/address_filter_promisc.v
new file mode 100644
index 000000000..6047e7c93
--- /dev/null
+++ b/usrp2/simple_gemac/address_filter_promisc.v
@@ -0,0 +1,32 @@
+
+
+module address_filter_promisc
+ (input clk,
+ input reset,
+ input go,
+ input [7:0] data,
+ output match,
+ output done);
+
+ reg [2:0] af_state;
+
+ always @(posedge clk)
+ if(reset)
+ af_state <= 0;
+ else
+ if(go)
+ af_state <= (data[0] == 1'b0) ? 1 : 7;
+ else
+ case(af_state)
+ 1 : af_state <= 2;
+ 2 : af_state <= 3;
+ 3 : af_state <= 4;
+ 4 : af_state <= 5;
+ 5 : af_state <= 6;
+ 6, 7 : af_state <= 0;
+ endcase // case (af_state)
+
+ assign match = (af_state==6);
+ assign done = (af_state==6)|(af_state==7);
+
+endmodule // address_filter_promisc
diff --git a/usrp2/simple_gemac/eth_tasks_f36.v b/usrp2/simple_gemac/eth_tasks_f36.v
index efd72778b..dc64971d4 100644
--- a/usrp2/simple_gemac/eth_tasks_f36.v
+++ b/usrp2/simple_gemac/eth_tasks_f36.v
@@ -4,11 +4,11 @@ task SendFlowCtrl;
input [15:0] fc_len;
begin
$display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
- pause_time <= fc_len;
+ //pause_time <= fc_len;
@(posedge eth_clk);
- pause_req <= 1;
+ //pause_req <= 1;
@(posedge eth_clk);
- pause_req <= 0;
+ //pause_req <= 0;
$display("Sent Flow Control");
end
endtask // SendFlowCtrl
diff --git a/usrp2/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v
index b02bb0758..32f517bb3 100644
--- a/usrp2/simple_gemac/simple_gemac_rx.v
+++ b/usrp2/simple_gemac/simple_gemac_rx.v
@@ -56,10 +56,10 @@ module simple_gemac_rx
else
rx_ack <= (rx_state == RX_GOODFRAME);
- wire is_ucast, is_bcast, is_mcast, is_pause;
- wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
- (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
-
+ wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
+ wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
+ (pass_bcast & is_bcast) | (pass_pause & is_pause);
+
assign rx_data = rxd_del;
assign rx_error = (rx_state == RX_ERROR);
@@ -79,6 +79,8 @@ module simple_gemac_rx
.address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(48'h0180_c200_0001), .match(is_pause), .done());
+ address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+ .match(is_any_ucast), .done());
always @(posedge rx_clk)
go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
diff --git a/usrp2/simple_gemac/simple_gemac_wb.v b/usrp2/simple_gemac/simple_gemac_wb.v
index 6df277e3e..1ef38be11 100644
--- a/usrp2/simple_gemac/simple_gemac_wb.v
+++ b/usrp2/simple_gemac/simple_gemac_wb.v
@@ -1,16 +1,17 @@
module wb_reg
#(parameter ADDR=0,
- parameter DEFAULT=0)
+ parameter DEFAULT=0,
+ parameter WIDTH=32)
(input clk, input rst,
input [5:0] adr, input wr_acc,
- input [31:0] dat_i, output reg [31:0] dat_o);
+ input [31:0] dat_i, output reg [WIDTH-1:0] dat_o);
always @(posedge clk)
if(rst)
dat_o <= DEFAULT;
else if(wr_acc & (adr == ADDR))
- dat_o <= dat_i;
+ dat_o <= dat_i[WIDTH-1:0];
endmodule // wb_reg
@@ -41,19 +42,19 @@ module simple_gemac_wb
wire [6:0] misc_settings;
assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
- wb_reg #(.ADDR(0),.DEFAULT(7'b0111001))
+ wb_reg #(.ADDR(0),.DEFAULT(7'b0111011),.WIDTH(7))
wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(misc_settings) );
- wb_reg #(.ADDR(1),.DEFAULT(0))
+ wb_reg #(.ADDR(1),.DEFAULT(0),.WIDTH(16))
wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
- wb_reg #(.ADDR(2),.DEFAULT(0))
+ wb_reg #(.ADDR(2),.DEFAULT(0),.WIDTH(32))
wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
- wb_reg #(.ADDR(3),.DEFAULT(0))
+ wb_reg #(.ADDR(3),.DEFAULT(0),.WIDTH(16))
wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
- wb_reg #(.ADDR(4),.DEFAULT(0))
+ wb_reg #(.ADDR(4),.DEFAULT(0),.WIDTH(32))
wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
@@ -80,15 +81,15 @@ module simple_gemac_wb
reg [15:0] MIIRX_DATA;
wire [2:0] MIISTATUS;
- wb_reg #(.ADDR(5),.DEFAULT(0))
+ wb_reg #(.ADDR(5),.DEFAULT(0),.WIDTH(9))
wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
- wb_reg #(.ADDR(6),.DEFAULT(0))
+ wb_reg #(.ADDR(6),.DEFAULT(0),.WIDTH(13))
wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
- wb_reg #(.ADDR(7),.DEFAULT(0))
+ wb_reg #(.ADDR(7),.DEFAULT(0),.WIDTH(16))
wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(CtrlData) );
@@ -133,11 +134,11 @@ module simple_gemac_wb
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
- wb_reg #(.ADDR(11),.DEFAULT(0))
+ wb_reg #(.ADDR(11),.DEFAULT(0),.WIDTH(16))
wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(pause_time) );
- wb_reg #(.ADDR(12),.DEFAULT(0))
+ wb_reg #(.ADDR(12),.DEFAULT(0),.WIDTH(16))
wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
.dat_i(wb_dat_i), .dat_o(pause_thresh) );
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.build b/usrp2/simple_gemac/simple_gemac_wrapper.build
index 30f65ab17..9293deca6 100755
--- a/usrp2/simple_gemac/simple_gemac_wrapper.build
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.build b/usrp2/simple_gemac/simple_gemac_wrapper19.build
index 4be0aac1f..b9475baa2 100755
--- a/usrp2/simple_gemac/simple_gemac_wrapper19.build
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
+iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
index 7d57542dc..b61d60d30 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -44,12 +44,12 @@ module simple_gemac_wrapper19_tb;
reg wb_stb=0, wb_cyc=0, wb_we=0;
wire wb_ack;
- reg [18:0] tx_f19_data=0;
+ reg [19:0] tx_f19_data=0;
reg tx_f19_src_rdy = 0;
wire tx_f19_dst_rdy;
- wire [35:0] rx_f36_data;
- wire rx_f36_src_rdy;
- wire rx_f36_dst_rdy = 1;
+ wire [35:0] rx_f19_data;
+ wire rx_f19_src_rdy;
+ wire rx_f19_dst_rdy = 1;
simple_gemac_wrapper19 simple_gemac_wrapper19
(.clk125(eth_clk), .reset(reset),
@@ -59,7 +59,7 @@ module simple_gemac_wrapper19_tb;
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
//.pause_req(pause_req), .pause_time(pause_time),
- .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+ .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
.tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
index 26a471a49..0aadc7e93 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
@@ -24,9 +24,6 @@ module simple_gemac_wrapper_tb;
wire [7:0] rx_data, tx_data;
- reg [15:0] pause_time;
- reg pause_req = 0;
-
wire GMII_RX_CLK = GMII_GTX_CLK;
reg [7:0] FORCE_DAT_ERR = 0;
@@ -47,7 +44,7 @@ module simple_gemac_wrapper_tb;
reg [35:0] tx_f36_data=0;
reg tx_f36_src_rdy = 0;
wire tx_f36_dst_rdy;
- wire rx_f36_data;
+ wire [35:0] rx_f36_data;
wire rx_f36_src_rdy;
wire rx_f36_dst_rdy = 1;
@@ -57,7 +54,6 @@ module simple_gemac_wrapper_tb;
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
- .pause_req(pause_req), .pause_time(pause_time),
.sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
.tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 30b47b818..363ac3635 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -163,7 +163,7 @@ module u2_core
wire ram_loader_rst, wb_rst, dsp_rst;
assign dsp_rst = wb_rst;
- wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+ wire [31:0] status;
wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
@@ -359,33 +359,32 @@ module u2_core
wire wr3_ready_i, wr3_ready_o;
wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
-
- buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+
+ wire [35:0] tx_err_data;
+ wire tx_err_src_rdy, tx_err_dst_rdy;
+
+ wire [31:0] router_debug;
+
+ packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
- .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+ .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
.wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
-
- .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+
.set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
- .status(status),.sys_int_o(buffer_int),
-
- .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
- .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
-
- // Write Interfaces
- .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
- .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
- .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
- .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
- // Read Interfaces
- .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
- .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
- .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
- .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
- );
- wire [31:0] status_enc;
- priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+ .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),
+
+ .status(status), .sys_int_o(buffer_int), .debug(router_debug),
+
+ .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+ .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o),
+ .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+ .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+
+ .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+ .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+ .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+ );
// /////////////////////////////////////////////////////////////////////////
// SPI -- Slave #2
@@ -427,23 +426,22 @@ module u2_core
cycle_count <= cycle_count + 1;
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = 32'd3;
+ localparam compat_num = 32'd4;
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-
- .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
- .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+ .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+ .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+ wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
@@ -459,37 +457,39 @@ module u2_core
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] udp_tx_data, udp_rx_data;
- wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
-
- udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+ wire [35:0] rx_f36_data, tx_f36_data;
+ wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
+
+ wire [18:0] _rx_f19_data;
+ wire _rx_f19_src_rdy, _rx_f19_dst_rdy;
+
+ //mac rx to eth input...
+ fifo19_rxrealign fifo19_rxrealign
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
- .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
- .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
- .debug(debug_udp) );
+ .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
+ .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
- wire [35:0] tx_err_data, udp1_tx_data;
- wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
-
- fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+ fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+ .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
+ .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
- fifo36_mux #(.prio(0)) mux_err_stream
- (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
- .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
- .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
- .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
-
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+ .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
.dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
+
+ //eth output to mac tx...
+ fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+ .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
+
+ fifo36_to_fifo19 eth_out_fifo36_to_fifo19
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
+ .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
+
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -727,7 +727,7 @@ module u2_core
.pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
.exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
.debug(debug_sync));
-
+
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
generated by cgit v1.2.3 (git 2.46.0) at 2025-11-04 03:15:56 +0000