4 files changed, 67 insertions, 3 deletions
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 2f6b5fde3..0e08b800e 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -13,6 +13,7 @@ else
 endif
 BASE_DIR = $(abspath ..)
 ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
 ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
 BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
 BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
@@ -26,12 +27,13 @@ all: bin
 proj: $(ISE_FILE)
 
 check: $(ISE_FILE)
+	$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf
 	$(ISE_HELPER) "Check Syntax"
 
 synth: $(ISE_FILE)
 	$(ISE_HELPER) "Synthesize - XST"
 
-bin: $(BIN_FILE)
+bin: check $(BIN_FILE)
 
 mcs: $(MCS_FILE)
 
diff --git a/usrp2/top/python/check_inout.py b/usrp2/top/python/check_inout.py
new file mode 100755
index 000000000..ff371d378
--- /dev/null
+++ b/usrp2/top/python/check_inout.py
@@ -0,0 +1,62 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+# Description:
+# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
+# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
+
+import sys
+import re
+
+if __name__=='__main__':
+  if len(sys.argv) == 2:
+    print "Usage: %s <top level Verilog file> <pin definition UCF>"
+    sys.exit(-1)
+
+  verilog_filename = sys.argv[1]
+  ucf_filename = sys.argv[2]
+
+  verilog_file = open(verilog_filename, 'r')
+  ucf_file = open(ucf_filename, 'r')
+
+  verilog_iolist = list()
+  ucf_iolist = list()
+
+  #read in all input, inout, and output declarations and compile a list
+  for line in verilog_file:
+    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
+      verilog_iolist.append(match)
+
+  for line in ucf_file:
+      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
+      if m is not None:
+        ucf_iolist.append(m.group(1))
+
+  #now find corresponding matches and error when you don't find one
+  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
+  err = False
+
+  for item in verilog_iolist:
+    if item not in ucf_iolist:
+      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+      err = True
+
+  if err:
+    sys.exit(-1)
+
+  print "No errors found."
+  sys.exit(0)
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index a9ff9413d..aee9e57bf 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -250,7 +250,7 @@ NET "PHY_INTn"  LOC = "L22"  ;
 NET "MDIO"  LOC = "K21"  ;
 NET "MDC"  LOC = "J23"  ;
 NET "PHY_RESETn"  LOC = "J22"  ;
-NET "ETH_LEd"  LOC = "H20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ETH_LED"  LOC = "H20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
 
 ## MIMO Interface
 NET "exp_time_out_p"  LOC = "Y14"  ;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index a0ba4d4cc..3641ce962 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -83,7 +83,7 @@ module u2plus
    output PHY_RESETn,
    output ETH_LED,
    
-   input POR,
+//   input POR,
    
    // Expansion
    input exp_time_in_p, input exp_time_in_n, // Diff