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-rw-r--r--control_lib/wb_1master.v318
-rwxr-xr-xtop/u2_core/u2_core.v145
2 files changed, 239 insertions, 224 deletions
diff --git a/control_lib/wb_1master.v b/control_lib/wb_1master.v
index e56ba1fb2..fb313efae 100644
--- a/control_lib/wb_1master.v
+++ b/control_lib/wb_1master.v
@@ -38,26 +38,40 @@
// Up to 8 slaves share a Wishbone Bus connection to 1 master
module wb_1master
- #(parameter s0_addr_w = 4, // slave 0 address decode width
- parameter s0_addr = 4'h0, // slave 0 address
- parameter s1_addr_w = 4 , // slave 1 address decode width
- parameter s1_addr = 4'h1, // slave 1 address
- parameter s215_addr_w = 8 , // slave 2 to slave 7 address decode width
- parameter s2_addr = 8'h92, // slave 2 address
- parameter s3_addr = 8'h93, // slave 3 address
- parameter s4_addr = 8'h94, // slave 4 address
- parameter s5_addr = 8'h95, // slave 5 address
- parameter s6_addr = 8'h96, // slave 6 address
- parameter s7_addr = 8'h97, // slave 7 address
- parameter s8_addr = 8'h98, // slave 7 address
- parameter s9_addr = 8'h99, // slave 7 address
- parameter s10_addr = 8'h9a, // slave 7 address
- parameter s11_addr = 8'h9b, // slave 7 address
- parameter s12_addr = 8'h9c, // slave 7 address
- parameter s13_addr = 8'h9d, // slave 7 address
- parameter s14_addr = 8'h9e, // slave 7 address
- parameter s15_addr = 8'h9f, // slave 7 address
-
+ #(parameter decode_w = 8, // address decode width
+ parameter s0_addr = 8'h0, // slave 0 address
+ parameter s0_mask = 8'h0, // slave 0 don't cares
+ parameter s1_addr = 8'h0, // slave 1 address
+ parameter s1_mask = 8'h0, // slave 1 don't cares
+ parameter s2_addr = 8'h0, // slave 2 address
+ parameter s2_mask = 8'h0, // slave 2 don't cares
+ parameter s3_addr = 8'h0, // slave 3 address
+ parameter s3_mask = 8'h0, // slave 3 don't cares
+ parameter s4_addr = 8'h0, // slave 4 address
+ parameter s4_mask = 8'h0, // slave 4 don't cares
+ parameter s5_addr = 8'h0, // slave 5 address
+ parameter s5_mask = 8'h0, // slave 5 don't cares
+ parameter s6_addr = 8'h0, // slave 6 address
+ parameter s6_mask = 8'h0, // slave 6 don't cares
+ parameter s7_addr = 8'h0, // slave 7 address
+ parameter s7_mask = 8'h0, // slave 7 don't cares
+ parameter s8_addr = 8'h0, // slave 8 address
+ parameter s8_mask = 8'h0, // slave 8 don't cares
+ parameter s9_addr = 8'h0, // slave 9 address
+ parameter s9_mask = 8'h0, // slave 9 don't cares
+ parameter sa_addr = 8'h0, // slave a address
+ parameter sa_mask = 8'h0, // slave a don't cares
+ parameter sb_addr = 8'h0, // slave b address
+ parameter sb_mask = 8'h0, // slave b don't cares
+ parameter sc_addr = 8'h0, // slave c address
+ parameter sc_mask = 8'h0, // slave c don't cares
+ parameter sd_addr = 8'h0, // slave d address
+ parameter sd_mask = 8'h0, // slave d don't cares
+ parameter se_addr = 8'h0, // slave e address
+ parameter se_mask = 8'h0, // slave e don't cares
+ parameter sf_addr = 8'h0, // slave f address
+ parameter sf_mask = 8'h0, // slave f don't cares
+
parameter dw = 32, // Data bus Width
parameter aw = 32, // Address bus Width
parameter sw = 4) // Number of Select Lines
@@ -188,71 +202,71 @@
input s9_err_i,
input s9_rty_i,
- input [dw-1:0] s10_dat_i,
- output [dw-1:0] s10_dat_o,
- output [aw-1:0] s10_adr_o,
- output [sw-1:0] s10_sel_o,
- output s10_we_o,
- output s10_cyc_o,
- output s10_stb_o,
- input s10_ack_i,
- input s10_err_i,
- input s10_rty_i,
+ input [dw-1:0] sa_dat_i,
+ output [dw-1:0] sa_dat_o,
+ output [aw-1:0] sa_adr_o,
+ output [sw-1:0] sa_sel_o,
+ output sa_we_o,
+ output sa_cyc_o,
+ output sa_stb_o,
+ input sa_ack_i,
+ input sa_err_i,
+ input sa_rty_i,
- input [dw-1:0] s11_dat_i,
- output [dw-1:0] s11_dat_o,
- output [aw-1:0] s11_adr_o,
- output [sw-1:0] s11_sel_o,
- output s11_we_o,
- output s11_cyc_o,
- output s11_stb_o,
- input s11_ack_i,
- input s11_err_i,
- input s11_rty_i,
+ input [dw-1:0] sb_dat_i,
+ output [dw-1:0] sb_dat_o,
+ output [aw-1:0] sb_adr_o,
+ output [sw-1:0] sb_sel_o,
+ output sb_we_o,
+ output sb_cyc_o,
+ output sb_stb_o,
+ input sb_ack_i,
+ input sb_err_i,
+ input sb_rty_i,
- input [dw-1:0] s12_dat_i,
- output [dw-1:0] s12_dat_o,
- output [aw-1:0] s12_adr_o,
- output [sw-1:0] s12_sel_o,
- output s12_we_o,
- output s12_cyc_o,
- output s12_stb_o,
- input s12_ack_i,
- input s12_err_i,
- input s12_rty_i,
+ input [dw-1:0] sc_dat_i,
+ output [dw-1:0] sc_dat_o,
+ output [aw-1:0] sc_adr_o,
+ output [sw-1:0] sc_sel_o,
+ output sc_we_o,
+ output sc_cyc_o,
+ output sc_stb_o,
+ input sc_ack_i,
+ input sc_err_i,
+ input sc_rty_i,
- input [dw-1:0] s13_dat_i,
- output [dw-1:0] s13_dat_o,
- output [aw-1:0] s13_adr_o,
- output [sw-1:0] s13_sel_o,
- output s13_we_o,
- output s13_cyc_o,
- output s13_stb_o,
- input s13_ack_i,
- input s13_err_i,
- input s13_rty_i,
+ input [dw-1:0] sd_dat_i,
+ output [dw-1:0] sd_dat_o,
+ output [aw-1:0] sd_adr_o,
+ output [sw-1:0] sd_sel_o,
+ output sd_we_o,
+ output sd_cyc_o,
+ output sd_stb_o,
+ input sd_ack_i,
+ input sd_err_i,
+ input sd_rty_i,
- input [dw-1:0] s14_dat_i,
- output [dw-1:0] s14_dat_o,
- output [aw-1:0] s14_adr_o,
- output [sw-1:0] s14_sel_o,
- output s14_we_o,
- output s14_cyc_o,
- output s14_stb_o,
- input s14_ack_i,
- input s14_err_i,
- input s14_rty_i,
+ input [dw-1:0] se_dat_i,
+ output [dw-1:0] se_dat_o,
+ output [aw-1:0] se_adr_o,
+ output [sw-1:0] se_sel_o,
+ output se_we_o,
+ output se_cyc_o,
+ output se_stb_o,
+ input se_ack_i,
+ input se_err_i,
+ input se_rty_i,
- input [dw-1:0] s15_dat_i,
- output [dw-1:0] s15_dat_o,
- output [aw-1:0] s15_adr_o,
- output [sw-1:0] s15_sel_o,
- output s15_we_o,
- output s15_cyc_o,
- output s15_stb_o,
- input s15_ack_i,
- input s15_err_i,
- input s15_rty_i
+ input [dw-1:0] sf_dat_i,
+ output [dw-1:0] sf_dat_o,
+ output [aw-1:0] sf_adr_o,
+ output [sw-1:0] sf_sel_o,
+ output sf_we_o,
+ output sf_cyc_o,
+ output sf_stb_o,
+ input sf_ack_i,
+ input sf_err_i,
+ input sf_rty_i
);
// ////////////////////////////////////////////////////////////////
@@ -278,22 +292,22 @@
128 : i_dat_s <= s7_dat_i;
256 : i_dat_s <= s8_dat_i;
512 : i_dat_s <= s9_dat_i;
- 1024 : i_dat_s <= s10_dat_i;
- 2048 : i_dat_s <= s11_dat_i;
- 4096 : i_dat_s <= s12_dat_i;
- 8192 : i_dat_s <= s13_dat_i;
- 16384 : i_dat_s <= s14_dat_i;
- 32768 : i_dat_s <= s15_dat_i;
+ 1024 : i_dat_s <= sa_dat_i;
+ 2048 : i_dat_s <= sb_dat_i;
+ 4096 : i_dat_s <= sc_dat_i;
+ 8192 : i_dat_s <= sd_dat_i;
+ 16384 : i_dat_s <= se_dat_i;
+ 32768 : i_dat_s <= sf_dat_i;
default : i_dat_s <= s0_dat_i;
endcase // case(ssel_dec)
assign {m0_ack_o, m0_err_o, m0_rty_o}
= {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
- s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i ,
+ s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
- s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i ,
+ s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
- s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i };
+ s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
// Slave output interfaces
assign s0_adr_o = m0_adr_i;
@@ -366,65 +380,85 @@
assign s9_cyc_o = m0_cyc_i;
assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];
- assign s10_adr_o = m0_adr_i;
- assign s10_sel_o = m0_sel_i;
- assign s10_dat_o = m0_dat_i;
- assign s10_we_o = m0_we_i;
- assign s10_cyc_o = m0_cyc_i;
- assign s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];
+ assign sa_adr_o = m0_adr_i;
+ assign sa_sel_o = m0_sel_i;
+ assign sa_dat_o = m0_dat_i;
+ assign sa_we_o = m0_we_i;
+ assign sa_cyc_o = m0_cyc_i;
+ assign sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];
- assign s11_adr_o = m0_adr_i;
- assign s11_sel_o = m0_sel_i;
- assign s11_dat_o = m0_dat_i;
- assign s11_we_o = m0_we_i;
- assign s11_cyc_o = m0_cyc_i;
- assign s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];
+ assign sb_adr_o = m0_adr_i;
+ assign sb_sel_o = m0_sel_i;
+ assign sb_dat_o = m0_dat_i;
+ assign sb_we_o = m0_we_i;
+ assign sb_cyc_o = m0_cyc_i;
+ assign sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];
- assign s12_adr_o = m0_adr_i;
- assign s12_sel_o = m0_sel_i;
- assign s12_dat_o = m0_dat_i;
- assign s12_we_o = m0_we_i;
- assign s12_cyc_o = m0_cyc_i;
- assign s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];
+ assign sc_adr_o = m0_adr_i;
+ assign sc_sel_o = m0_sel_i;
+ assign sc_dat_o = m0_dat_i;
+ assign sc_we_o = m0_we_i;
+ assign sc_cyc_o = m0_cyc_i;
+ assign sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];
- assign s13_adr_o = m0_adr_i;
- assign s13_sel_o = m0_sel_i;
- assign s13_dat_o = m0_dat_i;
- assign s13_we_o = m0_we_i;
- assign s13_cyc_o = m0_cyc_i;
- assign s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];
+ assign sd_adr_o = m0_adr_i;
+ assign sd_sel_o = m0_sel_i;
+ assign sd_dat_o = m0_dat_i;
+ assign sd_we_o = m0_we_i;
+ assign sd_cyc_o = m0_cyc_i;
+ assign sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];
- assign s14_adr_o = m0_adr_i;
- assign s14_sel_o = m0_sel_i;
- assign s14_dat_o = m0_dat_i;
- assign s14_we_o = m0_we_i;
- assign s14_cyc_o = m0_cyc_i;
- assign s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];
+ assign se_adr_o = m0_adr_i;
+ assign se_sel_o = m0_sel_i;
+ assign se_dat_o = m0_dat_i;
+ assign se_we_o = m0_we_i;
+ assign se_cyc_o = m0_cyc_i;
+ assign se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];
- assign s15_adr_o = m0_adr_i;
- assign s15_sel_o = m0_sel_i;
- assign s15_dat_o = m0_dat_i;
- assign s15_we_o = m0_we_i;
- assign s15_cyc_o = m0_cyc_i;
- assign s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];
+ assign sf_adr_o = m0_adr_i;
+ assign sf_sel_o = m0_sel_i;
+ assign sf_dat_o = m0_dat_i;
+ assign sf_we_o = m0_we_i;
+ assign sf_cyc_o = m0_cyc_i;
+ assign sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];
// Address decode logic
// WARNING -- must make sure these are mutually exclusive!
- assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr);
- assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr);
- assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s2_addr);
- assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s3_addr);
- assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s4_addr);
- assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s5_addr);
- assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s6_addr);
- assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s7_addr);
- assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s8_addr);
- assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s9_addr);
- assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s10_addr);
- assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s11_addr);
- assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s12_addr);
- assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s13_addr);
- assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s14_addr);
- assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s15_addr);
-
+
+
+ assign ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+ assign ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+ assign ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+ assign ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+ assign ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+ assign ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+ assign ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+ assign ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+ assign ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+ assign ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+ assign ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+ assign ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+ assign ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+ assign ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+ assign ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+ assign ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+ assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+ assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+ assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+ assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+ assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+ assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+ assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+ assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+ assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+ assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+ assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+ assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+ assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+ assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+ assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+ assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */
endmodule // wb_1master
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 363f7340e..1f78f6d3d 100755
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -168,57 +168,68 @@ module u2_core
wire [dw-1:0] m0_dat_o, m0_dat_i;
wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
- s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
- s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
- wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
- wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
- wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
- wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
- wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
- wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
- wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
- wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
-
- wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
- .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
- .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
- .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
- .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
+ s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+ sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
+ wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
+ wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
+ wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
+ wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
+ wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
+ wire m0_err, m0_rty;
+ wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
+
+ wb_1master #(.decode_w(6),
+ .s0_addr(6'b0000_00),.s0_mask(6'b100000),
+ .s1_addr(6'b1000_00),.s1_mask(6'b110000),
+ .s2_addr(6'b1100_00),.s2_mask(6'b111111),
+ .s3_addr(6'b1100_01),.s3_mask(6'b111111),
+ .s4_addr(6'b1100_10),.s4_mask(6'b111111),
+ .s5_addr(6'b1100_11),.s5_mask(6'b111111),
+ .s6_addr(6'b1101_00),.s6_mask(6'b111111),
+ .s7_addr(6'b1101_01),.s7_mask(6'b111111),
+ .s8_addr(6'b1101_10),.s8_mask(6'b111111),
+ .s9_addr(6'b1101_11),.s9_mask(6'b111111),
+ .sa_addr(6'b1110_00),.sa_mask(6'b111111),
+ .sb_addr(6'b1110_01),.sb_mask(6'b111111),
+ .sc_addr(6'b1110_10),.sc_mask(6'b111111),
+ .sd_addr(6'b1110_11),.sd_mask(6'b111111),
+ .se_addr(6'b1111_00),.se_mask(6'b111111),
+ .sf_addr(6'b1111_01),.sf_mask(6'b111111),
.dw(dw),.aw(aw),.sw(sw)) wb_1master
(.clk_i(wb_clk),.rst_i(wb_rst),
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
.s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
- .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+ .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
.s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
- .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+ .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
.s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
- .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+ .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
.s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
- .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+ .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
.s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
- .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+ .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
.s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
- .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+ .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
.s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
- .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+ .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
.s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
- .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+ .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
.s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
- .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+ .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
.s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
- .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
- .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
- .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
- .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
- .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
- .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
- .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
- .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
- .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
- .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
- .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
- .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) );
+ .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+ .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+ .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+ .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+ .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+ .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+ .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+ .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+ .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+ .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+ .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+ .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0) );
//////////////////////////////////////////////////////////////////////////////////////////
// Reset Controller
@@ -300,9 +311,6 @@ module u2_core
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
.flush_icache(flush_icache));
- assign s0_err = 1'b0;
- assign s0_rty = 1'b0;
-
setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(flush_icache));
@@ -324,7 +332,7 @@ module u2_core
buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
- .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+ .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
.stream_clk(dsp_clk), .stream_rst(dsp_rst),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
@@ -349,12 +357,10 @@ module u2_core
spi_top shared_spi
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
.wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
- .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
+ .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
.ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
.sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
- assign s2_rty = 1'b0;
-
// I2C -- Slave #3
i2c_master_top #(.ARST_LVL(1))
i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
@@ -365,8 +371,6 @@ module u2_core
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
assign s3_dat_i[31:8] = 24'd0;
- assign s3_err = 1'b0;
- assign s3_rty = 1'b0;
// GPIOs -- Slave #4
nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
@@ -374,8 +378,6 @@ module u2_core
.dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
.gpio( {io_tx,io_rx} ) );
- assign s4_err = 1'b0;
- assign s4_rty = 1'b0;
// Buffer Pool Status -- Slave #5
wb_readback_mux buff_pool_status
@@ -392,9 +394,6 @@ module u2_core
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
);
- assign s5_err = 1'b0;
- assign s5_rty = 1'b0;
-
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
@@ -412,9 +411,6 @@ module u2_core
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- assign s6_err = 1'b0;
- assign s6_rty = 1'b0;
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
@@ -422,8 +418,6 @@ module u2_core
.wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
.sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
- assign s7_err = 1'b0;
- assign s7_rty = 1'b0;
assign s7_dat_i = 32'd0;
// Output control lines
@@ -470,8 +464,6 @@ module u2_core
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
.irq(irq) );
- assign s8_err = 0;
- assign s8_rty = 0;
// /////////////////////////////////////////////////////////////////////////
// Master Timer, Slave #9
@@ -482,22 +474,17 @@ module u2_core
.cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
.we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
.sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
- assign s9_err = 0;
- assign s9_rty = 0;
// /////////////////////////////////////////////////////////////////////////
// UART, Slave #10
simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries
(.clk_i(wb_clk),.rst_i(wb_rst),
- .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
- .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+ .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+ .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
.rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
.tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
- assign s10_err = 0;
- assign s10_rty = 0;
-
// /////////////////////////////////////////////////////////////////////////
// ATR Controller, Slave #11
@@ -508,11 +495,9 @@ module u2_core
atr_controller atr_controller
(.clk_i(wb_clk),.rst_i(wb_rst),
- .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
- .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
- .run_rx(run_rx_d1),.run_tx(run_tx), .ctrl_lines(atr_lines) );
- assign s11_err = 0;
- assign s11_rty = 0;
+ .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+ .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+ .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
// //////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
@@ -526,14 +511,12 @@ module u2_core
wire pps_o;
time_sync time_sync
(.wb_clk_i(wb_clk),.rst_i(wb_rst),
- .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
- .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+ .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
+ .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
.sys_clk_i(dsp_clk),.master_time_o(master_time),
.pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
.int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
- assign s12_err = 0;
- assign s12_rty = 0;
// /////////////////////////////////////////////////////////////////////////
// SD Card Reader / Writer, Slave #13
@@ -541,11 +524,10 @@ module u2_core
sd_spi_wb sd_spi_wb
(.clk(wb_clk),.rst(wb_rst),
.sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
- .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
- .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
- .wb_ack_o(s13_ack) );
- assign s13_err = 0;
- assign s13_rty = 0;
+ .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
+ .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i),
+ .wb_ack_o(sd_ack) );
+
// /////////////////////////////////////////////////////////////////////////
// DSP
wire [31:0] sample_rx, sample_tx;
@@ -615,8 +597,8 @@ module u2_core
wb_bridge_16_32 bridge
(.wb_clk(wb_clk),.wb_rst(wb_rst),
- .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
- .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+ .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
+ .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
.B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
.B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
@@ -628,7 +610,6 @@ module u2_core
.sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
.sram_mode(),.sram_zz() );
- assign s14_err = 0; assign s14_rty = 0;
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 10:49:22 +0000