diff options
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx_tb.v | 68 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_frontend_tb.v | 45 |
2 files changed, 113 insertions, 0 deletions
diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v new file mode 100644 index 000000000..991b3a850 --- /dev/null +++ b/usrp2/sdr_lib/dsp_core_rx_tb.v @@ -0,0 +1,68 @@ + +`timescale 1ns/1ns +module dsp_core_rx_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("dsp_core_rx_tb.vcd"); + initial $dumpvars(0,dsp_core_rx_tb); + + reg [17:0] adc_in; + wire [15:0] adc_out_i, adc_out_q; + + always @(posedge clk) + begin + if(adc_in[17]) + $write("-%d,",-adc_in); + else + $write("%d,",adc_in); + if(adc_out_i[15]) + $write("-%d\n",-adc_out_i); + else + $write("%d\n",adc_out_i); + end + + reg run; + reg set_stb; + reg [7:0] set_addr; + reg [31:0] set_data; + + dsp_core_rx #(.BASE(0)) dsp_core_rx + (.clk(clk),.rst(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_i(adc_in), .adc_ovf_i(0), + .adc_q(0), .adc_ovf_q(0), + .sample({adc_out_i,adc_out_q}), + .run(run), .strobe(), .debug()); + + initial + begin + run <= 0; + @(negedge rst); + @(posedge clk); + set_addr <= 1; + set_data <= {16'd1024,16'd1024}; + set_stb <= 1; + @(posedge clk); + set_addr <= 2; + set_data <= 8; + set_stb <= 1; + @(posedge clk); + set_stb <= 0; + @(posedge clk); + run <= 1; + end + + always @(posedge clk) + if(rst) + adc_in <= 0; + else + adc_in <= adc_in + 4; + //adc_in <= (($random % 473) + 23)/4; + +endmodule // dsp_core_rx_tb diff --git a/usrp2/sdr_lib/rx_frontend_tb.v b/usrp2/sdr_lib/rx_frontend_tb.v new file mode 100644 index 000000000..487b72687 --- /dev/null +++ b/usrp2/sdr_lib/rx_frontend_tb.v @@ -0,0 +1,45 @@ + +`timescale 1ns/1ns +module rx_frontend_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("rx_frontend_tb.vcd"); + initial $dumpvars(0,rx_frontend_tb); + + reg [15:0] adc_in; + wire [17:0] adc_out; + + always @(posedge clk) + begin + if(adc_in[13]) + $write("-%d,",-adc_in); + else + $write("%d,",adc_in); + if(adc_out[13]) + $write("-%d\n",-adc_out); + else + $write("%d\n",adc_out); + end + + rx_frontend #(.BASE(0)) rx_frontend + (.clk(clk),.rst(rst), + .set_stb(0),.set_addr(0),.set_data(0), + .adc_a(adc_in), .adc_ovf_a(0), + .adc_b(0), .adc_ovf_b(0), + .i_out(adc_out),.q_out(), + .run(), .debug()); + + always @(posedge clk) + if(rst) + adc_in <= 0; + else + adc_in <= adc_in + 4; + //adc_in <= (($random % 473) + 23)/4; + +endmodule // rx_frontend_tb |