diff options
| -rw-r--r-- | usrp2/control_lib/bootram.v | 12 | ||||
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 648ccc9ed..5e527de90 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -5,7 +5,7 @@ // Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1 module bootram - (input clk, + (input clk, input reset, input [12:0] if_adr, output [31:0] if_data, @@ -23,14 +23,14 @@ module bootram wire [3:0] WEB; assign if_data = if_adr[12] ? (if_adr[11] ? DOA3 : DOA2) : (if_adr[11] ? DOA1 : DOA0); - assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOA3 : DOA2) : (dwb_adr_i[11] ? DOA1 : DOA0); + assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); always @(posedge clk) - if(dwb_stb_i & ~dwb_ack_o) - dwb_ack_o <= 1; - else + if(reset) dwb_ack_o <= 0; - + else + dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; + assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 579e946e8..189a342cd 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -273,7 +273,7 @@ module u2plus_core wire [31:0] if_dat_boot, if_dat_main; assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; - bootram bootram(.clk(wb_clk), + bootram bootram(.clk(wb_clk), .reset(wb_rst), .if_adr(if_adr[12:0]), .if_data(if_dat_boot), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); |