diff options
| -rw-r--r-- | fpga/usrp2/control_lib/bootram.v | 2 | ||||
| -rwxr-xr-x | fpga/usrp2/sdr_lib/cic_decim.v | 8 | ||||
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e_core.v | 8 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/Makefile | 23 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus.v | 8 | ||||
| -rw-r--r-- | fpga/usrp2/top/N2x0/u2plus_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/USRP2/u2_core.v | 2 |
8 files changed, 41 insertions, 16 deletions
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index 249a09814..fb7bd46c8 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -82,7 +82,7 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input + .DIA(32'hffffffff), // Port A 32-bit Data Input .DIPA(4'd0), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input diff --git a/fpga/usrp2/sdr_lib/cic_decim.v b/fpga/usrp2/sdr_lib/cic_decim.v index 9a03081b0..e6b6e9590 100755 --- a/fpga/usrp2/sdr_lib/cic_decim.v +++ b/fpga/usrp2/sdr_lib/cic_decim.v @@ -45,10 +45,10 @@ module cic_decim ext_input (.in(signal_in),.out(signal_in_ext)); always @(posedge clock) - if(reset) + if(~enable) for(i=0;i<N;i=i+1) integrator[i] <= 0; - else if (enable && strobe_in) + else if (strobe_in) begin integrator[0] <= integrator[0] + signal_in_ext; for(i=1;i<N;i=i+1) @@ -56,7 +56,7 @@ module cic_decim end always @(posedge clock) - if(reset) + if(~enable) begin sampler <= 0; for(i=0;i<N;i=i+1) @@ -65,7 +65,7 @@ module cic_decim differentiator[i] <= 0; end end - else if (enable && strobe_out) + else if (strobe_out) begin sampler <= integrator[N-1]; differentiator[0] <= sampler; diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 4683f653c..6a80eba76 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -142,7 +142,7 @@ module u1plus_core // RX ADC Frontend, does IQ Balance, DC Offset, muxing wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p - wire run_rx, run_rx0, run_rx1; + wire run_rx0, run_rx1; rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend (.clk(wb_clk),.rst(wb_rst), @@ -421,7 +421,7 @@ module u1plus_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + .run_rx(run_rx0 | run_rx1), .run_tx(run_tx), .ctrl_lines(atr_lines)); // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index c4fc16444..8cd51fc10 100644 --- a/fpga/usrp2/top/E1x0/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -148,7 +148,7 @@ module u1e_core // RX ADC Frontend, does IQ Balance, DC Offset, muxing wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p - wire run_rx, run_rx0, run_rx1; + wire run_rx0, run_rx1; rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend (.clk(wb_clk),.rst(wb_rst), @@ -345,7 +345,7 @@ module u1e_core assign test_ctrl = xfer_rate[11:8]; assign test_rate = xfer_rate[7:0]; - assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; + assign { debug_led[3:0] } = ~{run_rx0 | run_rx1,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : @@ -462,7 +462,7 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + .run_rx(run_rx0 | run_rx1), .run_tx(run_tx), .ctrl_lines(atr_lines)); // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 @@ -509,7 +509,7 @@ module u1e_core */ assign debug = debug_gpmc; - assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx0, tx_i[11:0]}, + assign debug_gpio_0 = { {run_tx, 2'b0, strobe_rx0, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vt; diff --git a/fpga/usrp2/top/N2x0/Makefile b/fpga/usrp2/top/N2x0/Makefile new file mode 100644 index 000000000..b6a3d9624 --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile @@ -0,0 +1,23 @@ +# +# Copyright 2011 Ettus Research LLC +# + +all: N200R3 N210R3 N200R4 N210R4 + find -name "*.twr" | xargs grep constraint | grep met + +clean: + rm -rf build* + +N200R3: + make -f Makefile.$@ bin + +N210R3: + make -f Makefile.$@ bin + +N200R4: + make -f Makefile.$@ bin + +N210R4: + make -f Makefile.$@ bin + +.PHONY: all clean diff --git a/fpga/usrp2/top/N2x0/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v index be6cdeeca..be1f355d2 100644 --- a/fpga/usrp2/top/N2x0/u2plus.v +++ b/fpga/usrp2/top/N2x0/u2plus.v @@ -188,13 +188,15 @@ module u2plus .out({adc_a_inv,adc_b})); assign adc_a = ~adc_a_inv; `else - reg [13:0] adc_a, adc_b; + reg [13:0] adc_a, adc_b, adc_a_pre, adc_b_pre; always @(posedge dsp_clk) begin - adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + adc_a_pre <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; - adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + adc_b_pre <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + adc_a <= ~adc_a_pre; //Note: A must be inverted, but not B + adc_b <= adc_b_pre; end `endif // !`ifdef LVDS diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index f01306f97..9906daa5f 100644 --- a/fpga/usrp2/top/N2x0/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -427,7 +427,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd1}; //major, minor + localparam compat_num = {16'd7, 16'd2}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index ee1116eac..d54d16cf0 100644 --- a/fpga/usrp2/top/USRP2/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -432,7 +432,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd1}; //major, minor + localparam compat_num = {16'd7, 16'd2}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), |