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-rw-r--r--usrp2/gpif/gpif.v78
-rw-r--r--usrp2/gpif/gpif_rd.v69
-rw-r--r--usrp2/gpif/gpif_wr.v36
-rw-r--r--usrp2/top/u1plus/u1plus_core.v4
4 files changed, 125 insertions, 62 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 789e22e98..bcb33eb4d 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -23,16 +23,18 @@ module gpif
wire WR = gpif_ctl[0];
wire RD = gpif_ctl[1];
wire OE = gpif_ctl[2];
- wire have_space, have_pkt_rdy;
+ wire EP = gpif_ctl[3];
+
+ wire CF, CE, DF, DE;
+
+ assign gpif_rdy = { CF, CE, DF, DE };
+
wire [15:0] gpif_dat_out;
assign gpif_dat = OE ? gpif_dat_out : 16'bz;
- assign gpif_rdy[0] = have_space;
- assign gpif_rdy[1] = have_pkt_rdy;
-
wire [15:0] gpif_d_copy = gpif_d;
- assign debug0 = {11'd0, WR, RD, OE, have_space, have_pkt_rdy, gpif_d_copy};
+ assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] };
assign debug1 = 32'd0;
// ////////////////////////////////////////////////////////////////////
@@ -40,16 +42,20 @@ module gpif
wire [18:0] tx19_data;
wire tx19_src_rdy, tx19_dst_rdy;
- wire [35:0] tx36_data, tx36b_data, tx36c_data;
- wire tx36_src_rdy, tx36_dst_rdy, tx36b_src_rdy, tx36b_dst_rdy, tx36c_src_rdy, tx36c_dst_rdy;
- wire [35:0] ctrl_data;
+ wire [35:0] tx36_data;
+ wire tx36_src_rdy, tx36_dst_rdy;
+
+ wire [18:0] ctrl;
wire ctrl_src_rdy, ctrl_dst_rdy;
gpif_wr gpif_wr
(.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
- .gpif_data(gpif_d), .gpif_wr(WR), .have_space(have_space),
+ .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP),
+ .gpif_full_d(DF), .gpif_full_c(CF),
+
.sys_clk(fifo_clk), .sys_rst(fifo_rst),
- .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy),
+ .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy),
+ .ctrl_o(ctrl), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy),
.debug() );
fifo19_to_fifo36 #(.LE(1)) f19_to_f36
@@ -57,48 +63,26 @@ module gpif
.f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy),
.f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
- fifo_short #(.WIDTH(36)) tx_sfifo
- (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
- .dataout(tx36b_data), .src_rdy_o(tx36b_src_rdy), .dst_rdy_i(tx36b_dst_rdy));
-
- fifo36_demux #(.match_data(32'h1000_0000), .match_mask(32'hF000_0000)) tx_demux
- (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .data_i(tx36b_data), .src_rdy_i(tx36b_src_rdy), .dst_rdy_o(tx36b_dst_rdy),
- .data0_o(ctrl_data), .src0_rdy_o(ctrl_src_rdy), .dst0_rdy_i(ctrl_dst_rdy),
- .data1_o(tx36c_data), .src1_rdy_o(tx36c_src_rdy), .dst1_rdy_i(tx36c_dst_rdy));
-
fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .datain(tx36c_data), .src_rdy_i(tx36c_src_rdy), .dst_rdy_o(tx36c_dst_rdy),
+ .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
.dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
// ////////////////////////////////////////////////////////////////////
// RX Side
- wire [35:0] rx36_data, rx36b_data, rx36c_data;
- wire rx36_src_rdy, rx36_dst_rdy, rx36b_src_rdy, rx36b_dst_rdy, rx36c_src_rdy, rx36c_dst_rdy;
+ wire [35:0] rx36_data;
+ wire rx36_src_rdy, rx36_dst_rdy;
wire [18:0] rx19_data;
wire rx19_src_rdy, rx19_dst_rdy;
- wire [35:0] resp_data;
+ wire [18:0] resp_data;
wire resp_src_rdy, resp_dst_rdy;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
- .dataout(rx36c_data), .src_rdy_o(rx36c_src_rdy), .dst_rdy_i(rx36c_dst_rdy));
-
- fifo36_mux #(.prio(1)) rx_mux
- (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .data0_i(resp_data), .src0_rdy_i(resp_src_rdy), .dst0_rdy_o(resp_dst_rdy),
- .data1_i(rx36c_data), .src1_rdy_i(rx36c_src_rdy), .dst1_rdy_o(rx36c_dst_rdy),
- .data_o(rx36b_data), .src_rdy_o(rx36b_src_rdy), .dst_rdy_i(rx36b_dst_rdy));
-
- fifo_short #(.WIDTH(36)) rx_sfifo
- (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
- .datain(rx36b_data), .src_rdy_i(rx36b_src_rdy), .dst_rdy_o(rx36b_dst_rdy),
.dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
-
+
fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness?
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
@@ -106,13 +90,17 @@ module gpif
gpif_rd gpif_rd
(.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
- .gpif_data(gpif_dat_out), .gpif_rd(RD), .have_pkt_rdy(have_pkt_rdy),
+ .gpif_data(gpif_dat_out), .gpif_rd(RD), .gpif_ep(EP),
+ .gpif_empty_d(DE), .gpif_empty_c(CE),
+
.sys_clk(fifo_clk), .sys_rst(fifo_rst),
- .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy));
+ .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy),
+ .resp_i(resp), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy),
+ .debug() );
// ////////////////////////////////////////////////////////////////////
// FIFO to Wishbone interface
-
+/*
fifo_to_wb fifo_to_wb
(.clk(fifo_clk), .reset(fifo_rst), .clear(0),
.data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
@@ -120,5 +108,15 @@ module gpif
.wb_adr_o(), .wb_dat_mosi(), .wb_dat_miso(),
.wb_sel_o(), .wb_cyc_o(), .wb_stb_o(), .wb_we_o(), .wb_ack_i(),
.debug0(), .debug1());
+ */
+
+ // Loopback for testing
+ assign resp = ctrl;
+ assign resp_src_rdy = ctrl_src_rdy;
+ assign ctrl_dst_rdy = resp_src_rdy;
+
+ //assign rx_data_i = tx_data_o;
+ //assign rx_src_rdy_i = tx_src_rdy_o;
+ //assign tx_dst_rdy_i = rx_dst_rdy_o;
endmodule // gpif
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v
index a3167da16..7581592cb 100644
--- a/usrp2/gpif/gpif_rd.v
+++ b/usrp2/gpif/gpif_rd.v
@@ -1,21 +1,19 @@
module gpif_rd
(input gpif_clk, input gpif_rst,
- output [15:0] gpif_data, input gpif_rd, output reg have_pkt_rdy,
-
+ output [15:0] gpif_data, input gpif_rd, input gpif_ep,
+ output reg gpif_empty_d, output reg gpif_empty_c,
+
input sys_clk, input sys_rst,
- input [18:0] data_i, input src_rdy_i, output dst_rdy_o
+ input [18:0] data_i, input src_rdy_i, output dst_rdy_o,
+ input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o,
+ output [31:0] debug
);
- wire [15:0] rxfifolevel;
- wire [15:0] data_o;
+ wire [17:0] data_o;
wire rx_full;
- // USB Read Side of FIFO
- always @(negedge gpif_clk)
- have_pkt_rdy <= (rxfifolevel >= 256); // FIXME make this more robust
-
- // 257 Bug Fix
+ // 33/257 Bug Fix
reg [8:0] read_count;
always @(negedge gpif_clk)
if(gpif_rst)
@@ -25,19 +23,62 @@ module gpif_rd
else
read_count <= 0;
+ // Data Path
wire [17:0] data_int;
wire src_rdy_int, dst_rdy_int;
-
fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk
(.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
.rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
.arst(sys_rst));
- fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo
+ // FIXME -- handle short packets
+ wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8];
+
+ fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo
(.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
.datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
- .dataout(data_o), .src_rdy_o(), .dst_rdy_i(gpif_rd & ~read_count[8]), .occupied(rxfifolevel));
+ .dataout(data_o), .src_rdy_o(), .dst_rdy_i(send_data_line), .occupied());
- assign gpif_data = data_o[15:0];
+ reg [7:0] packet_count;
+ always @(negedge gpif_clk)
+ if(gpif_rst)
+ packet_count <= 0;
+ else
+ if(src_rdy_int & dst_rdy_int & data_int[17]) // eop
+ if(~(send_data_line & data_o[16]))
+ packet_count <= packet_count + 1;
+ else
+ ;
+ else
+ if(send_data_line & data_o[16])
+ packet_count <= packet_count - 1;
+
+ always @(negedge gpif_clk)
+ if(gpif_rst)
+ gpif_empty_d <= 1;
+ else
+ gpif_empty_d <= ~|packet_count;
+
+ // Response Path
+ wire [15:0] resp_fifolevel;
+ wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4];
+ wire [17:0] resp_o;
+
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk
+ (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(),
+ .rclk(~gpif_clk), .dataout(resp_o),
+ .src_rdy_o(), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel),
+ .arst(sys_rst));
+
+ // FIXME -- handle short packets
+
+ always @(negedge gpif_clk)
+ if(gpif_rst)
+ gpif_empty_c <= 1;
+ else
+ gpif_empty_c <= resp_fifolevel < 16;
+
+ // Output Mux
+ assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0];
endmodule // gpif_rd
diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v
index 6a73d1721..4c6ee9efc 100644
--- a/usrp2/gpif/gpif_wr.v
+++ b/usrp2/gpif/gpif_wr.v
@@ -1,18 +1,20 @@
module gpif_wr
(input gpif_clk, input gpif_rst,
- input [15:0] gpif_data, input gpif_wr,
- output reg have_space,
+ input [15:0] gpif_data, input gpif_wr, input gpif_ep,
+ output reg gpif_full_d, output reg gpif_full_c,
input sys_clk, input sys_rst,
output [18:0] data_o, output src_rdy_o, input dst_rdy_i,
+ output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i,
output [31:0] debug );
- reg wr_reg;
+ reg wr_reg, ep_reg;
reg [15:0] gpif_data_reg;
always @(posedge gpif_clk)
begin
+ ep_reg <= gpif_ep;
wr_reg <= gpif_wr;
gpif_data_reg <= gpif_data;
end
@@ -29,20 +31,25 @@ module gpif_wr
reg sop;
wire eop = (write_count == 255);
+ wire eop_ctrl = (write_count == 15);
always @(posedge gpif_clk)
sop <= gpif_wr & ~wr_reg;
+ // Data Path
wire [15:0] fifo_space;
always @(posedge gpif_clk)
- have_space <= fifo_space > 256;
+ if(gpif_rst)
+ gpif_full_d <= 1;
+ else
+ gpif_full_d <= fifo_space < 256;
wire [17:0] data_int;
wire src_rdy_int, dst_rdy_int;
-
+
fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo
(.clk(gpif_clk), .reset(gpif_rst), .clear(0),
- .datain({eop,sop,gpif_data_reg}), .src_rdy_i(wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
+ .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space),
.dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk
@@ -51,5 +58,22 @@ module gpif_wr
.arst(sys_rst));
assign data_o[18] = 0;
+
+ // Control Path
+ wire [15:0] ctrl_fifo_space;
+ always @(posedge gpif_clk)
+ if(gpif_rst)
+ gpif_full_c <= 1;
+ else
+ gpif_full_c <= ctrl_fifo_space < 16;
+
+ fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) ctrl_fifo_2clk
+ (.wclk(gpif_clk), .datain({eop_ctrl,sop,gpif_data_reg}),
+ .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space),
+ .rclk(sys_clk), .dataout(ctrl_o[17:0]),
+ .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(),
+ .arst(sys_rst));
+
+ assign ctrl_o[18] = 0;
endmodule // gpif_wr
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index b52515610..9dca0031b 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -1,8 +1,8 @@
-//`define LOOPBACK 1
+`define LOOPBACK 1
//`define TIMED 1
-`define DSP 1
+//`define DSP 1
module u1plus_core
(input clk_fpga, input rst_fpga,
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 10:58:30 +0000