diff options
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 23 | ||||
| -rw-r--r-- | usrp2/vrt/gen_context_pkt.v | 7 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 8 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_control.v | 9 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_deframer.v | 2 |
5 files changed, 25 insertions, 24 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index ec973df8d..3c31d33a9 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -162,6 +162,7 @@ module u2_core wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; @@ -660,14 +661,17 @@ module u2_core wire [35:0] tx_data; wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; + wire clear_tx; + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 - ( - .int_clk(dsp_clk), + (.int_clk(dsp_clk), .ext_clk(clk_to_mac), -// .ext_clk(wb_clk), - .rst(dsp_rst), + .rst(dsp_rst | clear_tx), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), .RAM_D_poe(RAM_D_poe), @@ -679,15 +683,14 @@ module u2_core .RAM_CE1n(RAM_CE1n), // .datain({rd1_flags,rd1_dat}), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), // WRITE - .dst_rdy_o(rd1_ready_i), // not FULL + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), // .dataout(tx_data), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), // not EMPTY + .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), - .debug2(debug_extfifo2) - ); + .debug2(debug_extfifo2) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), @@ -702,8 +705,6 @@ module u2_core .underrun(underrun), .run(run_tx), .debug(debug_vt)); - assign dsp_rst = wb_rst; - // /////////////////////////////////////////////////////////////////////////////////// // SERDES diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0eb035f3e..efc170743 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -38,9 +38,10 @@ module gen_context_pkt stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; - + + // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe always @(posedge clk) - if(reset | clear) + if(reset) begin ctxt_state <= CTXT_IDLE; seqno <= 0; @@ -84,7 +85,7 @@ module gen_context_pkt endcase // case (ctxt_state) fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(clear), + (.clk(clk), .reset(reset), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); assign data_o[35:34] = 2'b00; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 00da4c6e1..21e826f1c 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -33,7 +33,11 @@ module vita_tx_chain assign underrun = error & ~(error_code == 1); assign message = error_code; - + + setting_reg #(.my_addr(BASE_CTRL+1)) sr + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_vita)); + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); @@ -88,7 +92,7 @@ module vita_tx_chain assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages - (.clk(clk), .reset(reset), .clear(clear_vita), + (.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 936762212..eb41c54c0 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -58,11 +58,6 @@ module vita_tx_control reg [2:0] ibs_state; - wire clear_state; - setting_reg #(.my_addr(BASE+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -74,7 +69,7 @@ module vita_tx_control reg send_error; always @(posedge clk) - if(reset | clear_state) + if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; @@ -163,7 +158,7 @@ module vita_tx_control assign error = send_error; always @(posedge clk) - if(reset) + if(reset | clear) packet_consumed <= 0; else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 7fb8e3893..7697be367 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -80,7 +80,7 @@ module vita_tx_deframer wire fifo_space; always @(posedge clk) - if(reset | clear_seqnum) + if(reset | clear | clear_seqnum) begin seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; |