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-rw-r--r--usrp2/fifo/packet_generator.v20
-rw-r--r--usrp2/fifo/packet_generator32.v2
-rw-r--r--usrp2/fifo/packet_verifier.v2
-rw-r--r--usrp2/gpmc/gpmc_async.v94
-rw-r--r--usrp2/top/u1e/u1e_core.v75
5 files changed, 112 insertions, 81 deletions
diff --git a/usrp2/fifo/packet_generator.v b/usrp2/fifo/packet_generator.v
index a751fdfb1..bbcab6db2 100644
--- a/usrp2/fifo/packet_generator.v
+++ b/usrp2/fifo/packet_generator.v
@@ -2,7 +2,8 @@
module packet_generator
(input clk, input reset, input clear,
- output reg [7:0] data_o, output sof_o, output eof_o,
+ output reg [7:0] data_o, output sof_o, output eof_o,
+ input [127:0] header,
output src_rdy_o, input dst_rdy_i);
localparam len = 32'd2000;
@@ -40,6 +41,23 @@ module packet_generator
5 : data_o <= seq[23:16];
6 : data_o <= seq[15:8];
7 : data_o <= seq[7:0];
+ 8 : data_o <= header[7:0];
+ 9 : data_o <= header[15:8];
+ 10 : data_o <= header[23:16];
+ 11 : data_o <= header[31:24];
+ 12 : data_o <= header[39:32];
+ 13 : data_o <= header[47:40];
+ 14 : data_o <= header[55:48];
+ 15 : data_o <= header[63:56];
+ 16 : data_o <= header[71:64];
+ 17 : data_o <= header[79:72];
+ 18 : data_o <= header[87:80];
+ 19 : data_o <= header[95:88];
+ 20 : data_o <= header[103:96];
+ 21 : data_o <= header[111:104];
+ 22 : data_o <= header[119:112];
+ 23 : data_o <= header[127:120];
+
32'hFFFF_FFFC : data_o <= crc_out[31:24];
32'hFFFF_FFFD : data_o <= crc_out[23:16];
32'hFFFF_FFFE : data_o <= crc_out[15:8];
diff --git a/usrp2/fifo/packet_generator32.v b/usrp2/fifo/packet_generator32.v
index 6f8004964..1dc57191d 100644
--- a/usrp2/fifo/packet_generator32.v
+++ b/usrp2/fifo/packet_generator32.v
@@ -2,6 +2,7 @@
module packet_generator32
(input clk, input reset, input clear,
+ input [127:0] header,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
wire [7:0] ll_data;
@@ -10,6 +11,7 @@ module packet_generator32
packet_generator pkt_gen
(.clk(clk), .reset(reset), .clear(clear),
.data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+ .header(header),
.src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
ll8_to_fifo36 ll8_to_f36
diff --git a/usrp2/fifo/packet_verifier.v b/usrp2/fifo/packet_verifier.v
index b49ad1bbb..21a4c136e 100644
--- a/usrp2/fifo/packet_verifier.v
+++ b/usrp2/fifo/packet_verifier.v
@@ -18,7 +18,7 @@ module packet_verifier
reg [31:0] length;
wire first_byte, last_byte;
reg second_byte, last_byte_d1;
-
+ wire match_crc;
wire calc_crc = src_rdy_i & dst_rdy_o;
crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i),
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 23bad56ae..b2c91dfbc 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -1,7 +1,9 @@
//////////////////////////////////////////////////////////////////////////////////
module gpmc_async
- #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+ #(parameter TXFIFOSIZE = 11,
+ parameter RXFIFOSIZE = 11,
+ parameter BUSDEBUG = 1)
(// GPMC signals
input arst,
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -70,9 +72,9 @@ module gpmc_async
.f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
.datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
- .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+ .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy));
// ////////////////////////////////////////////
// RX Data Path
@@ -85,8 +87,8 @@ module gpmc_async
wire dummy;
fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
.dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
@@ -126,5 +128,87 @@ module gpmc_async
.wb_ack_i(wb_ack_i) );
assign debug = pkt_count;
+
+ // ////////////////////////////////////////////
+ // Test support, traffic generator, loopback, etc.
+
+ // RX side muxes test data into the same stream
+ wire [35:0] timedrx_data, loopbackrx_data, testrx_data, rx_data;
+ wire [35:0] timedtx_data, loopbacktx_data, testtx_data, tx_data;
+ wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
+ testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy;
+ wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
+ testtx_src_rdy, testtx_dst_rdy, tx_src_rdy, tx_dst_rdy;
+ wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
+
+ wire [31:0] total, crc_err, seq_err, len_err;
+ wire [7:0] rx_rate, tx_rate;
+ wire rx_enable, tx_enable;
+ wire underrun, overrun;
+ wire sel_testtx, sel_loopbacktx;
+
+ fifo36_mux rx_test_mux_lvl_1
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
+ .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
+ .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
+
+ fifo36_mux rx_test_mux_lvl_2
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
+ .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
+ .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+ fifo_short #(.WIDTH(36)) loopback_fifo
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
+ .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
+ .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
+ // Crossbar used as a demux for switching TX stream to main DSP or to test logic
+ crossbar36 tx_crossbar_lvl_1
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .cross(sel_testtx),
+ .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
+ .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input
+ .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
+ .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
+
+ crossbar36 tx_crossbar_lvl_2
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .cross(sel_loopbacktx),
+ .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
+ .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input
+ .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
+ .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
+
+ // Fixed rate TX traffic consumer
+ fifo_pacer tx_pacer
+ (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable),
+ .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
+ .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
+ .underrun(underrun), .overrun());
+
+ packet_verifier32 pktver32
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
+ .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+ // Fixed rate RX traffic generator
+ packet_generator32 pktgen32
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .header({len_err,seq_err,crc_err,total}),
+ .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
+
+ fifo_pacer rx_pacer
+ (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable),
+ .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
+ .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
+ .underrun(), .overrun(overrun));
+
+ // FIXME -- hook up crossbar controls
+ // FIXME -- collect error stats
+ // FIXME -- set rates and enables on pacers
+ // FIXME -- make sure packet completes before we shutoff
+ // FIXME -- handle overrun and underrun
+
endmodule // gpmc_async
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7d5924bea..4f5a3e112 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,9 +1,5 @@
-//`define LOOPBACK 1
-//`define TIMED 1
-`define DSP 1
-
module u1e_core
(input clk_fpga, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -117,56 +113,6 @@ module u1e_core
wire rx_eof = rx_data[33];
wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
-`ifdef LOOPBACK
- wire [7:0] WHOAMI = 1;
-
- fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
- .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
- assign tx_underrun = 0;
- assign rx_overrun = 0;
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // LOOPBACK
-
-`ifdef TIMED
- wire [7:0] WHOAMI = 2;
-
- // TX side
- wire tx_enable;
-
- fifo_pacer tx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
- .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
- .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
- .underrun(tx_underrun), .overrun());
-
- packet_verifier32 pktver32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
- .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
- // RX side
- wire rx_enable;
-
- packet_generator32 pktgen32
- (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
- .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
-
- fifo_pacer rx_pacer
- (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
- .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
- .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
- .underrun(), .overrun(rx_overrun));
-
- wire run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // `ifdef TIMED
-
-`ifdef DSP
- wire [7:0] WHOAMI = 0;
-
wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug;
// /////////////////////////////////////////////////////////////////////////
@@ -231,23 +177,6 @@ module u1e_core
assign tx_i = tx_i_int[15:2];
assign tx_q = tx_q_int[15:2];
-`else // !`ifdef DSP
- // Dummy DSP signal generator for test purposes
- wire [23:0] tx_i_int, tx_q_int;
- wire [23:0] freq = {reg_test,8'd0};
- reg [23:0] phase;
-
- always @(posedge wb_clk)
- phase <= phase + freq;
-
- cordic_z24 #(.bitwidth(24)) tx_cordic
- (.clock(wb_clk), .reset(wb_rst), .enable(1),
- .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
-
- assign tx_i = tx_i_int[23:10];
- assign tx_q = tx_q_int[23:10];
-`endif // !`ifdef DSP
-
// /////////////////////////////////////////////////////////////////////////////////////
// Wishbone Intercon, single master
wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
@@ -320,7 +249,6 @@ module u1e_core
// Slave 0, Misc LEDs, Switches, controls
localparam REG_LEDS = 7'd0; // out
- localparam REG_SWITCHES = 7'd2; // in
localparam REG_CGEN_CTRL = 7'd4; // out
localparam REG_CGEN_ST = 7'd6; // in
localparam REG_TEST = 7'd8; // out
@@ -361,12 +289,11 @@ module u1e_core
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :
- (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
(s0_adr[6:0] == REG_TEST) ? reg_test :
(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
- (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+ (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 04:33:15 +0000