summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--usrp2/top/B100/u1plus_core.v2
-rw-r--r--usrp2/top/E1x0/u1e_core.v2
-rw-r--r--usrp2/top/N2x0/u2plus_core.v3
-rw-r--r--usrp2/top/USRP2/u2_core.v3
-rw-r--r--usrp2/vrt/vita_tx_chain.v43
5 files changed, 41 insertions, 12 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index c61d836d0..b9a7e55a2 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -213,7 +213,7 @@ module u1plus_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 5bf78bad2..d3495707d 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -218,7 +218,7 @@ module u1e_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index f3405e63a..0ee66d170 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -170,6 +170,7 @@ module u2plus_core
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
+ localparam DSP_TX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
@@ -659,7 +660,7 @@ module u2plus_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 6c1a418d5..746853fbf 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -175,6 +175,7 @@ module u2_core
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
// localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo
localparam DSP_RX_FIFOSIZE = 10;
+ localparam DSP_TX_FIFOSIZE = 10;
localparam ETH_TX_FIFOSIZE = 9;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
@@ -645,7 +646,7 @@ module u2_core
wire [31:0] sample_tx;
wire strobe_tx;
- vita_tx_chain #(.BASE(SR_TX_CTRL),
+ vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
.PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
.DSP_NUMBER(0))
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 07e143f19..7ea3978af 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -18,6 +18,7 @@
module vita_tx_chain
#(parameter BASE=0,
+ parameter FIFOSIZE=10,
parameter REPORT_ERROR=0,
parameter DO_FLOW_CONTROL=0,
parameter PROT_ENG_FLAGS=0,
@@ -46,31 +47,57 @@ module vita_tx_chain
wire [31:0] error_code;
wire clear_seqnum;
wire [31:0] current_seqnum;
-
+
+ wire clear;
+ assign clear_vita = clear;
assign underrun = error;
assign message = error_code;
setting_reg #(.my_addr(BASE+1)) sr
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(),.changed(clear_vita));
+ .in(set_data),.out(),.changed(clear));
setting_reg #(.my_addr(BASE+2), .at_reset(0)) sr_streamid
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(streamid),.changed(clear_seqnum));
+ wire [FIFOSIZE-1:0] access_adr, access_len;
+ wire access_we, access_stb, access_ok, access_done, access_skip_read;
+ wire [35:0] dsp_to_buf, buf_to_dsp;
+ wire [35:0] tx_data_int2;
+ wire tx_src_rdy_int2, tx_dst_rdy_int2;
+
+ double_buffer #(.BUF_SIZE(FIFOSIZE)) db
+ (.clk(clk),.reset(reset),.clear(clear),
+ .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+ .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+ .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
+
+ .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+ .data_o(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2));
+/*
+ dspengine_8to16 #(.BASE(BASE+X), .BUF_SIZE(FIFOSIZE)) dspengine_16to8
+ (.clk(clk),.reset(reset),.clear(clear),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+ .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+ .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
+*/
+ assign access_done = access_ok; //passthrough
+
vita_tx_deframer #(.BASE(BASE),
.MAXCHAN(MAXCHAN),
.USE_TRANS_HEADER(USE_TRANS_HEADER))
vita_tx_deframer
- (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum),
+ (.clk(clk), .reset(reset), .clear(clear), .clear_seqnum(clear_seqnum),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+ .data_i(tx_data_int2), .src_rdy_i(tx_src_rdy_int2), .dst_rdy_o(tx_dst_rdy_int2),
.sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
.current_seqnum(current_seqnum),
.debug(debug_vtd) );
vita_tx_control #(.BASE(BASE), .WIDTH(32*MAXCHAN)) vita_tx_control
- (.clk(clk), .reset(reset), .clear(clear_vita),
+ (.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code),
.sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
@@ -81,18 +108,18 @@ module vita_tx_chain
wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int;
gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt
- (.clk(clk), .reset(reset), .clear(clear_vita),
+ (.clk(clk), .reset(reset), .clear(clear),
.trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(),
.streamid(streamid), .vita_time(vita_time), .message(32'd0),
.seqnum(current_seqnum),
.data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy));
trigger_context_pkt #(.BASE(BASE)) trigger_context_pkt
- (.clk(clk), .reset(reset), .clear(clear_vita),
+ (.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.packet_consumed(packet_consumed), .trigger(trigger));
gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt
- (.clk(clk), .reset(reset), .clear(clear_vita),
+ (.clk(clk), .reset(reset), .clear(clear),
.trigger((error|ack) & (REPORT_ERROR==1)), .sent(),
.streamid(streamid), .vita_time(vita_time), .message(message),
.seqnum(current_seqnum),
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 06:29:29 +0000