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-rw-r--r--usrp2/fifo/fifo19_to_fifo36.v74
-rw-r--r--usrp2/simple_gemac/simple_gemac_wrapper.v65
-rw-r--r--usrp2/top/u2_rev3/u2_core.v25
3 files changed, 85 insertions, 79 deletions
diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v
index ae2edddc7..502821435 100644
--- a/usrp2/fifo/fifo19_to_fifo36.v
+++ b/usrp2/fifo/fifo19_to_fifo36.v
@@ -15,60 +15,73 @@ module fifo19_to_fifo36
input f36_dst_rdy_i,
output [31:0] debug
);
-
- reg f36_sof, f36_eof;
- reg [1:0] f36_occ;
+ // Shortfifo on input to guarantee no deadlock
+ wire [18:0] f19_data_int;
+ wire f19_src_rdy_int, f19_dst_rdy_int;
+
+ fifo_short #(.WIDTH(19)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o),
+ .dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int),
+ .space(),.occupied() );
+
+ // Actual f19 to f36 which could deadlock if not connected to shortfifos
+ reg f36_sof_int, f36_eof_int;
+ reg [1:0] f36_occ_int;
+ wire [35:0] f36_data_int;
+ wire f36_src_rdy_int, f36_dst_rdy_int;
+
reg [1:0] state;
reg [15:0] dat0, dat1;
- wire f19_sof = f19_datain[16];
- wire f19_eof = f19_datain[17];
- wire f19_occ = f19_datain[18];
+ wire f19_sof_int = f19_data_int[16];
+ wire f19_eof_int = f19_data_int[17];
+ wire f19_occ_int = f19_data_int[18];
- wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+ wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int;
always @(posedge clk)
- if(f19_src_rdy_i & ((state==0)|xfer_out))
- f36_sof <= f19_sof;
+ if(f19_src_rdy_int & ((state==0)|xfer_out))
+ f36_sof_int <= f19_sof_int;
always @(posedge clk)
- if(f19_src_rdy_i & ((state != 2)|xfer_out))
- f36_eof <= f19_eof;
+ if(f19_src_rdy_int & ((state != 2)|xfer_out))
+ f36_eof_int <= f19_eof_int;
always @(posedge clk)
if(reset)
begin
state <= 0;
- f36_occ <= 0;
+ f36_occ_int <= 0;
end
else
- if(f19_src_rdy_i)
+ if(f19_src_rdy_int)
case(state)
0 :
begin
- dat0 <= f19_datain;
- if(f19_eof)
+ dat0 <= f19_data_int;
+ if(f19_eof_int)
begin
state <= 2;
- f36_occ <= f19_occ ? 2'b01 : 2'b10;
+ f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
end
else
state <= 1;
end
1 :
begin
- dat1 <= f19_datain;
+ dat1 <= f19_data_int;
state <= 2;
- if(f19_eof)
- f36_occ <= f19_occ ? 2'b11 : 2'b00;
+ if(f19_eof_int)
+ f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00;
end
2 :
if(xfer_out)
begin
- dat0 <= f19_datain;
- if(f19_eof) // remain in state 2 if we are at eof
- f36_occ <= f19_occ ? 2'b01 : 2'b10;
+ dat0 <= f19_data_int;
+ if(f19_eof_int) // remain in state 2 if we are at eof
+ f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
else
state <= 1;
end
@@ -77,14 +90,21 @@ module fifo19_to_fifo36
if(xfer_out)
begin
state <= 0;
- f36_occ <= 0;
+ f36_occ_int <= 0;
end
- assign f19_dst_rdy_o = xfer_out | (state != 2);
- assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
- {f36_occ,f36_eof,f36_sof,dat0,dat1};
- assign f36_src_rdy_o = (state == 2);
+ assign f19_dst_rdy_int = xfer_out | (state != 2);
+ assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} :
+ {f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1};
+ assign f36_src_rdy_int = (state == 2);
assign debug = state;
+
+ // Shortfifo on output to guarantee no deadlock
+ fifo_short #(.WIDTH(36)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
+ .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
+ .space(),.occupied() );
endmodule // fifo19_to_fifo36
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v
index efcf89276..38c47ca37 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -30,7 +30,9 @@ module simple_gemac_wrapper
wire pause_req;
wire pause_request_en, pause_respect_en;
wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space;
-
+
+ wire [31:0] debug_state;
+
wire tx_reset, rx_reset;
reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
@@ -49,7 +51,8 @@ module simple_gemac_wrapper
.rx_clk(rx_clk), .rx_data(rx_data),
.rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
.tx_clk(tx_clk), .tx_data(tx_data),
- .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+ .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+ .debug(debug_state)
);
simple_gemac_wb simple_gemac_wb
@@ -65,14 +68,12 @@ module simple_gemac_wrapper
// RX FIFO Chain
wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+ wire [7:0] rx_ll_data;
- wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
- wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-
- wire [7:0] rx_ll_data, rx_ll_data2;
-
- wire [35:0] rx_f36_data_int1;
- wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+ wire [18:0] rx_f19_data_int1, rx_f19_data_int2;
+ wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
+ wire [35:0] rx_f36_data_int;
+ wire rx_f36_src_rdy_int, rx_f36_dst_rdy_int;
rxmac_to_ll8 rx_adapt
(.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -80,27 +81,25 @@ module simple_gemac_wrapper
.ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof
.ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
- ll8_shortfifo rx_sfifo
+ ll8_to_fifo19 ll8_to_fifo19
(.clk(rx_clk), .reset(rx_reset), .clear(0),
- .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
- .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
- .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
- .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+ .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
+ .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
+ .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
- assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n;
- assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
- assign rx_ll_sof2_n = ~rx_ll_sof2;
- assign rx_ll_eof2_n = ~rx_ll_eof2;
-
- ll8_to_fifo36 ll8_to_fifo36
+ fifo19_rxrealign fifo19_rxrealign
(.clk(rx_clk), .reset(rx_reset), .clear(0),
- .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
- .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
- .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+ .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
+ .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
+
+ fifo19_to_fifo36 rx_fifo19_to_fifo36
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .f19_datain(rx_f19_data_int2), .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2),
+ .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) );
fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
- (.wclk(rx_clk), .datain(rx_f36_data_int1),
- .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
+ (.wclk(rx_clk), .datain(rx_f36_data_int),
+ .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space),
.rclk(sys_clk), .dataout(rx_f36_data),
.src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
@@ -113,10 +112,9 @@ module simple_gemac_wrapper
wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
- (.wclk(sys_clk), .datain(tx_f36_data),
- .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
- .rclk(tx_clk), .dataout(tx_f36_data_int1),
- .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
+ (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
+ .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(),
+ .arst(reset));
fifo36_to_ll8 fifo36_to_ll8
(.clk(tx_clk), .reset(tx_reset), .clear(clear),
@@ -142,24 +140,25 @@ module simple_gemac_wrapper
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+ // Flow Control
flow_ctrl_rx flow_ctrl_rx
(.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
.rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
.tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
wire [31:0] debug_tx, debug_rx;
-
+
assign debug_tx = { { tx_ll_data },
{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy,
tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
{ tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
{ tx_data} };
assign debug_rx = { { rx_ll_data },
- { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy,
- rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
- { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+ { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
+ { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]},
{ rx_data} };
assign debug = debug_rx;
endmodule // simple_gemac_wrapper
+
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 5652673be..747b2c6cb 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -433,32 +433,24 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
- wire [18:0] rx_f19_data, tx_f19_data;
- wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-
- simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ wire [35:0] rx_f36_data, tx_f36_data;
+ wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
+
+ simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
(.clk125(clk_to_mac), .reset(wb_rst),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(dsp_clk),
- .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
- .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+ .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
.wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
.mdio(MDIO), .mdc(MDC),
.debug(debug_mac));
- wire [35:0] rx_f36_data, tx_f36_data;
- wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
//mac rx to eth input...
- fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f19_datain(rx_f19_data), .f19_src_rdy_i(rx_f19_src_rdy), .f19_dst_rdy_o(rx_f19_dst_rdy),
- .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
@@ -470,11 +462,6 @@ module u2_core
.datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
.dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
- fifo36_to_fifo19 eth_out_fifo36_to_fifo19
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
- .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
// /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 20:58:47 +0000