diff options
| -rw-r--r-- | usrp2/vrt/gen_context_pkt.v | 64 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 43 |
2 files changed, 107 insertions, 0 deletions
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v new file mode 100644 index 000000000..9e3fcbca8 --- /dev/null +++ b/usrp2/vrt/gen_context_pkt.v @@ -0,0 +1,64 @@ + + +module gen_context_pkt + #(parameter PROT_ENG_FLAGS =1) + (input clk, input reset, input clear, + input trigger, output sent, + input [31:0] streamid, + input [63:0] vita_time, + input [31:0] message, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + localparam CTXT_IDLE = 0; + localparam CTXT_PROT_ENG = 1; + localparam CTXT_HEADER = 2; + localparam CTXT_STREAMID = 3; + localparam CTXT_SECS = 4; + localparam CTXT_TICS = 5; + localparam CTXT_TICS2 = 6; + localparam CTXT_MESSAGE = 7; + localparam CTXT_DONE = 8; + + reg [33:0] data_int; + wire src_rdy_int, dst_rdy_int; + wire [3:0] seqno = 0; + reg [3:0] ctxt_state; + + always @(posedge clk) + if(reset | clear) + ctxt_state <= CTXT_IDLE; + else + case(ctxt_state) + CTXT_IDLE : + if(trigger) + ctxt_state <= CTXT_HEADER; + + CTXT_DONE : + if(~trigger) + ctxt_state <= CTXT_IDLE; + + default : + if(dst_rdy_int) + ctxt_state <= ctxt_state + 1; + endcase // case (ctxt_state) + + assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); + + always @* + case(ctxt_state) + CTXT_HEADER : data_int <= { 2'b01, 12'b010100001101, seqno, 16'd6 }; + CTXT_STREAMID : data_int <= { 2'b00, streamid }; + CTXT_SECS : data_int <= { 2'b00, vita_time[63:32] }; + CTXT_TICS : data_int <= { 2'b00, 32'd0 }; + CTXT_TICS2 : data_int <= { 2'b00, vita_time[31:0] }; + CTXT_MESSAGE : data_int <= { 2'b10, message }; + default : {2'b00, 32'b00}; + endcase // case (ctxt_state) + + fifo_short (.WIDTH(34)) ctxt_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + assign data_o[35:34] = 2'b00; + +endmodule // gen_context_pkt diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v new file mode 100644 index 000000000..17cfe1799 --- /dev/null +++ b/usrp2/vrt/vita_tx_chain.v @@ -0,0 +1,43 @@ + +module vita_tx_chain + #(parameter SR_TX_CTRL=0, + parameter SR_TX_DSP=0) + (input dsp_clk, input dsp_rst, + input set_stb_dsp, input [7:0] set_addr_dsp, input [31:0] set_data_dsp, + input [63:0] vita_time, + input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, + output [15:0] dac_a, output [15:0] dac_b, + output underrun, output run_tx, + output [31:0] debug); + + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign debug = debug_vtc | debug_vtd; + +endmodule // vita_tx_chain |