diff options
| -rw-r--r-- | usrp2/top/u1e_passthru/Makefile | 107 | ||||
| -rw-r--r-- | usrp2/top/u1e_passthru/passthru.ucf | 266 | ||||
| -rw-r--r-- | usrp2/top/u1e_passthru/passthru.v | 18 |
3 files changed, 391 insertions, 0 deletions
diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..62923f87f --- /dev/null +++ b/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,107 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := passthru +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +top/u1e_passthru/passthru.ucf \ +top/u1e_passthru/passthru.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..1672132a2 --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,266 @@ + +#NET "CLK_FPGA_P" LOC = "Y11" ; +#NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +#NET "EM_D<15>" LOC = "D13" ; +#NET "EM_D<14>" LOC = "D15" ; +#NET "EM_D<13>" LOC = "C16" ; +#NET "EM_D<12>" LOC = "B20" ; +#NET "EM_D<11>" LOC = "A19" ; +#NET "EM_D<10>" LOC = "A17" ; +#NET "EM_D<9>" LOC = "E15" ; +#NET "EM_D<8>" LOC = "F15" ; +#NET "EM_D<7>" LOC = "E16" ; +#NET "EM_D<6>" LOC = "F16" ; +#NET "EM_D<5>" LOC = "B17" ; +#NET "EM_D<4>" LOC = "C17" ; +#NET "EM_D<3>" LOC = "B19" ; +#NET "EM_D<2>" LOC = "D19" ; +#NET "EM_D<1>" LOC = "C19" ; +#NET "EM_D<0>" LOC = "A20" ; + +#NET "EM_A<10>" LOC = "C14" ; +#NET "EM_A<9>" LOC = "C10" ; +#NET "EM_A<8>" LOC = "C5" ; +#NET "EM_A<7>" LOC = "A18" ; +#NET "EM_A<6>" LOC = "A15" ; +#NET "EM_A<5>" LOC = "A12" ; +#NET "EM_A<4>" LOC = "A10" ; +#NET "EM_A<3>" LOC = "E7" ; +#NET "EM_A<2>" LOC = "A7" ; +#NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +##NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +##NET "EM_NCS1" LOC = "D18" ; +##NET "EM_NCS0" LOC = "D17" ; + +#NET "EM_CLK" LOC = "F11" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +##NET "EM_NADV_ALE" LOC = "B15" ; +##NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +#NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +#NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +#NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +#NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +#NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +#NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +#NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +#NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug +#NET "overo_gpio144" LOC = "A5" ; # tx_have_space +#NET "overo_gpio145" LOC = "C7" ; # tx_underrun +#NET "overo_gpio146" LOC = "A6" ; # rx_have_data +#NET "overo_gpio147" LOC = "B6" ; # rx_overrun +#NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +#NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +#NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +##NET "overo_txd1" LOC = "C6" ; +##NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + +##NET "SYSEN" LOC = "C11" ; + +## I2C +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; + +## SPI +### DBoard SPI +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +##NET "aux_sdi_codec" LOC = "F19" ; +##NET "aux_sdo_codec" LOC = "F18" ; +##NET "aux_sclk_codec" LOC = "D21" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +#NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; + +## Debug pins +#NET "debug_led<2>" LOC = "T5" ; +#NET "debug_led<1>" LOC = "R2" ; +#NET "debug_led<0>" LOC = "R1" ; +#NET "debug<0>" LOC = "P6" ; +#NET "debug<1>" LOC = "R6" ; +#NET "debug<2>" LOC = "P1" ; +#NET "debug<3>" LOC = "P2" ; +#NET "debug<4>" LOC = "N6" ; +#NET "debug<5>" LOC = "N5" ; +#NET "debug<6>" LOC = "N1" ; +#NET "debug<7>" LOC = "K2" ; +#NET "debug<8>" LOC = "K3" ; +#NET "debug<9>" LOC = "K6" ; +#NET "debug<10>" LOC = "L5" ; +#NET "debug<11>" LOC = "H2" ; +#NET "debug<12>" LOC = "K4" ; +#NET "debug<13>" LOC = "K5" ; +#NET "debug<14>" LOC = "G1" ; +#NET "debug<15>" LOC = "H1" ; +#NET "debug<16>" LOC = "H5" ; +#NET "debug<17>" LOC = "H6" ; +#NET "debug<18>" LOC = "E3" ; +#NET "debug<19>" LOC = "E4" ; +#NET "debug<20>" LOC = "G5" ; +#NET "debug<21>" LOC = "G6" ; +#NET "debug<22>" LOC = "F2" ; +#NET "debug<23>" LOC = "F1" ; +#NET "debug<24>" LOC = "H3" ; +#NET "debug<25>" LOC = "H4" ; +#NET "debug<26>" LOC = "F4" ; +#NET "debug<27>" LOC = "F5" ; +#NET "debug<28>" LOC = "C2" ; +#NET "debug<29>" LOC = "C1" ; +#NET "debug<30>" LOC = "F3" ; +#NET "debug<31>" LOC = "G3" ; +#NET "debug_clk<0>" LOC = "L6" ; +#NET "debug_clk<1>" LOC = "M5" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + +##NET "RXSYNC" LOC = "F22" ; +##NET "reset_codec" LOC = "D22" ; + +##NET "DB<11>" LOC = "E22" ; +##NET "DB<10>" LOC = "J19" ; +##NET "DB<9>" LOC = "H20" ; +##NET "DB<8>" LOC = "G19" ; +##NET "DB<7>" LOC = "F20" ; +##NET "DB<6>" LOC = "K16" ; +##NET "DB<5>" LOC = "J17" ; +##NET "DB<4>" LOC = "H22" ; +##NET "DB<3>" LOC = "G22" ; +##NET "DB<2>" LOC = "H17" ; +##NET "DB<1>" LOC = "H18" ; +##NET "DB<0>" LOC = "K20" ; +##NET "DA<11>" LOC = "J20" ; +##NET "DA<10>" LOC = "K19" ; +##NET "DA<9>" LOC = "K18" ; +##NET "DA<8>" LOC = "L22" ; +##NET "DA<7>" LOC = "K22" ; +##NET "DA<6>" LOC = "N22" ; +##NET "DA<5>" LOC = "M22" ; +##NET "DA<4>" LOC = "N20" ; +##NET "DA<3>" LOC = "N19" ; +##NET "DA<2>" LOC = "R22" ; +##NET "DA<1>" LOC = "P22" ; +##NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; + +#NET "PPS_IN" LOC = "M17" ; + +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; + +##NET "CLKOUT2_CODEC" LOC = "U12" ; +##NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "AB21" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; +##NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +##NET "unnamed_net37" LOC = "B1" ; # TMS +##NET "unnamed_net36" LOC = "B22" ; # TDO +##NET "unnamed_net35" LOC = "D2" ; # TDI +##NET "unnamed_net34" LOC = "A21" ; # TCK +##NET "unnamed_net45" LOC = "F7" ; # PUDC_B +##NET "unnamed_net44" LOC = "V6" ; # M2 +##NET "unnamed_net43" LOC = "AA3" ; # M1 +##NET "unnamed_net42" LOC = "AB3" ; # M0 +##NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..459c226ee --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio0, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio0; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru |