diff options
| -rwxr-xr-x | rbf/rev2/std_2rxhb_2tx.rbf | bin | 179750 -> 180404 bytes | |||
| -rwxr-xr-x | rbf/rev4/std_2rxhb_2tx.rbf | bin | 179750 -> 180404 bytes | |||
| -rw-r--r-- | sdr_lib/atr_delay.v | 83 | ||||
| -rw-r--r-- | sdr_lib/master_control.v | 10 | ||||
| -rw-r--r-- | toplevel/usrp_std/usrp_std.qsf | 5 |
5 files changed, 96 insertions, 2 deletions
diff --git a/rbf/rev2/std_2rxhb_2tx.rbf b/rbf/rev2/std_2rxhb_2tx.rbf Binary files differindex dbcd84e2d..2b97f9d4e 100755 --- a/rbf/rev2/std_2rxhb_2tx.rbf +++ b/rbf/rev2/std_2rxhb_2tx.rbf diff --git a/rbf/rev4/std_2rxhb_2tx.rbf b/rbf/rev4/std_2rxhb_2tx.rbf Binary files differindex dbcd84e2d..2b97f9d4e 100755 --- a/rbf/rev4/std_2rxhb_2tx.rbf +++ b/rbf/rev4/std_2rxhb_2tx.rbf diff --git a/sdr_lib/atr_delay.v b/sdr_lib/atr_delay.v new file mode 100644 index 000000000..a832421a1 --- /dev/null +++ b/sdr_lib/atr_delay.v @@ -0,0 +1,83 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o); + input clk_i; + input rst_i; + input ena_i; + input tx_empty_i; + input [31:0] tx_delay_i; + input [31:0] rx_delay_i; + output atr_tx_o; + + reg [3:0] state; + reg [31:0] count; + + `define ST_RX_DELAY 4'b0001 + `define ST_RX 4'b0010 + `define ST_TX_DELAY 4'b0100 + `define ST_TX 4'b1000 + + always @(posedge clk_i) + if (rst_i | ~ena_i) + begin + state <= `ST_RX; + count <= 0; + end + else + case (state) + `ST_RX: + if (!tx_empty_i) + begin + state <= `ST_TX_DELAY; + count <= tx_delay_i; + end + + `ST_TX_DELAY: + if (count == 0) + state <= `ST_TX; + else + count <= count - 1; + + `ST_TX: + if (tx_empty_i) + begin + state <= `ST_RX_DELAY; + count <= rx_delay_i; + end + + `ST_RX_DELAY: + if (count == 0) + state <= `ST_RX; + else + count <= count - 1; + + default: // Error + begin + state <= `ST_RX; + count <= 0; + end + endcase + + assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY); + +endmodule // atr_delay + diff --git a/sdr_lib/master_control.v b/sdr_lib/master_control.v index 863d44a82..6befc4dfd 100644 --- a/sdr_lib/master_control.v +++ b/sdr_lib/master_control.v @@ -3,6 +3,7 @@ // USRP - Universal Software Radio Peripheral // // Copyright (C) 2003,2005 Matt Ettus +// Copyright (C) 2007 Corgan Enterprises LLC // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -111,8 +112,9 @@ module master_control <= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); endcase // case(serial_addr) - wire transmit_now = !tx_empty & enable_tx; + wire transmit_now; wire atr_ctl; + wire [31:0] atr_tx_delay, atr_rx_delay; wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3; setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0)); @@ -132,8 +134,14 @@ module master_control setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3)); //setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl)); + setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay)); + setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay)); + assign atr_ctl = 1'b1; + atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl & enable_tx),.tx_empty_i(tx_empty), + .tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now)); + wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0; wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg); diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index ad98b1165..14dbd30c2 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -27,7 +27,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION 6.1 +set_global_assignment -name LAST_QUARTUS_VERSION 7.0 # Pin & Location Assignments # ========================== @@ -368,6 +368,9 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk # end ENTITY(usrp_std) # -------------------- +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v |