diff options
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 6 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_control.v | 61 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_deframer.v | 7 |
3 files changed, 50 insertions, 24 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 705be4a0e..bcdbea820 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -14,7 +14,7 @@ module vita_tx_chain output [31:0] debug); localparam MAXCHAN = 1; - localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); wire [FIFOWIDTH-1:0] tx1_data; wire tx1_src_rdy, tx1_dst_rdy; @@ -25,10 +25,10 @@ module vita_tx_chain wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; wire error; - wire [15:0] error_code; + wire [31:0] error_code; assign underrun = error; - assign message = {16'h0,error_code}; + assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 56a6c5a17..e02866af2 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -7,10 +7,10 @@ module vita_tx_control input [63:0] vita_time, output error, - output reg [15:0] error_code, + output reg [31:0] error_code, // From vita_tx_deframer - input [5+64+WIDTH-1:0] sample_fifo_i, + input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -22,14 +22,15 @@ module vita_tx_control output [31:0] debug ); - assign sample = sample_fifo_i[5+64+WIDTH-1:5+64]; + assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; wire [63:0] send_time = sample_fifo_i[63:0]; - wire eop = sample_fifo_i[64]; - wire eob = sample_fifo_i[65]; - wire sob = sample_fifo_i[66]; - wire send_at = sample_fifo_i[67]; - wire seqnum_err = sample_fifo_i[68]; + wire [15:0] seqnum = sample_fifo_i[79:64]; + wire eop = sample_fifo_i[80]; + wire eob = sample_fifo_i[81]; + wire sob = sample_fifo_i[82]; + wire send_at = sample_fifo_i[83]; + wire seqnum_err = sample_fifo_i[84]; wire now, early, late, too_early; @@ -46,11 +47,11 @@ module vita_tx_control localparam IBS_ERROR = 3; localparam IBS_ERROR_DONE = 4; - localparam CODE_UNDERRUN = 2; - localparam CODE_SEQ_ERROR = 4; - localparam CODE_TIME_ERROR = 8; - localparam CODE_UNDERRUN_MIDPKT = 16; - localparam CODE_SEQ_ERROR_MIDBURST = 32; + wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; + wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; + wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; + wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16}; + wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32}; reg [2:0] ibs_state; @@ -59,9 +60,22 @@ module vita_tx_control (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); + wire [31:0] error_policy; + setting_reg #(.my_addr(BASE+3)) sr_error_policy + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(error_policy),.changed()); + + wire policy_wait = error_policy[0]; + wire policy_next_packet = error_policy[1]; + wire policy_next_burst = error_policy[2]; + reg send_error; + always @(posedge clk) if(reset | clear_state) - ibs_state <= IBS_IDLE; + begin + ibs_state <= IBS_IDLE; + send_error <= 0; + end else case(ibs_state) IBS_IDLE : @@ -70,6 +84,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_SEQ_ERROR; + send_error <= 1; end else if(~send_at | now) ibs_state <= IBS_RUN; @@ -77,6 +92,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_TIME_ERROR; + send_error <= 1; end IBS_RUN : @@ -85,6 +101,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_UNDERRUN_MIDPKT; + send_error <= 1; end else if(eop) if(eob) @@ -97,20 +114,27 @@ module vita_tx_control begin ibs_state <= IBS_ERROR_DONE; error_code <= CODE_UNDERRUN; + send_error <= 1; end else if(sample_fifo_src_rdy_i) if(seqnum_err) begin ibs_state <= IBS_ERROR; error_code <= CODE_SEQ_ERROR_MIDBURST; + send_error <= 1; end else ibs_state <= IBS_RUN; IBS_ERROR : - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_ERROR_DONE; - + begin + send_error <= 0; + if(sample_fifo_src_rdy_i & eop) + if(policy_next_packet | (policy_next_burst & eob)) + ibs_state <= IBS_IDLE; + else + ibs_state <= IBS_ERROR_DONE; + end IBS_ERROR_DONE : ; @@ -118,7 +142,8 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - assign error = (ibs_state == IBS_ERROR_DONE); + //assign error = (ibs_state == IBS_ERROR_DONE); + assign error = send_error; assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index ce9f222e8..58878790d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -10,7 +10,7 @@ module vita_tx_deframer input src_rdy_i, output dst_rdy_o, - output [5+64+(32*MAXCHAN)-1:0] sample_fifo_o, + output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -21,7 +21,7 @@ module vita_tx_deframer output [31:0] debug ); - localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); wire [1:0] numchan; setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan @@ -185,7 +185,8 @@ module vita_tx_deframer .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); // sob, eob, has_secs (send_at) ignored on all lines except first - assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; + assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, + 12'd0,seqnum_reg,send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; |