diff options
31 files changed, 930 insertions, 1621 deletions
diff --git a/firmware/zpu/apps/txrx_uhd.c b/firmware/zpu/apps/txrx_uhd.c index 68c24e872..12f173f5c 100644 --- a/firmware/zpu/apps/txrx_uhd.c +++ b/firmware/zpu/apps/txrx_uhd.c @@ -1,8 +1,5 @@ -// -// Copyright 2010-2011 Ettus Research LLC -// /* - * Copyright 2007,2008 Free Software Foundation, Inc. + * Copyright 2010-2011 Ettus Research LLC * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,94 +15,58 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <lwip/ip.h> -#include <lwip/udp.h> +//peripheral headers #include "u2_init.h" -#include "memory_map.h" #include "spi.h" +#include "i2c.h" #include "hal_io.h" #include "pic.h" -#include <stdbool.h> -#include "ethernet.h" + +//printf headers #include "nonstdio.h" -#include <net/padded_eth_hdr.h> -#include <net_common.h> -#include "memcpy_wa.h" -#include <stddef.h> -#include <stdlib.h> -#include <string.h> -#include "clocks.h" + +//network headers +#include "arp_cache.h" +#include "ethernet.h" +#include "net_common.h" #include "usrp2/fw_common.h" -#include <i2c.h> -#include <ethertype.h> -#include <arp_cache.h> #include "udp_fw_update.h" #include "pkt_ctrl.h" -#include "banal.h" -static void setup_network(void); +//standard headers +#include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <stdbool.h> -// ---------------------------------------------------------------- -// the fast-path setup global variables -// ---------------------------------------------------------------- -static eth_mac_addr_t fp_mac_addr_src, fp_mac_addr_dst; -struct socket_address fp_socket_src, fp_socket_dst; extern uint16_t dsp0_dst_port, err0_dst_port, dsp1_dst_port; -static void handle_udp_err0_packet( +static void handle_udp_data_packet( struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len ){ - sr_udp_sm->err0_port = (((uint32_t)dst.port) << 16) | src.port; - err0_dst_port = src.port; - printf("Storing for async error path:\n"); - printf(" source udp port: %d\n", dst.port); - printf(" destination udp port: %d\n", src.port); - newline(); -} + size_t which; + switch(dst.port){ + case USRP2_UDP_DSP0_PORT: + which = 0; + dsp0_dst_port = src.port; + break; -static void handle_udp_dsp1_packet( - struct socket_address src, struct socket_address dst, - unsigned char *payload, int payload_len -){ - sr_udp_sm->dsp1_port = (((uint32_t)dst.port) << 16) | src.port; - dsp1_dst_port = src.port; - printf("Storing for dsp1 path:\n"); - printf(" source udp port: %d\n", dst.port); - printf(" destination udp port: %d\n", src.port); - newline(); -} + case USRP2_UDP_DSP1_PORT: + which = 2; + dsp1_dst_port = src.port; + break; -static void handle_udp_dsp0_packet( - struct socket_address src, struct socket_address dst, - unsigned char *payload, int payload_len -){ - fp_mac_addr_src = *ethernet_mac_addr(); - arp_cache_lookup_mac(&src.addr, &fp_mac_addr_dst); - fp_socket_src = dst; - fp_socket_dst = src; - sr_udp_sm->dsp0_port = (((uint32_t)dst.port) << 16) | src.port; - dsp0_dst_port = src.port; - printf("Storing for dsp0 path:\n"); - printf(" source mac addr: "); - print_mac_addr(&fp_mac_addr_src); newline(); - printf(" source ip addr: "); - print_ip_addr(&fp_socket_src.addr); newline(); - printf(" source udp port: %d\n", fp_socket_src.port); - printf(" destination mac addr: "); - print_mac_addr(&fp_mac_addr_dst); newline(); - printf(" destination ip addr: "); - print_ip_addr(&fp_socket_dst.addr); newline(); - printf(" destination udp port: %d\n", fp_socket_dst.port); - newline(); - - //setup network - setup_network(); + case USRP2_UDP_ERR0_PORT: + which = 1; + err0_dst_port = src.port; + break; + + default: return; + } + eth_mac_addr_t eth_mac_host; arp_cache_lookup_mac(&src.addr, ð_mac_host); + setup_framer(eth_mac_host, *ethernet_mac_addr(), src, dst, which); } #define OTW_GPIO_BANK_TO_NUM(bank) \ @@ -278,6 +239,7 @@ static void handle_udp_ctrl_packet( send_udp_pkt(USRP2_UDP_CTRL_PORT, src, &ctrl_data_out, sizeof(ctrl_data_out)); } +#include <net/padded_eth_hdr.h> static void handle_inp_packet(uint32_t *buff, size_t num_lines){ //test if its an ip recovery packet @@ -318,40 +280,6 @@ void link_changed_callback(int speed){ } } -static void setup_network(void){ - - //setup ethernet header machine - sr_udp_sm->eth_hdr.mac_dst_0_1 = (fp_mac_addr_dst.addr[0] << 8) | fp_mac_addr_dst.addr[1]; - sr_udp_sm->eth_hdr.mac_dst_2_3 = (fp_mac_addr_dst.addr[2] << 8) | fp_mac_addr_dst.addr[3]; - sr_udp_sm->eth_hdr.mac_dst_4_5 = (fp_mac_addr_dst.addr[4] << 8) | fp_mac_addr_dst.addr[5]; - sr_udp_sm->eth_hdr.mac_src_0_1 = (fp_mac_addr_src.addr[0] << 8) | fp_mac_addr_src.addr[1]; - sr_udp_sm->eth_hdr.mac_src_2_3 = (fp_mac_addr_src.addr[2] << 8) | fp_mac_addr_src.addr[3]; - sr_udp_sm->eth_hdr.mac_src_4_5 = (fp_mac_addr_src.addr[4] << 8) | fp_mac_addr_src.addr[5]; - sr_udp_sm->eth_hdr.ether_type = ETHERTYPE_IPV4; - - //setup ip header machine - unsigned int chksum = 0; - sr_udp_sm->ip_hdr.ver_ihl_tos = CHKSUM(0x4500, &chksum); // IPV4, 5 words of header (20 bytes), TOS=0 - sr_udp_sm->ip_hdr.total_length = UDP_SM_INS_IP_LEN; // Don't checksum this line in SW - sr_udp_sm->ip_hdr.identification = CHKSUM(0x0000, &chksum); // ID - sr_udp_sm->ip_hdr.flags_frag_off = CHKSUM(0x4000, &chksum); // don't fragment - sr_udp_sm->ip_hdr.ttl_proto = CHKSUM(0x2011, &chksum); // TTL=32, protocol = UDP (17 decimal) - //sr_udp_sm->ip_hdr.checksum .... filled in below - uint32_t src_ip_addr = fp_socket_src.addr.addr; - uint32_t dst_ip_addr = fp_socket_dst.addr.addr; - sr_udp_sm->ip_hdr.src_addr_high = CHKSUM(src_ip_addr >> 16, &chksum); // IP src high - sr_udp_sm->ip_hdr.src_addr_low = CHKSUM(src_ip_addr & 0xffff, &chksum); // IP src low - sr_udp_sm->ip_hdr.dst_addr_high = CHKSUM(dst_ip_addr >> 16, &chksum); // IP dst high - sr_udp_sm->ip_hdr.dst_addr_low = CHKSUM(dst_ip_addr & 0xffff, &chksum); // IP dst low - sr_udp_sm->ip_hdr.checksum = UDP_SM_INS_IP_HDR_CHKSUM | (chksum & 0xffff); - - //setup the udp header machine - sr_udp_sm->udp_hdr.src_port = UDP_SM_INS_UDP_SRC_PORT; - sr_udp_sm->udp_hdr.dst_port = UDP_SM_INS_UDP_DST_PORT; - sr_udp_sm->udp_hdr.length = UDP_SM_INS_UDP_LEN; - sr_udp_sm->udp_hdr.checksum = UDP_SM_LAST_WORD; // zero UDP checksum -} - int main(void) { @@ -370,9 +298,9 @@ main(void) //2) register callbacks for udp ports we service init_udp_listeners(); register_udp_listener(USRP2_UDP_CTRL_PORT, handle_udp_ctrl_packet); - register_udp_listener(USRP2_UDP_DSP0_PORT, handle_udp_dsp0_packet); - register_udp_listener(USRP2_UDP_ERR0_PORT, handle_udp_err0_packet); - register_udp_listener(USRP2_UDP_DSP1_PORT, handle_udp_dsp1_packet); + register_udp_listener(USRP2_UDP_DSP0_PORT, handle_udp_data_packet); + register_udp_listener(USRP2_UDP_ERR0_PORT, handle_udp_data_packet); + register_udp_listener(USRP2_UDP_DSP1_PORT, handle_udp_data_packet); #ifdef USRP2P register_udp_listener(USRP2_UDP_UPDATE_PORT, handle_udp_fw_update_packet); #endif diff --git a/firmware/zpu/lib/eth_mac_regs.h b/firmware/zpu/lib/eth_mac_regs.h deleted file mode 100644 index d680f8de0..000000000 --- a/firmware/zpu/lib/eth_mac_regs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* -*- c -*- */ -/* - * Copyright 2007 Free Software Foundation, Inc. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef INCLUDED_ETH_MAC_REGS_H -#define INCLUDED_ETH_MAC_REGS_H - -/* - * Simple GEMAC - * - */ -typedef struct { - volatile int settings; - volatile int ucast_hi; - volatile int ucast_lo; - volatile int mcast_hi; - volatile int mcast_lo; - volatile int miimoder; - volatile int miiaddress; - volatile int miitx_data; - volatile int miicommand; - volatile int miistatus; - volatile int miirx_data; - volatile int pause_time; - volatile int pause_thresh; -} eth_mac_regs_t; - -// settings register -#define MAC_SET_PAUSE_EN (1 << 0) // Makes us respect received pause frames (normally on) -#define MAC_SET_PASS_ALL (1 << 1) // Enables promiscuous mode, currently broken -#define MAC_SET_PASS_PAUSE (1 << 2) // Sends pause frames through (normally off) -#define MAC_SET_PASS_BCAST (1 << 3) // Sends broadcast frames through (normally on) -#define MAC_SET_PASS_MCAST (1 << 4) // Sends multicast frames that match mcast addr (normally off) -#define MAC_SET_PASS_UCAST (1 << 5) // Sends unicast (normal) frames through if they hit in address filter (normally on) -#define MAC_SET_PAUSE_SEND_EN (1 << 6) // Enables sending pause frames - -// miicommand register -#define MIIC_SCANSSTAT (1 << 0) // Scan status -#define MIIC_RSTAT (1 << 1) // Read status -#define MIIC_WCTRLDATA (1 << 2) // Write control data - -// miistatus register -#define MIIS_LINKFAIL (1 << 0) // The link failed -#define MIIS_BUSY (1 << 1) // The MII is busy (operation in progress) -#define MIIS_NVALID (1 << 2) // The data in the status register is invalid - // This it is only valid when the scan status is active. - -#endif /* INCLUDED_ETH_MAC_REGS_H */ diff --git a/firmware/zpu/usrp2p/memory_map.h b/firmware/zpu/lib/memory_map.h index 2567a4588..938cf7776 100644 --- a/firmware/zpu/usrp2p/memory_map.h +++ b/firmware/zpu/lib/memory_map.h @@ -21,34 +21,33 @@ #include <stdint.h> - -#define MASTER_CLK_RATE 100000000 // 100 MHz - - -//////////////////////////////////////////////////////////////// -// -// Memory map for embedded wishbone bus -// -//////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////// -// Boot RAM, Slave 0 - -#define BOOTRAM_BASE 0x0000 - - -//////////////////////////////////////////////////////////////// -// Packet Router RAM, Slave 1 -// -// The buffers themselves are located in Slave 1, Packet Router RAM. -// The status registers are in Slave 5, Packet Router Status. -// The control register is in Slave 7, Settings Bus. - -#define ROUTER_RAM_BASE 0x4000 +#define MASTER_CLK_RATE 100000000 // 100 MHz + +//////////////////////////////////////////////////////////////////////// +// Define slave bases +//////////////////////////////////////////////////////////////////////// +#define ROUTER_RAM_BASE 0x4000 +#define SPI_BASE 0x5000 +#define I2C_BASE 0x5400 +#define GPIO_BASE 0x5800 +#define READBACK_BASE 0x5C00 +#define ETH_BASE 0x6000 +#define SETTING_REGS_BASE 0x7000 +#define PIC_BASE 0x8000 +#define UART_BASE 0x8800 +#define ATR_BASE 0x8C00 +#ifdef USRP2 +#define SDSPI_BASE 0xB000 +#endif +#ifdef USRP2P +#define ICAP_BASE 0xA000 +#define SPIF_BASE 0xB000 +#define RAM_BASE 0xC000 +#endif ///////////////////////////////////////////////////// // SPI Core, Slave 2. See core docs for more info -#define SPI_BASE 0x6000 // Base address (16-bit) is base peripheral addr +///////////////////////////////////////////////////// typedef struct { volatile uint32_t txrx0; @@ -62,7 +61,6 @@ typedef struct { #define spi_regs ((spi_regs_t *) SPI_BASE) - // Masks for controlling different peripherals #define SPI_SS_AD9510 1 #define SPI_SS_AD9777 2 @@ -85,9 +83,7 @@ typedef struct { //////////////////////////////////////////////// // I2C, Slave 3 -// See Wishbone I2C-Master Core Specification. - -#define I2C_BASE 0x6100 +//////////////////////////////////////////////// typedef struct { volatile uint32_t prescaler_lo; // r/w @@ -123,37 +119,9 @@ typedef struct { #define I2C_ST_TIP (1 << 1) // Transfer-in-progress #define I2C_ST_IP (1 << 0) // Interrupt pending - -//////////////////////////////////////////////// -// GPIO, Slave 4 -// -// These go to the daughterboard i/o pins - -#define GPIO_BASE 0x6200 - -typedef struct { - volatile uint32_t io; // tx data in high 16, rx in low 16 - volatile uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 - volatile uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB - volatile uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB -} gpio_regs_t; - -// each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric - -#define gpio_base ((gpio_regs_t *) GPIO_BASE) - /////////////////////////////////////////////////// // Packet Router Status, Slave 5 -// -// The buffers themselves are located in Slave 1, Packet Router RAM. -// The status registers are in Slave 5, Packet Router Status. -// The control register is in Slave 7, Settings Bus. - -#define ROUTER_STATUS_BASE 0x6300 +/////////////////////////////////////////////////// typedef struct { volatile uint32_t _padding[8]; @@ -165,9 +133,7 @@ typedef struct { volatile uint32_t irqs; } router_status_t; -#define router_status ((router_status_t *) ROUTER_STATUS_BASE) - -#define BUTTON_PUSHED ((router_status->irqs & PIC_BUTTON) ? 0 : 1) +#define router_status ((router_status_t *) READBACK_BASE) // The hw_config register @@ -195,10 +161,43 @@ hwconfig_wishbone_divisor(void) /////////////////////////////////////////////////// // Ethernet Core, Slave 6 +/////////////////////////////////////////////////// -#define ETH_BASE 0x6400 - -#include "eth_mac_regs.h" +typedef struct { + volatile int settings; + volatile int ucast_hi; + volatile int ucast_lo; + volatile int mcast_hi; + volatile int mcast_lo; + volatile int miimoder; + volatile int miiaddress; + volatile int miitx_data; + volatile int miicommand; + volatile int miistatus; + volatile int miirx_data; + volatile int pause_time; + volatile int pause_thresh; +} eth_mac_regs_t; + +// settings register +#define MAC_SET_PAUSE_EN (1 << 0) // Makes us respect received pause frames (normally on) +#define MAC_SET_PASS_ALL (1 << 1) // Enables promiscuous mode, currently broken +#define MAC_SET_PASS_PAUSE (1 << 2) // Sends pause frames through (normally off) +#define MAC_SET_PASS_BCAST (1 << 3) // Sends broadcast frames through (normally on) +#define MAC_SET_PASS_MCAST (1 << 4) // Sends multicast frames that match mcast addr (normally off) +#define MAC_SET_PASS_UCAST (1 << 5) // Sends unicast (normal) frames through if they hit in address filter (normally on) +#define MAC_SET_PAUSE_SEND_EN (1 << 6) // Enables sending pause frames + +// miicommand register +#define MIIC_SCANSSTAT (1 << 0) // Scan status +#define MIIC_RSTAT (1 << 1) // Read status +#define MIIC_WCTRLDATA (1 << 2) // Write control data + +// miistatus register +#define MIIS_LINKFAIL (1 << 0) // The link failed +#define MIIS_BUSY (1 << 1) // The MII is busy (operation in progress) +#define MIIS_NVALID (1 << 2) // The data in the status register is invalid + // This it is only valid when the scan status is active. #define eth_mac ((eth_mac_regs_t *) ETH_BASE) @@ -207,26 +206,26 @@ hwconfig_wishbone_divisor(void) // // Output-only from processor point-of-view. // 1KB of address space (== 256 32-bit write-only regs) +//////////////////////////////////////////////////// + +#define SR_MISC 0 // 7 regs +#define SR_SIMTIMER 8 // 2 +#define SR_TIME64 10 // 6 +#define SR_BUF_POOL 16 // 4 +#define SR_RX_FRONT 24 // 5 +#define SR_RX_CTRL0 32 // 9 +#define SR_RX_DSP0 48 // 7 +#define SR_RX_CTRL1 80 // 9 +#define SR_RX_DSP1 96 // 7 -#define MISC_OUTPUT_BASE 0x5000 +#define SR_TX_FRONT 128 // ? +#define SR_TX_CTRL 144 // 6 +#define SR_TX_DSP 160 // 5 -#define SR_MISC 0 -#define SR_TX_PROT_ENG 32 -#define SR_RX_PROT_ENG 48 -#define SR_ROUTER_CTRL 64 -#define SR_UDP_SM 96 -#define SR_TX_DSP 208 -#define SR_TX_CTRL 224 -#define SR_RX_DSP0 160 -#define SR_RX_DSP1 240 -#define SR_RX_CTRL0 176 -#define SR_RX_CTRL1 32 -#define SR_TIME64 192 -#define SR_SIMTIMER 198 -#define SR_LAST 255 +#define SR_UDP_SM 192 // 64 -#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +#define _SR_ADDR(sr) (SETTING_REGS_BASE + (sr) * sizeof(uint32_t)) #define SR_ADDR_BLDRDONE _SR_ADDR(5) @@ -239,20 +238,19 @@ typedef struct { volatile uint32_t iface_ctrl; } router_ctrl_t; -#define router_ctrl ((router_ctrl_t *) _SR_ADDR(SR_ROUTER_CTRL)) +#define router_ctrl ((router_ctrl_t *) _SR_ADDR(SR_BUF_POOL)) // --- misc outputs --- typedef struct { - volatile uint32_t clk_ctrl; - volatile uint32_t serdes_ctrl; - volatile uint32_t adc_ctrl; - volatile uint32_t leds; - volatile uint32_t phy_ctrl; // LSB is reset line to eth phy - volatile uint32_t debug_mux_ctrl; - volatile uint32_t ram_page; // FIXME should go somewhere else... - volatile uint32_t flush_icache; // Flush the icache - volatile uint32_t led_src; // HW or SW control for LEDs + volatile uint32_t clk_ctrl; + volatile uint32_t serdes_ctrl; + volatile uint32_t adc_ctrl; + volatile uint32_t leds; + volatile uint32_t phy_ctrl; // LSB is reset line to eth phy + volatile uint32_t debug_mux_ctrl; + volatile uint32_t led_src; // HW or SW control for LEDs + volatile uint32_t flush_icache; // Flush the icache } output_regs_t; #define CLK_RESET (1<<4) @@ -277,73 +275,17 @@ typedef struct { // LED_F // controlled by CPLD #define LED_RJ45 (1 << 5) -#define output_regs ((output_regs_t *) MISC_OUTPUT_BASE) +#define output_regs ((output_regs_t *) SETTING_REGS_BASE) -// --- udp tx regs --- +// --- protocol framer regs --- -typedef struct { - // Bits 19:16 are control info; bits 15:0 are data (see below) - // First two words are unused. - volatile uint32_t _nope[2]; - //--- ethernet header - 14 bytes--- - volatile struct{ - uint32_t mac_dst_0_1; //word 2 - uint32_t mac_dst_2_3; - uint32_t mac_dst_4_5; - uint32_t mac_src_0_1; - uint32_t mac_src_2_3; - uint32_t mac_src_4_5; - uint32_t ether_type; //word 8 - } eth_hdr; - //--- ip header - 20 bytes --- - volatile struct{ - uint32_t ver_ihl_tos; //word 9 - uint32_t total_length; - uint32_t identification; - uint32_t flags_frag_off; - uint32_t ttl_proto; - uint32_t checksum; - uint32_t src_addr_high; - uint32_t src_addr_low; - uint32_t dst_addr_high; - uint32_t dst_addr_low; //word 18 - } ip_hdr; - //--- udp header - 8 bytes --- - volatile struct{ - uint32_t src_port; //word 19 - uint32_t dst_port; - uint32_t length; - uint32_t checksum; //word 22 - } udp_hdr; - volatile uint32_t _pad[1]; - volatile uint32_t dsp0_port; - volatile uint32_t err0_port; - volatile uint32_t dsp1_port; - volatile uint32_t err1_port; -} sr_udp_sm_t; - -// control bits (all expect UDP_SM_LAST_WORD are mutually exclusive) - -// Insert a UDP source port from the table -#define UDP_SM_INS_UDP_SRC_PORT (1 << 21) - -// Insert a UDP dest port from the table -#define UDP_SM_INS_UDP_DST_PORT (1 << 20) - -// This is the last word of the header -#define UDP_SM_LAST_WORD (1 << 19) - -// Insert IP header checksum here. Data is the xor of 16'hFFFF and -// the values written into regs 9-13 and 15-18. -#define UDP_SM_INS_IP_HDR_CHKSUM (1 << 18) - -// Insert IP Length here (data ignored) -#define UDP_SM_INS_IP_LEN (1 << 17) - -// Insert UDP Length here (data ignore) -#define UDP_SM_INS_UDP_LEN (1 << 16) - -#define sr_udp_sm ((sr_udp_sm_t *) _SR_ADDR(SR_UDP_SM)) +typedef struct{ + struct{ + volatile uint32_t entry[16]; + } table[4]; +} sr_proto_framer_t; + +#define sr_proto_framer_regs ((sr_proto_framer_t *) _SR_ADDR(SR_UDP_SM)) // --- VITA TX CTRL regs --- @@ -397,66 +339,9 @@ typedef struct { #define sr_time64 ((sr_time64_t *) _SR_ADDR(SR_TIME64)) - -/* - * --- ethernet tx protocol engine regs (write only) --- - * - * These registers control the transmit portion of the ethernet - * protocol engine (out of USRP2). The protocol engine handles fifo - * status and sequence number insertion in outgoing packets, and - * automagically generates status packets when required to inform the - * host of changes in fifo availability. - * - * All outgoing packets have their fifo_status field set to the number - * of 32-bit lines of fifo available in the ethernet Rx fifo (see - * usrp2_eth_packet.h). Seqno's are set if FIXME, else 0. - * - * FIXME clean this up once we know how it's supposed to behave. - */ - -typedef struct { - volatile uint32_t flags; // not yet fully defined (channel?) - volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr - volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr - volatile uint32_t mac_src2345; // 4 bytes of destination mac addr - volatile uint32_t seqno; // Write to init seqno. It autoincs on match -} tx_proto_engine_regs_t; - -#define tx_proto_engine ((tx_proto_engine_regs_t *) _SR_ADDR(SR_TX_PROT_ENG)) - -/* - * --- ethernet rx protocol engine regs (write only) --- - * - * These registers control the receive portion of the ethernet - * protocol engine (into USRP2). The protocol engine offloads common - * packet inspection operations so that firmware has less to do on - * "fast path" packets. - * - * The registers define conditions which must be matched for a packet - * to be considered a "fast path" packet. If a received packet - * matches the src and dst mac address, ethertype, flags field, and - * expected seqno number it is considered a "fast path" packet, and - * the expected seqno is updated. If the packet fails to satisfy any - * of the above conditions it's a "slow path" packet, and the - * corresponding SLOWPATH flag will be set buffer_status register. - */ - -typedef struct { - volatile uint32_t flags; // not yet fully defined (channel?) - volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr - volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr - volatile uint32_t mac_src2345; // 4 bytes of destination mac addr - volatile uint32_t ethertype_pad; // ethertype in high 16-bits -} rx_proto_engine_regs_t; - -#define rx_proto_engine ((rx_proto_engine_regs_t *) _SR_ADDR(SR_RX_PROT_ENG)) - - - -/////////////////////////////////////////////////// +/////////////////////////////////////////////////////// // Simple Programmable Interrupt Controller, Slave 8 - -#define PIC_BASE 0x6500 +/////////////////////////////////////////////////////// // Interrupt request lines // Bit numbers (LSB == 0) that correpond to interrupts into PIC @@ -511,12 +396,8 @@ typedef struct { #define sr_simple_timer ((sr_simple_timer_t *) _SR_ADDR(SR_SIMTIMER)) /////////////////////////////////////////////////// -// UNUSED, Slave 9 - -/////////////////////////////////////////////////// // UART, Slave 10 - -#define UART_BASE 0x6700 +/////////////////////////////////////////////////// typedef struct { // All elements are 8 bits except for clkdiv (16), but we use uint32 to make @@ -526,34 +407,32 @@ typedef struct { volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads volatile uint32_t txchar; // Write characters to be sent here volatile uint32_t rxchar; // Read received characters here - volatile uint32_t x[3]; //padding to reach 32B } uart_regs_t; #define uart_regs ((uart_regs_t *) UART_BASE) /////////////////////////////////////////////////// -// ATR Controller, Slave 11 - -#define ATR_BASE 0x6800 +// SD Card SPI interface, Slave 13 +// All regs are 8 bits wide, but are accessed as if they are 32 bits +/////////////////////////////////////////////////// +#ifdef USRP2 typedef struct { - volatile uint32_t v[16]; -} atr_regs_t; - -#define ATR_IDLE 0x0 // indicies into v -#define ATR_TX 0x1 -#define ATR_RX 0x2 -#define ATR_FULL 0x3 + volatile uint32_t status; // Write a 1 or 0 for controlling CS + volatile uint32_t clkdiv; + volatile uint32_t send_dat; + volatile uint32_t receive_dat; +} sdspi_regs_t; -#define atr_regs ((atr_regs_t *) ATR_BASE) +#define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE) -/////////////////////////////////////////////////// -// UNUSED, Slave 12 +#endif //USRP2 /////////////////////////////////////////////////// // ICAP, Slave 13 +/////////////////////////////////////////////////// +#ifdef USRP2P -#define ICAP_BASE 0x6A00 typedef struct { uint32_t icap; //only the lower 8 bits matter } icap_regs_t; @@ -564,8 +443,8 @@ typedef struct { // SPI Flash interface, Slave 14 // Control register definitions are the same as SPI, so use SPI_CTRL_ASS, etc. // Peripheral mask not needed since bus is dedicated (CE held low) +/////////////////////////////////////////////////// -#define SPIF_BASE 0x6B00 typedef struct { volatile uint32_t txrx0; volatile uint32_t txrx1; @@ -578,13 +457,6 @@ typedef struct { #define spif_regs ((spif_regs_t *) SPIF_BASE) -//////////////////////////////////////////////////////////////// -// Main RAM, Slave 15 - -#define RAM_BASE 0x8000 - - - -/////////////////////////////////////////////////// -#endif +#endif //USRP2P +#endif /* INCLUDED_MEMORY_MAP_H */ diff --git a/firmware/zpu/lib/net_common.c b/firmware/zpu/lib/net_common.c index f70f279ac..2e3257b35 100644 --- a/firmware/zpu/lib/net_common.c +++ b/firmware/zpu/lib/net_common.c @@ -36,17 +36,35 @@ #include <string.h> #include "pkt_ctrl.h" +/*********************************************************************** + * Constants + Globals + **********************************************************************/ static const bool debug = false; - static const size_t out_buff_size = 2048; - static const eth_mac_addr_t BCAST_MAC_ADDR = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; +#define MAX_UDP_LISTENERS 6 //used in the top level application... uint16_t dsp0_dst_port, err0_dst_port, dsp1_dst_port; -// ------------------------------------------------------------------------ +/*********************************************************************** + * 16-bit one's complement sum + **********************************************************************/ +static uint32_t chksum_buffer( + uint16_t *buf, size_t nshorts, + uint32_t initial_chksum +){ + uint32_t chksum = initial_chksum; + for (size_t i = 0; i < nshorts; i++) chksum += buf[i]; + + while (chksum >> 16) chksum = (chksum & 0xffff) + (chksum >> 16); + + return chksum; +} +/*********************************************************************** + * Listener registry + **********************************************************************/ static eth_mac_addr_t _local_mac_addr; static struct ip_addr _local_ip_addr; void register_addrs(const eth_mac_addr_t *mac_addr, const struct ip_addr *ip_addr){ @@ -54,10 +72,6 @@ void register_addrs(const eth_mac_addr_t *mac_addr, const struct ip_addr *ip_add _local_ip_addr = *ip_addr; } -//------------------------------------------------------------------------- - -#define MAX_UDP_LISTENERS 6 - struct listener_entry { unsigned short port; udp_receiver_t rcvr; @@ -104,9 +118,55 @@ register_udp_listener(int port, udp_receiver_t rcvr) } } -// ------------------------------------------------------------------------ - +/*********************************************************************** + * Protocol framer + **********************************************************************/ +void setup_framer( + eth_mac_addr_t eth_dst, + eth_mac_addr_t eth_src, + struct socket_address sock_dst, + struct socket_address sock_src, + size_t which +){ + struct { + padded_eth_hdr_t eth; + struct ip_hdr ip; + struct udp_hdr udp; + } frame; + + //-- load Ethernet header --// + frame.eth.dst = eth_dst; + frame.eth.src = eth_src; + frame.eth.ethertype = ETHERTYPE_IPV4; + + //-- load IPv4 header --// + IPH_VHLTOS_SET(&frame.ip, 4, 5, 0); + IPH_LEN_SET(&frame.ip, 0); + IPH_ID_SET(&frame.ip, 0); + IPH_OFFSET_SET(&frame.ip, IP_DF); // don't fragment + IPH_TTL_SET(&frame.ip, 32); + IPH_PROTO_SET(&frame.ip, IP_PROTO_UDP); + IPH_CHKSUM_SET(&frame.ip, 0); + frame.ip.src = sock_src.addr; + frame.ip.dest = sock_dst.addr; + IPH_CHKSUM_SET(&frame.ip, chksum_buffer( + (unsigned short *) &frame.ip, + sizeof(frame.ip)/sizeof(short), 0 + )); + + //-- load UDP header --// + frame.udp.src = sock_src.port; + frame.udp.dest = sock_dst.port; + frame.udp.len = 0; + frame.udp.chksum = 0; + + //copy into the framer table registers + memcpy_wa((void *)(sr_proto_framer_regs->table[which].entry + 1), &frame, sizeof(frame)); +} +/*********************************************************************** + * Slow-path packet framing and transmission + **********************************************************************/ /*! * low level routine to assembly an ethernet frame and send it. * @@ -164,43 +224,25 @@ send_pkt( if (debug) printf("sent %d bytes\n", (int)total_len); } -unsigned int CHKSUM(unsigned int x, unsigned int *chksum) -{ - *chksum += x; - *chksum = (*chksum & 0xffff) + (*chksum>>16); - *chksum = (*chksum & 0xffff) + (*chksum>>16); - return x; -} - -static unsigned int -chksum_buffer(unsigned short *buf, int nshorts, unsigned int initial_chksum) -{ - unsigned int chksum = initial_chksum; - for (int i = 0; i < nshorts; i++) - CHKSUM(buf[i], &chksum); - - return chksum; -} - void send_ip_pkt(struct ip_addr dst, int protocol, const void *buf0, size_t len0, const void *buf1, size_t len1) { - int ttl = 32; - struct ip_hdr ip; IPH_VHLTOS_SET(&ip, 4, 5, 0); IPH_LEN_SET(&ip, IP_HLEN + len0 + len1); IPH_ID_SET(&ip, 0); IPH_OFFSET_SET(&ip, IP_DF); /* don't fragment */ - ip._ttl_proto = (ttl << 8) | (protocol & 0xff); - ip._chksum = 0; + IPH_TTL_SET(&ip, 32); + IPH_PROTO_SET(&ip, protocol); + IPH_CHKSUM_SET(&ip, 0); ip.src = _local_ip_addr; ip.dest = dst; - ip._chksum = ~chksum_buffer((unsigned short *) &ip, - sizeof(ip)/sizeof(short), 0); + IPH_CHKSUM_SET(&ip, ~chksum_buffer( + (unsigned short *) &ip, sizeof(ip)/sizeof(short), 0 + )); eth_mac_addr_t dst_mac; bool found = arp_cache_lookup_mac(&ip.dest, &dst_mac); diff --git a/firmware/zpu/lib/net_common.h b/firmware/zpu/lib/net_common.h index 409022352..3cbc5c514 100644 --- a/firmware/zpu/lib/net_common.h +++ b/firmware/zpu/lib/net_common.h @@ -1,6 +1,5 @@ -/* -*- c++ -*- */ /* - * Copyright 2009,2010 Ettus Research LLC + * Copyright 2009-2011 Ettus Research LLC * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,12 +22,22 @@ #include <net/socket_address.h> #include <net/eth_mac_addr.h> -/* - * 1's complement sum for IP and UDP headers +/*! + * Setup an entry in the protocol framer for a UDP socket. * - * init chksum to zero to start. + * \param eth_dst ethernet destination mac addr + * \param eth_src ethernet source mac addr + * \param sock_dst udp/ip socket destination + * \param sock_src udp/ip socket source + * \param which the index into the table */ -unsigned int CHKSUM(unsigned int x, unsigned int *chksum); +void setup_framer( + eth_mac_addr_t eth_dst, + eth_mac_addr_t eth_src, + struct socket_address sock_dst, + struct socket_address sock_src, + size_t which +); typedef void (*udp_receiver_t)(struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len); diff --git a/firmware/zpu/usrp2/CMakeLists.txt b/firmware/zpu/usrp2/CMakeLists.txt index e54499084..75acae750 100644 --- a/firmware/zpu/usrp2/CMakeLists.txt +++ b/firmware/zpu/usrp2/CMakeLists.txt @@ -19,6 +19,8 @@ INCLUDE(${CMAKE_SOURCE_DIR}/lib/CMakeLists.txt) INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}) +ADD_DEFINITIONS(-DUSRP2) + ADD_LIBRARY(libusrp2fw STATIC ${COMMON_SRCS} sd.c diff --git a/firmware/zpu/usrp2/ethernet.c b/firmware/zpu/usrp2/ethernet.c index 5d4654bda..9a41eb280 100644 --- a/firmware/zpu/usrp2/ethernet.c +++ b/firmware/zpu/usrp2/ethernet.c @@ -1,4 +1,5 @@ /* + * Copyright 2011 Ettus Research LLC * Copyright 2007 Free Software Foundation, Inc. * * This program is free software: you can redistribute it and/or modify @@ -18,7 +19,6 @@ #include "ethernet.h" #include "eth_phy.h" #include "eth_mac.h" -#include "eth_mac_regs.h" #include "pic.h" #include "hal_io.h" #include "nonstdio.h" diff --git a/firmware/zpu/usrp2/memory_map.h b/firmware/zpu/usrp2/memory_map.h deleted file mode 100644 index 79b11759a..000000000 --- a/firmware/zpu/usrp2/memory_map.h +++ /dev/null @@ -1,578 +0,0 @@ -// Copyright 2010-2011 Ettus Research LLC -/* - * Copyright 2007,2008,2009 Free Software Foundation, Inc. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -/* Overall Memory Map - * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP) - * 8000-BFFF 16K Packet Router - * C000-FFFF 16K Peripherals - */ - - -#ifndef INCLUDED_MEMORY_MAP_H -#define INCLUDED_MEMORY_MAP_H - -#include <stdint.h> - - -#define MASTER_CLK_RATE 100000000 // 100 MHz - - -//////////////////////////////////////////////////////////////// -// -// Memory map for embedded wishbone bus -// -//////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////// -// Main RAM, Slave 0 - -#define RAM_BASE 0x0000 - -//////////////////////////////////////////////////////////////// -// Packet Router RAM, Slave 1 -// -// The buffers themselves are located in Slave 1, Packet Router RAM. -// The status registers are in Slave 5, Packet Router Status. -// The control register is in Slave 7, Settings Bus. - -#define ROUTER_RAM_BASE 0x8000 - -///////////////////////////////////////////////////// -// SPI Core, Slave 2. See core docs for more info -#define SPI_BASE 0xC000 // Base address (16-bit) - -typedef struct { - volatile uint32_t txrx0; - volatile uint32_t txrx1; - volatile uint32_t txrx2; - volatile uint32_t txrx3; - volatile uint32_t ctrl; - volatile uint32_t div; - volatile uint32_t ss; -} spi_regs_t; - -#define spi_regs ((spi_regs_t *) SPI_BASE) - - -// Masks for controlling different peripherals -#define SPI_SS_AD9510 1 -#define SPI_SS_AD9777 2 -#define SPI_SS_RX_DAC 4 -#define SPI_SS_RX_ADC 8 -#define SPI_SS_RX_DB 16 -#define SPI_SS_TX_DAC 32 -#define SPI_SS_TX_ADC 64 -#define SPI_SS_TX_DB 128 -#define SPI_SS_ADS64P44 256 - -// Masks for different parts of CTRL reg -#define SPI_CTRL_ASS (1<<13) -#define SPI_CTRL_IE (1<<12) -#define SPI_CTRL_LSB (1<<11) -#define SPI_CTRL_TXNEG (1<<10) -#define SPI_CTRL_RXNEG (1<< 9) -#define SPI_CTRL_GO_BSY (1<< 8) -#define SPI_CTRL_CHAR_LEN_MASK 0x7F - -//////////////////////////////////////////////// -// I2C, Slave 3 -// See Wishbone I2C-Master Core Specification. - -#define I2C_BASE 0xC400 - -typedef struct { - volatile uint32_t prescaler_lo; // r/w - volatile uint32_t prescaler_hi; // r/w - volatile uint32_t ctrl; // r/w - volatile uint32_t data; // wr = transmit reg; rd = receive reg - volatile uint32_t cmd_status; // wr = command reg; rd = status reg -} i2c_regs_t; - -#define i2c_regs ((i2c_regs_t *) I2C_BASE) - -#define I2C_CTRL_EN (1 << 7) // core enable -#define I2C_CTRL_IE (1 << 6) // interrupt enable - -// -// STA, STO, RD, WR, and IACK bits are cleared automatically -// -#define I2C_CMD_START (1 << 7) // generate (repeated) start condition -#define I2C_CMD_STOP (1 << 6) // generate stop condition -#define I2C_CMD_RD (1 << 5) // read from slave -#define I2C_CMD_WR (1 << 4) // write to slave -#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1) -#define I2C_CMD_RSVD_2 (1 << 2) // reserved -#define I2C_CMD_RSVD_1 (1 << 1) // reserved -#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt - -#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK) -#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected -#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration -#define I2C_ST_RSVD_4 (1 << 4) // reserved -#define I2C_ST_RSVD_3 (1 << 3) // reserved -#define I2C_ST_RSVD_2 (1 << 2) // reserved -#define I2C_ST_TIP (1 << 1) // Transfer-in-progress -#define I2C_ST_IP (1 << 0) // Interrupt pending - - -//////////////////////////////////////////////// -// GPIO, Slave 4 -// -// These go to the daughterboard i/o pins - -#define GPIO_BASE 0xC800 - -typedef struct { - volatile uint32_t io; // tx data in high 16, rx in low 16 - volatile uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 - volatile uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB - volatile uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB -} gpio_regs_t; - -// each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric - -#define gpio_base ((gpio_regs_t *) GPIO_BASE) - -/////////////////////////////////////////////////// -// Packet Router Status, Slave 5 -// -// The buffers themselves are located in Slave 1, Packet Router RAM. -// The status registers are in Slave 5, Packet Router Status. -// The control register is in Slave 7, Settings Bus. - -#define ROUTER_STATUS_BASE 0xCC00 - -typedef struct { - volatile uint32_t _padding[8]; - volatile uint32_t status; - volatile uint32_t hw_config; // see below - volatile uint32_t time64_secs_rb; - volatile uint32_t time64_ticks_rb; - volatile uint32_t compat_num; - volatile uint32_t irqs; -} router_status_t; - -#define router_status ((router_status_t *) ROUTER_STATUS_BASE) - -// The hw_config register - -#define HWC_SIMULATION 0x80000000 -#define HWC_WB_CLK_DIV_MASK 0x0000000f - -/*! - * \brief return non-zero if we're running under the simulator - */ -inline static int -hwconfig_simulation_p(void) -{ - return router_status->hw_config & HWC_SIMULATION; -} - -/*! - * \brief Return Wishbone Clock divisor. - * The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor. - */ -inline static int -hwconfig_wishbone_divisor(void) -{ - return router_status->hw_config & HWC_WB_CLK_DIV_MASK; -} - -/////////////////////////////////////////////////// -// Ethernet Core, Slave 6 - -#define ETH_BASE 0xD000 - -#include "eth_mac_regs.h" - -#define eth_mac ((eth_mac_regs_t *) ETH_BASE) - -//////////////////////////////////////////////////// -// Settings Bus, Slave #7, Not Byte Addressable! -// -// Output-only from processor point-of-view. -// 1KB of address space (== 256 32-bit write-only regs) - - -#define MISC_OUTPUT_BASE 0xD400 -#define TX_PROTOCOL_ENGINE_BASE 0xD480 -#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -#define ROUTER_CTRL_BASE 0xD500 -#define LAST_SETTING_REG 0xD7FC // last valid setting register - -#define SR_MISC 0 -#define SR_TX_PROT_ENG 32 -#define SR_RX_PROT_ENG 48 -#define SR_ROUTER_CTRL 64 -#define SR_UDP_SM 96 -#define SR_TX_DSP 208 -#define SR_TX_CTRL 224 -#define SR_RX_DSP0 160 -#define SR_RX_DSP1 240 -#define SR_RX_CTRL0 176 -#define SR_RX_CTRL1 32 -#define SR_TIME64 192 -#define SR_SIMTIMER 198 -#define SR_LAST 255 - -#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) - -// --- packet router control regs --- - -typedef struct { - volatile uint32_t mode_ctrl; - volatile uint32_t ip_addr; - volatile uint32_t data_ports; //dsp0 (low 16) dsp1 (high 16) - volatile uint32_t iface_ctrl; -} router_ctrl_t; - -#define router_ctrl ((router_ctrl_t *) ROUTER_CTRL_BASE) - -// --- misc outputs --- - -typedef struct { - volatile uint32_t clk_ctrl; - volatile uint32_t serdes_ctrl; - volatile uint32_t adc_ctrl; - volatile uint32_t leds; - volatile uint32_t phy_ctrl; // LSB is reset line to eth phy - volatile uint32_t debug_mux_ctrl; - volatile uint32_t ram_page; // FIXME should go somewhere else... - volatile uint32_t flush_icache; // Flush the icache - volatile uint32_t led_src; // HW or SW control for LEDs -} output_regs_t; - -#define CLK_RESET (1<<4) -#define CLK_ENABLE (1<<3) | (1<<2) -#define CLK_SEL (1<<1) | (1<<0) - -#define SERDES_ENABLE 8 -#define SERDES_PRBSEN 4 -#define SERDES_LOOPEN 2 -#define SERDES_RXEN 1 - -#define ADC_CTRL_ON 0x0F -#define ADC_CTRL_OFF 0x00 - -// crazy order that matches the labels on the case - -#define LED_A (1 << 4) -#define LED_B (1 << 1) -#define LED_C (1 << 3) -#define LED_D (1 << 0) -#define LED_E (1 << 2) -// LED_F // controlled by CPLD -#define LED_RJ45 (1 << 5) - -#define output_regs ((output_regs_t *) MISC_OUTPUT_BASE) - -// --- udp tx regs --- - -typedef struct { - // Bits 19:16 are control info; bits 15:0 are data (see below) - // First two words are unused. - volatile uint32_t _nope[2]; - //--- ethernet header - 14 bytes--- - volatile struct{ - uint32_t mac_dst_0_1; //word 2 - uint32_t mac_dst_2_3; - uint32_t mac_dst_4_5; - uint32_t mac_src_0_1; - uint32_t mac_src_2_3; - uint32_t mac_src_4_5; - uint32_t ether_type; //word 8 - } eth_hdr; - //--- ip header - 20 bytes --- - volatile struct{ - uint32_t ver_ihl_tos; //word 9 - uint32_t total_length; - uint32_t identification; - uint32_t flags_frag_off; - uint32_t ttl_proto; - uint32_t checksum; - uint32_t src_addr_high; - uint32_t src_addr_low; - uint32_t dst_addr_high; - uint32_t dst_addr_low; //word 18 - } ip_hdr; - //--- udp header - 8 bytes --- - volatile struct{ - uint32_t src_port; //word 19 - uint32_t dst_port; - uint32_t length; - uint32_t checksum; //word 22 - } udp_hdr; - volatile uint32_t _pad[1]; - volatile uint32_t dsp0_port; - volatile uint32_t err0_port; - volatile uint32_t dsp1_port; - volatile uint32_t err1_port; -} sr_udp_sm_t; - -// control bits (all expect UDP_SM_LAST_WORD are mutually exclusive) - -// Insert a UDP source port from the table -#define UDP_SM_INS_UDP_SRC_PORT (1 << 21) - -// Insert a UDP dest port from the table -#define UDP_SM_INS_UDP_DST_PORT (1 << 20) - -// This is the last word of the header -#define UDP_SM_LAST_WORD (1 << 19) - -// Insert IP header checksum here. Data is the xor of 16'hFFFF and -// the values written into regs 9-13 and 15-18. -#define UDP_SM_INS_IP_HDR_CHKSUM (1 << 18) - -// Insert IP Length here (data ignored) -#define UDP_SM_INS_IP_LEN (1 << 17) - -// Insert UDP Length here (data ignore) -#define UDP_SM_INS_UDP_LEN (1 << 16) - -#define sr_udp_sm ((sr_udp_sm_t *) _SR_ADDR(SR_UDP_SM)) - -// --- VITA TX CTRL regs --- - -typedef struct { - volatile uint32_t num_chan; - volatile uint32_t clear_state; // clears out state machine, fifos, - volatile uint32_t report_sid; - volatile uint32_t policy; - volatile uint32_t cyc_per_up; - volatile uint32_t packets_per_up; -} sr_tx_ctrl_t; - -#define sr_tx_ctrl ((sr_tx_ctrl_t *) _SR_ADDR(SR_TX_CTRL)) - -// --- VITA RX CTRL regs --- -typedef struct { - // The following 3 are logically a single command register. - // They are clocked into the underlying fifo when time_ticks is written. - volatile uint32_t cmd; // {now, chain, num_samples(30) - volatile uint32_t time_secs; - volatile uint32_t time_ticks; -} sr_rx_ctrl_t; - -#define sr_rx_ctrl0 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL0)) -#define sr_rx_ctrl1 ((sr_rx_ctrl_t *) _SR_ADDR(SR_RX_CTRL1)) - -// ---------------------------------------------------------------- -// VITA49 64 bit time (write only) - /*! - * \brief Time 64 flags - * - * <pre> - * - * 3 2 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------------------------------------------------------+-+-+ - * | |S|P| - * +-----------------------------------------------------------+-+-+ - * - * P - PPS edge selection (0=negedge, 1=posedge, default=0) - * S - Source (0=sma, 1=mimo, 0=default) - * - * </pre> - */ -typedef struct { - volatile uint32_t secs; // value to set absolute secs to on next PPS - volatile uint32_t ticks; // value to set absolute ticks to on next PPS - volatile uint32_t flags; // flags - see chart above - volatile uint32_t imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) -} sr_time64_t; - -#define sr_time64 ((sr_time64_t *) _SR_ADDR(SR_TIME64)) - - -/* - * --- ethernet tx protocol engine regs (write only) --- - * - * These registers control the transmit portion of the ethernet - * protocol engine (out of USRP2). The protocol engine handles fifo - * status and sequence number insertion in outgoing packets, and - * automagically generates status packets when required to inform the - * host of changes in fifo availability. - * - * All outgoing packets have their fifo_status field set to the number - * of 32-bit lines of fifo available in the ethernet Rx fifo (see - * usrp2_eth_packet.h). Seqno's are set if FIXME, else 0. - * - * FIXME clean this up once we know how it's supposed to behave. - */ - -typedef struct { - volatile uint32_t flags; // not yet fully defined (channel?) - volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr - volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr - volatile uint32_t mac_src2345; // 4 bytes of destination mac addr - volatile uint32_t seqno; // Write to init seqno. It autoincs on match -} tx_proto_engine_regs_t; - -#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) - -/* - * --- ethernet rx protocol engine regs (write only) --- - * - * These registers control the receive portion of the ethernet - * protocol engine (into USRP2). The protocol engine offloads common - * packet inspection operations so that firmware has less to do on - * "fast path" packets. - * - * The registers define conditions which must be matched for a packet - * to be considered a "fast path" packet. If a received packet - * matches the src and dst mac address, ethertype, flags field, and - * expected seqno number it is considered a "fast path" packet, and - * the expected seqno is updated. If the packet fails to satisfy any - * of the above conditions it's a "slow path" packet, and the - * corresponding SLOWPATH flag will be set buffer_status register. - */ - -typedef struct { - volatile uint32_t flags; // not yet fully defined (channel?) - volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr - volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr - volatile uint32_t mac_src2345; // 4 bytes of destination mac addr - volatile uint32_t ethertype_pad; // ethertype in high 16-bits -} rx_proto_engine_regs_t; - -#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) - - - -/////////////////////////////////////////////////// -// Simple Programmable Interrupt Controller, Slave 8 - -#define PIC_BASE 0xD800 - -// Interrupt request lines -// Bit numbers (LSB == 0) that correpond to interrupts into PIC - -#define IRQ_BUFFER 0 // buffer manager -#define IRQ_ONETIME 1 -#define IRQ_SPI 2 -#define IRQ_I2C 3 -#define IRQ_PHY 4 // ethernet PHY -#define IRQ_UNDERRUN 5 -#define IRQ_OVERRUN 6 -#define IRQ_PPS 7 // pulse per second -#define IRQ_UART_RX 8 -#define IRQ_UART_TX 9 -#define IRQ_SERDES 10 -#define IRQ_CLKSTATUS 11 -#define IRQ_PERIODIC 12 - -#define IRQ_TO_MASK(x) (1 << (x)) - -#define PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER) -#define PIC_ONETIME_INT IRQ_TO_MASK(IRQ_ONETIME) -#define PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI) -#define PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C) -#define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY) -#define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN) -#define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN) -#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS) -#define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX) -#define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX) -#define PIC_SERDES IRQ_TO_MASK(IRQ_SERDES) -#define PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS) - -typedef struct { - volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level - volatile uint32_t polarity; // mask: 1 -> rising edge - volatile uint32_t mask; // mask: 1 -> disabled - volatile uint32_t pending; // mask: 1 -> pending; write 1's to clear pending ints -} pic_regs_t; - -#define pic_regs ((pic_regs_t *) PIC_BASE) - -// ---------------------------------------------------------------- -// WB_CLK_RATE is the time base for this -typedef struct { - volatile uint32_t onetime; // Number of wb clk cycles till the onetime interrupt - volatile uint32_t periodic; // Repeat rate of periodic interrupt -} sr_simple_timer_t; - -#define sr_simple_timer ((sr_simple_timer_t *) _SR_ADDR(SR_SIMTIMER)) - -/////////////////////////////////////////////////// -// UART, Slave 10 - -#define UART_BASE 0xE000 - -typedef struct { - // All elements are 8 bits except for clkdiv (16), but we use uint32 to make - // the hardware for decoding easier - volatile uint32_t clkdiv; // Set to 50e6 divided by baud rate (no x16 factor) - volatile uint32_t txlevel; // Number of spaces in the FIFO for writes - volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads - volatile uint32_t txchar; // Write characters to be sent here - volatile uint32_t rxchar; // Read received characters here -} uart_regs_t; - -#define uart_regs ((uart_regs_t *) UART_BASE) - -/////////////////////////////////////////////////// -// ATR Controller, Slave 11 - -#define ATR_BASE 0xE400 - -typedef struct { - volatile uint32_t v[16]; -} atr_regs_t; - -#define ATR_IDLE 0x0 // indicies into v -#define ATR_TX 0x1 -#define ATR_RX 0x2 -#define ATR_FULL 0x3 - -#define atr_regs ((atr_regs_t *) ATR_BASE) - -/////////////////////////////////////////////////// -// SD Card SPI interface, Slave 13 -// All regs are 8 bits wide, but are accessed as if they are 32 bits - -#define SDSPI_BASE 0xEC00 - -typedef struct { - volatile uint32_t status; // Write a 1 or 0 for controlling CS - volatile uint32_t clkdiv; - volatile uint32_t send_dat; - volatile uint32_t receive_dat; -} sdspi_regs_t; - -#define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE) - -/////////////////////////////////////////////////// -// External RAM interface, Slave 14 -// Pages are 1K. Page is 10 bits, set by a control register -// output_regs->ram_page - -#define EXTRAM_BASE 0xF000 -#define extram ((volatile uint32_t *) EXTRAM_BASE) - - -/////////////////////////////////////////////////// - -#endif - diff --git a/firmware/zpu/usrp2p/bootloader/init_bootloader.c b/firmware/zpu/usrp2p/bootloader/init_bootloader.c index 66481eb25..d797edce4 100644 --- a/firmware/zpu/usrp2p/bootloader/init_bootloader.c +++ b/firmware/zpu/usrp2p/bootloader/init_bootloader.c @@ -1,8 +1,19 @@ -/* -*- c++ -*- */ -/* - * Copyright 2010-2011 Ettus Research LLC - * - */ +// +// Copyright 2010-2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// #include <memory_map.h> #include <nonstdio.h> @@ -10,7 +21,6 @@ #include <xilinx_s3_icap.h> #include <spi_flash.h> #include <spi_flash_private.h> -//#include <clocks.h> #include <mdelay.h> #include <ihex.h> #include <bootloader_utils.h> @@ -19,12 +29,7 @@ #include <i2c.h> #include "usrp2/fw_common.h" -//void pic_interrupt_handler() __attribute__ ((interrupt_handler)); - -void pic_interrupt_handler() -{ - // nop stub -} +#define BUTTON_PUSHED ((router_status->irqs & PIC_BUTTON) ? 0 : 1) void load_ihex(void) { //simple IHEX parser to load proper records into RAM. loads program when it receives end of record. char buf[128]; //input data buffer diff --git a/firmware/zpu/usrp2p/ethernet.c b/firmware/zpu/usrp2p/ethernet.c index 03891f959..f5bd9f121 100644 --- a/firmware/zpu/usrp2p/ethernet.c +++ b/firmware/zpu/usrp2p/ethernet.c @@ -1,4 +1,5 @@ /* + * Copyright 2011 Ettus Research LLC * Copyright 2007 Free Software Foundation, Inc. * * This program is free software: you can redistribute it and/or modify @@ -21,7 +22,6 @@ #include "memory_map.h" #include "eth_phy.h" #include <eth_mac.h> -#include <eth_mac_regs.h> #include <pic.h> #include <hal_io.h> #include <nonstdio.h> diff --git a/fpga/usrp2/control_lib/ram_harvard.v b/fpga/usrp2/control_lib/ram_harvard.v index 948f9b36f..a190e20fd 100644 --- a/fpga/usrp2/control_lib/ram_harvard.v +++ b/fpga/usrp2/control_lib/ram_harvard.v @@ -27,9 +27,7 @@ module ram_harvard input dwb_we_i, output dwb_ack_o, input dwb_stb_i, - input [3:0] dwb_sel_i, - - input flush_icache ); + input [3:0] dwb_sel_i ); reg ack_d1; reg stb_d1; diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 7774ff076..04c17b647 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -251,28 +251,14 @@ module packet_router //////////////////////////////////////////////////////////////////// //dummy signals to connect the components below - wire [18:0] _udp_r2s_data, _udp_s2r_data; - wire _udp_r2s_valid, _udp_s2r_valid; - wire _udp_r2s_ready, _udp_s2r_ready; - wire [35:0] _com_out_data; wire _com_out_valid, _com_out_ready; - fifo36_to_fifo19 udp_fifo36_to_fifo19 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f36_datain(udp_out_data), .f36_src_rdy_i(udp_out_valid), .f36_dst_rdy_o(udp_out_ready), - .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) ); - prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .datain(_udp_r2s_data), .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready), - .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) ); - - fifo19_to_fifo36 udp_fifo19_to_fifo36 - (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .f19_datain(_udp_s2r_data), .f19_src_rdy_i(_udp_s2r_valid), .f19_dst_rdy_o(_udp_s2r_ready), - .f36_dataout(_com_out_data), .f36_src_rdy_o(_com_out_valid), .f36_dst_rdy_i(_com_out_ready) ); + .datain(udp_out_data), .src_rdy_i(udp_out_valid), .dst_rdy_o(udp_out_ready), + .dataout(_com_out_data), .src_rdy_o(_com_out_valid), .dst_rdy_i(_com_out_ready) ); fifo36_mux com_out_mux( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), diff --git a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd index b7e894232..f7743d602 100644 --- a/fpga/usrp2/opencores/zpu/core/zpu_config.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpu_config.vhd @@ -12,4 +12,9 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40";
-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
constant maxAddrBitIncIO : integer := 15;
+
+ -- start byte address of stack.
+ -- point to top of RAM - 2*words
+ constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"3ff8";
+
end zpu_config;
diff --git a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd index 24586b2f6..2450f14d3 100644 --- a/fpga/usrp2/opencores/zpu/core/zpu_core.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpu_core.vhd @@ -26,7 +26,6 @@ entity zpu_core is mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); @@ -203,7 +202,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - sp <= stack_start(maxAddrBitIncIO downto minAddrBit); + sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd index eee967a09..1a01563b8 100644 --- a/fpga/usrp2/opencores/zpu/core/zpupkg.vhd +++ b/fpga/usrp2/opencores/zpu/core/zpupkg.vhd @@ -73,7 +73,6 @@ package zpupkg is mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
diff --git a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd index 8af678b6a..294651fe2 100644 --- a/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd +++ b/fpga/usrp2/opencores/zpu/wishbone/zpu_system.vhd @@ -51,7 +51,7 @@ entity zpu_system is -- ZPU Control signals
enable : in std_logic;
interrupt : in std_logic;
- stack_start : in std_logic_vector(maxAddrBitIncIO downto 0);
+
zpu_status : out std_logic_vector(63 downto 0);
-- wishbone interfaces
@@ -84,7 +84,6 @@ begin mem_write => mem_write,
out_mem_addr => out_mem_addr,
mem_writeMask => mem_writeMask,
- stack_start => stack_start,
interrupt => interrupt,
zpu_status => zpu_status,
break => open);
diff --git a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd index a158ab9c0..23ff48c39 100644 --- a/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd +++ b/fpga/usrp2/opencores/zpu/zpu_top_pkg.vhd @@ -35,7 +35,7 @@ package zpu_top_pkg is -- ZPU Control signals enable : in std_logic; interrupt : in std_logic; - stack_start : in std_logic_vector(maxAddrBitIncIO downto 0); + zpu_status : out std_logic_vector(63 downto 0); -- wishbone interfaces diff --git a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd index 9735c4b54..48e5ee31d 100644 --- a/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd +++ b/fpga/usrp2/opencores/zpu/zpu_wb_top.vhd @@ -36,7 +36,6 @@ entity zpu_wb_top is -- misc zpu signals interrupt: in std_logic; - stack_start: in std_logic_vector(adr_w-1 downto 0); zpu_status: out std_logic_vector(63 downto 0) ); @@ -67,7 +66,6 @@ zpu_system0: zpu_system port map( areset => rst, enable => enb, interrupt => interrupt, - stack_start => stack_start, zpu_status => zpu_status, zpu_wb_i => zpu_wb_i, zpu_wb_o => zpu_wb_o diff --git a/fpga/usrp2/simple_gemac/Makefile.srcs b/fpga/usrp2/simple_gemac/Makefile.srcs index b82e64208..7bcc58c91 100644 --- a/fpga/usrp2/simple_gemac/Makefile.srcs +++ b/fpga/usrp2/simple_gemac/Makefile.srcs @@ -24,4 +24,6 @@ miim/eth_miim.v \ miim/eth_clockgen.v \ miim/eth_outputcontrol.v \ miim/eth_shiftreg.v \ +ethtx_realign.v \ +ethrx_realign.v \ )) diff --git a/fpga/usrp2/simple_gemac/ethrx_realign.v b/fpga/usrp2/simple_gemac/ethrx_realign.v new file mode 100644 index 000000000..0a369c914 --- /dev/null +++ b/fpga/usrp2/simple_gemac/ethrx_realign.v @@ -0,0 +1,72 @@ + +// NOTE: Will not work with single-line frames + +module ethrx_realign + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); + + reg [1:0] state; + reg [15:0] held; + reg [1:0] held_occ; + + wire xfer_in = src_rdy_i & dst_rdy_o; + wire xfer_out = src_rdy_o & dst_rdy_i; + + wire sof_in = datain[32]; + wire eof_in = datain[33]; + wire [1:0] occ_in = datain[35:34]; + wire sof_out, eof_out; + wire [1:0] occ_out; + + always @(posedge clk) + if(reset | clear) + begin + held <= 0; + held_occ <= 0; + end + else if(xfer_in) + begin + held <= datain[15:0]; + held_occ <= datain[35:34]; + end + + localparam RE_IDLE = 0; + localparam RE_HELD = 1; + localparam RE_DONE = 2; + + always @(posedge clk) + if(reset | clear) + state <= RE_IDLE; + else + case(state) + RE_IDLE : + if(src_rdy_i & dst_rdy_i) + if(eof_in) + state <= RE_DONE; + else + state <= RE_HELD; + + RE_HELD : + if(src_rdy_i & dst_rdy_i & eof_in) + if((occ_in==0)|(occ_in==3)) + state <= RE_DONE; + else + state <= RE_IDLE; + + RE_DONE : + if(dst_rdy_i) + state <= RE_IDLE; + + endcase // case (state) + + + assign sof_out = (state == RE_IDLE); + assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2); + assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) : + (occ_in == 1) ? 3 : 0; + + assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; + assign src_rdy_o = (state == RE_DONE) | src_rdy_i; + assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD)); +endmodule // ethrx_realign diff --git a/fpga/usrp2/simple_gemac/ethtx_realign.v b/fpga/usrp2/simple_gemac/ethtx_realign.v new file mode 100644 index 000000000..be53abf4c --- /dev/null +++ b/fpga/usrp2/simple_gemac/ethtx_realign.v @@ -0,0 +1,77 @@ + +//////////////////////////////////////////////////////////////////////// +// Ethernet TX - Realign +// +// - removes a 2-byte pad from the front a fifo36 stream +// - occupancy is preserved +// + +module ethtx_realign + (input clk, input reset, input clear, + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); + + reg [1:0] state; + reg [15:0] held; + reg [1:0] held_occ; + reg held_sof; + + wire xfer_in = src_rdy_i & dst_rdy_o; + wire xfer_out = src_rdy_o & dst_rdy_i; + + wire sof_in = datain[32]; + wire eof_in = datain[33]; + wire [1:0] occ_in = datain[35:34]; + wire occ_low = occ_in[1] ^ occ_in[0]; //occ is 1 or 2 + + always @(posedge clk) + if(reset | clear) + begin + held <= 0; + held_occ <= 0; + held_sof <= 0; + end + else if(xfer_in) + begin + held <= datain[15:0]; + held_occ <= occ_in; + held_sof <= sof_in; + end + + localparam RE_IDLE = 0; + localparam RE_HELD = 1; + localparam RE_DONE = 2; + + always @(posedge clk) + if(reset | clear) + state <= RE_IDLE; + else + case(state) + RE_IDLE : + if(xfer_in & eof_in) + state <= RE_DONE; + else if(xfer_in & sof_in) + state <= RE_HELD; + + RE_HELD : + if(xfer_in & xfer_out & eof_in) + if(occ_low) + state <= RE_IDLE; + else + state <= RE_DONE; + + RE_DONE : + if(xfer_out) + state <= RE_IDLE; + + endcase // case (state) + + wire sof_out = held_sof; + wire eof_out = (state == RE_HELD)? (eof_in & occ_low) : (state == RE_DONE); + wire [1:0] occ_out = ((state == RE_DONE)? held_occ : occ_in) ^ 2'b10; //(occ + 2)%4 + + assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; + assign src_rdy_o = (state == RE_HELD)? src_rdy_i : (state == RE_DONE); + assign dst_rdy_o = (state == RE_HELD)? dst_rdy_i : (state == RE_IDLE); + +endmodule // ethtx_realign diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v index b783729d5..8390eb2c6 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -106,17 +106,22 @@ module simple_gemac_wrapper // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; wire [7:0] tx_ll_data; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + wire [35:0] tx_f36_data_int1, tx_f36_data_int2; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2; fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); - + + ethtx_realign ethtx_realign + (.clk(tx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), + .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); + fifo36_to_ll8 fifo36_to_ll8 (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v index c155b7d41..2ac8b9be1 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -90,7 +90,6 @@ module simple_gemac_wrapper19 .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); - //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo (.wclk(rx_clk), .datain(rx_f19_data_int2), .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space), diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index 79470de9e..0e6120ec6 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -136,18 +136,22 @@ module u2_core input [3:0] clock_divider ); - localparam SR_MISC = 0; // Uses 9 regs - localparam SR_BUF_POOL = 64; // Uses 4 regs - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP0 = 160; // 16 - localparam SR_RX_CTRL0 = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - localparam SR_RX_DSP1 = 240; - localparam SR_RX_CTRL1 = 32; - + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs @@ -208,23 +212,23 @@ module u2_core wire m0_err, m0_rty; wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; - wb_1master #(.decode_w(6), - .s0_addr(6'b0000_00),.s0_mask(6'b100000), - .s1_addr(6'b1000_00),.s1_mask(6'b110000), - .s2_addr(6'b1100_00),.s2_mask(6'b111111), - .s3_addr(6'b1100_01),.s3_mask(6'b111111), - .s4_addr(6'b1100_10),.s4_mask(6'b111111), - .s5_addr(6'b1100_11),.s5_mask(6'b111111), - .s6_addr(6'b1101_00),.s6_mask(6'b111111), - .s7_addr(6'b1101_01),.s7_mask(6'b111111), - .s8_addr(6'b1101_10),.s8_mask(6'b111111), - .s9_addr(6'b1101_11),.s9_mask(6'b111111), - .sa_addr(6'b1110_00),.sa_mask(6'b111111), - .sb_addr(6'b1110_01),.sb_mask(6'b111111), - .sc_addr(6'b1110_10),.sc_mask(6'b111111), - .sd_addr(6'b1110_11),.sd_mask(6'b111111), - .se_addr(6'b1111_00),.se_mask(6'b111111), - .sf_addr(6'b1111_01),.sf_mask(6'b111111), + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // SD Card access + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -319,13 +323,12 @@ module u2_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone // I-port connects directly to processor and ram loader - wire flush_icache; ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), @@ -337,12 +340,8 @@ module u2_core .if_adr(16'b0), .if_data(), .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); - setting_reg #(.my_addr(SR_MISC+7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 wire rd0_ready_i, rd0_ready_o; @@ -417,7 +416,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -434,7 +433,7 @@ module u2_core // Ethernet MAC Slave #6 simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), @@ -491,7 +490,7 @@ module u2_core setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi index a7d051630..a0a3e13c5 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -1,5 +1,5 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4a20400_3a0b0b0b_0bae840c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4df2d_88080b0b_80088408; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b10400_3a0b0b0b_0bae940c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4ee2d_88080b0b_80088408; defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; @@ -18,178 +18,178 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_f0738306_0b0b0bad_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_992d5050_0b0b0b9e_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_80738306_0b0b0bae_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_a82d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_da2d5050_0b0b0b9f_88087575_80088408; defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae800c_810b0b0b; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae900c_810b0b0b; defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_ff3f0410_81f33f9d; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_8e3f0410_81f33f9e; defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; -defparam bootram.RAM0.INIT_23=256'hc00c8290_a0800bb5_b5bc0c82_0b0b0b0b_38838080_08822eb9_a138ae84_8008802e; -defparam bootram.RAM0.INIT_24=256'h80808480_b5c00cf8_8082800b_bc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5c4; -defparam bootram.RAM0.INIT_25=256'h0ba6b00b_c00c0b0b_80940bb5_0c80c0a8_0b0bb5bc_808c0b0b_0480c0a8_0bb5c40c; -defparam bootram.RAM0.INIT_26=256'hae8c0c70_92388412_5270802e_08700852_a338ae8c_c8335170_ff3d0db5_b5c40c04; -defparam bootram.RAM0.INIT_27=256'hb808802e_0b0b0bb5_04803d0d_833d0d04_0bb5c834_70f03881_70085252_2dae8c08; -defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5b8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; -defparam bootram.RAM0.INIT_29=256'h518bb43f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; -defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_b43fa6b4_52735198_38765378_ff74278f_775481ff_8008b238; -defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6ec51_a6b85184_3f91c23f_b4518598_068f38a6_812e0981; -defparam bootram.RAM0.INIT_2C=256'h3fa6f051_e03f86d6_85e13f8e_81a08c0c_fc3f800b_80e45189_81a08c0c_0d81ff0b; -defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81c6b4_805182ed_81ff0655_ee3f8008_84e23f83; -defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f82_a6388151_8008802e_5190b53f_81fc8080_5184bd3f_c338a79c; -defparam bootram.RAM0.INIT_2F=256'hf8518484_3f8a39a7_73519191_5184913f_c43fa7bc_8eaa3f90_fc808051_ffff5281; -defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a8fc_8008802e_518fa03f_3fb0800a_d05183f8_74b238a8_3ffea13f; -defparam bootram.RAM0.INIT_31=256'h8fc63f80_98800a51_5183cd3f_d83fa9b4_800a5190_88df3fb0_3f82ac51_815181f9; -defparam bootram.RAM0.INIT_32=256'h5183a53f_bb3faab0_800a518d_ffff5298_80805380_83ba3f82_38aa8451_08802eaa; -defparam bootram.RAM0.INIT_33=256'h80085480_518f893f_81fc8080_5183913f_ba39ab90_3faad451_a43f8fc9_82ac5188; -defparam bootram.RAM0.INIT_34=256'hac5187e9_82ea3f82_3faab051_80518d80_5281fc80_5380ffff_38828080_08802eb5; -defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a7f851_3f81548a_80518fd5_5187da3f_db3f82ac_a7bc5182_3f8f8e3f; +defparam bootram.RAM0.INIT_23=256'hd00c8290_a0800bb5_b5cc0c82_0b0b0b0b_38838080_08822eb9_a138ae94_9008802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5d00cf8_8082800b_cc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5d4; +defparam bootram.RAM0.INIT_25=256'h0ba6c00b_d00c0b0b_80940bb5_0c80c0a8_0b0bb5cc_808c0b0b_0480c0a8_0bb5d40c; +defparam bootram.RAM0.INIT_26=256'hae9c0c70_92388412_5270802e_08700852_a338ae9c_d8335170_ff3d0db5_b5d40c04; +defparam bootram.RAM0.INIT_27=256'hc808802e_0b0b0bb5_04803d0d_833d0d04_0bb5d834_70f03881_70085252_2dae9c08; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5c8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bc33f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c33fa6c4_52735198_38765378_ff74278f_775482ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6fc51_a6c85184_3f91d13f_c4518598_068f38a6_812e0981; +defparam bootram.RAM0.INIT_2C=256'h3fa78051_ef3f86e5_85e63f8e_81e08c0c_8b3f800b_80e4518a_81e08c0c_0d81ff0b; +defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81b8b4_805182ed_81ff0655_ee3f8008_84e23f83; +defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f83_a6388151_8008802e_5190c43f_81fc8080_5184bd3f_c338a7ac; +defparam bootram.RAM0.INIT_2F=256'h88518484_3f8a39a8_735191a0_5184913f_d33fa7cc_8eb93f90_fc808051_ffff5281; +defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a98c_8008802e_518faf3f_3fb0800a_e05183f8_74b238a8_3ffea13f; +defparam bootram.RAM0.INIT_31=256'h8fd53f80_98800a51_5183cd3f_e73fa9c4_800a5190_88ee3fb0_3f82ac51_815181f9; +defparam bootram.RAM0.INIT_32=256'h5183a53f_ca3faac0_800a518d_ffff5298_80805380_83ba3f83_38aa9451_08802eaa; +defparam bootram.RAM0.INIT_33=256'h80085480_518f983f_81fc8080_5183913f_ba39aba0_3faae451_b33f8fd8_82ac5188; +defparam bootram.RAM0.INIT_34=256'hac5187f8_82ea3f82_3faac051_80518d8f_5281fc80_5380ffff_38838080_08802eb5; +defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a88851_3f81548a_80518fe4_5187e93f_db3f82ac_a7cc5182_3f8f9d3f; defparam bootram.RAM0.INIT_36=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_0c863d0d_e33f7380; defparam bootram.RAM0.INIT_37=256'hff065185_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473; -defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a5186fd_81ff0654_cf3f8008; +defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a51878c_81ff0654_de3f8008; defparam bootram.RAM0.INIT_39=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533; defparam bootram.RAM0.INIT_3A=256'h70525684_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d; -defparam bootram.RAM0.INIT_3B=256'h3f800881_755183b2_76537b52_77259738_2e9e3880_56547380_81ff0670_ef3f8008; +defparam bootram.RAM0.INIT_3B=256'h3f800881_755183c1_76537b52_77259738_2e9e3880_56547380_81ff0670_fe3f8008; defparam bootram.RAM0.INIT_3C=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056; defparam bootram.RAM0.INIT_3D=256'h3d0d04fb_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff; -defparam bootram.RAM0.INIT_3E=256'h5581bb3f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; -defparam bootram.RAM0.INIT_3F=256'h800b800c_51819f3f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; +defparam bootram.RAM0.INIT_3E=256'h5581c03f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; +defparam bootram.RAM0.INIT_3F=256'h800b800c_5181a43f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; defparam bootram.RAM1.INIT_00=256'h81135374_55558439_76787055_04fc3d0d_3f833d0d_528051de_ff3d0d73_843d0d04; -defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181b23f; -defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533ae90_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; -defparam bootram.RAM1.INIT_03=256'hae901333_3d0d8053_3d0d04fe_0c535183_05702272_7510abcc_81ce8005_0d73a029; -defparam bootram.RAM1.INIT_04=256'h0d767856_0d04fc3d_e738843d_53827325_d13f8113_33527251_3fae9413_527251c9; -defparam bootram.RAM1.INIT_05=256'h73a02981_7351df3f_87388d52_2e098106_33537281_38ae9014_09810694_54748a2e; -defparam bootram.RAM1.INIT_06=256'hce800552_73a02981_04ff3d0d_0c863d0d_38748c15_72802ef8_84140853_ce800554; -defparam bootram.RAM1.INIT_07=256'hc6a40870_c2880c81_0d800b81_0d04ff3d_800c833d_38901208_70802ef8_88120851; -defparam bootram.RAM1.INIT_08=256'h2a81c284_800c7088_ff0681c2_70227081_10ae9805_38845170_84712583_8f065151; -defparam bootram.RAM1.INIT_09=256'h81517180_33555354_88059705_0d767802_0d04fd3d_880c833d_800b81c2_0c515181; -defparam bootram.RAM1.INIT_0A=256'h81900b81_81c28c0c_72108107_5170f138_81065151_70862a70_81c29008_2e818638; -defparam bootram.RAM1.INIT_0B=256'h06708132_872a7081_c2900870_70f13881_06515151_812a7081_c2900870_c2900c81; -defparam bootram.RAM1.INIT_0C=256'h0c81c290_7081c290_8338a051_5171812e_b13880e8_3871802e_70802eba_51515151; -defparam bootram.RAM1.INIT_0D=256'hcc398151_34ff1252_70810556_08517074_3881c28c_515170f1_70810651_0870812a; -defparam bootram.RAM1.INIT_0E=256'h535481c2_97053355_78028805_fd3d0d76_853d0d04_0c70800c_0b81c290_883980c0; -defparam bootram.RAM1.INIT_0F=256'h81905170_802e8438_81d05171_81c28c0c_f1387210_51515170_2a708106_90087086; -defparam bootram.RAM1.INIT_10=256'h81067081_70872a70_81c29008_5170f138_81065151_70812a70_81c29008_81c2900c; -defparam bootram.RAM1.INIT_11=256'h2e833890_d0517181_c28c0c80_38733381_802e80c5_80cf3871_5170802e_32515151; -defparam bootram.RAM1.INIT_12=256'h2a708106_90087087_f13881c2_51515170_2a708106_90087081_900c81c2_517081c2; -defparam bootram.RAM1.INIT_13=256'h81c2900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38_51515170_70813251; -defparam bootram.RAM1.INIT_14=256'h52717425_70a23870_06515254_0870810a_7581c6a4_04fd3d0d_0c853d0d_80517080; -defparam bootram.RAM1.INIT_15=256'h853d0d04_1252e239_27f13881_868d9f71_74315151_c6ac0870_ac085381_9b3881c6; -defparam bootram.RAM1.INIT_16=256'h06515171_127081ff_269638c9_527180da_ff065152_a9117081_8f0533ff_ff3d0d02; -defparam bootram.RAM1.INIT_17=256'h335358ff_58568076_3d0d797b_3d0d04f9_70800c83_ff065151_d0127081_b9268938; -defparam bootram.RAM1.INIT_18=256'h06721970_147081ff_aa387281_5371782e_81173353_ef38810b_09810682_5371ba2e; -defparam bootram.RAM1.INIT_19=256'h71d83881_70335152_bd387216_71802e82_53515452_06515151_337080c4_33abdd11; -defparam bootram.RAM1.INIT_1A=256'h7084190c_ff067205_3f800881_5252feec_06821733_842b9ff0_fb3f8008_163351fe; -defparam bootram.RAM1.INIT_1B=256'h80068417_8c2bbfe0_cb3f8008_163351fe_828a3883_54fd5374_11335753_7010178b; -defparam bootram.RAM1.INIT_1C=256'h9ff00673_8008842b_53fea93f_85173352_80067305_882b83fe_bb3f8008_335253fe; -defparam bootram.RAM1.INIT_1D=256'h842b9ff0_873f8008_163351fe_88180c87_ff067305_3f800881_5253fe98_05861733; -defparam bootram.RAM1.INIT_1E=256'hff068c19_89057081_d2387410_74742780_52717734_3f800812_5252fdf8_06881733; -defparam bootram.RAM1.INIT_1F=256'h53fdc13f_06723352_842b9ff0_cf3f8008_565152fd_52335552_70708105_08177119; -defparam bootram.RAM1.INIT_20=256'h51515284_065a525b_197081ff_81ff0681_33701a70_17081570_7274348c_80081353; -defparam bootram.RAM1.INIT_21=256'h81ff0673_19703070_05547305_0571882a_08783372_17088818_ffb03884_17087526; -defparam bootram.RAM1.INIT_22=256'h3f800812_5252fce4_068a1533_842b9ff0_f33f8008_515354fc_3356545b_101a8911; -defparam bootram.RAM1.INIT_23=256'h3d0d0480_72800c89_83398053_8539fe53_81068938_77722e09_5152fb53_7081ff06; -defparam bootram.RAM1.INIT_24=256'h337880ff_0d029305_0d04fe3d_f138823d_51515170_2a708106_90087088_3d0d81d6; -defparam bootram.RAM1.INIT_25=256'h7681d680_5170f138_81065151_70882a70_81d69008_80075353_060780c0_067a8c80; -defparam bootram.RAM1.INIT_26=256'h3881d690_72802e96_900c7251_800781d6_980c7182_ff0681d6_900c7581_0c7181d6; -defparam bootram.RAM1.INIT_27=256'h810b81d6_04fc3d0d_0c843d0d_08517080_3881d680_515170f1_70810651_0870882a; -defparam bootram.RAM1.INIT_28=256'h800b81d6_56fee43f_f63d0d7d_863d0d04_51ff873f_53805280_55885480_940c8880; -defparam bootram.RAM1.INIT_29=256'h88a80b81_81d6980c_800c810b_882b81d6_d6840c7c_0c8b0b81_0b81d690_980c8880; -defparam bootram.RAM1.INIT_2A=256'h900c8a80_800b81d6_80d33888_54737627_3f7e5580_900cfeb3_a80b81d6_d6900c8a; -defparam bootram.RAM1.INIT_2B=256'h883d7675_d680085b_84085a81_085981d6_5881d688_81d68c08_0cfe983f_0b81d690; -defparam bootram.RAM1.INIT_2C=256'h57348112_75708105_17517033_27913871_80527173_83387053_53707327_31525790; -defparam bootram.RAM1.INIT_2D=256'hc0526851_70545780_3d0d883d_3d0d04ea_d6980c8c_39800b81_1454ffa9_52ec3972; -defparam bootram.RAM1.INIT_2E=256'h81069438_81aa2e09_2e9d3873_547381ff_17703351_05575574_0284059d_fed23f80; -defparam bootram.RAM1.INIT_2F=256'h5473800c_27d13880_1555be75_548b3981_06853881_992e0981_51547381_74167033; -defparam bootram.RAM1.INIT_30=256'h85f73f80_d8527351_558453ab_fe823f80_84527951_3d705454_f93d0d86_983d0d04; -defparam bootram.RAM1.INIT_31=256'h97053370_fd3d0d02_a0940c04_04810b81_0c893d0d_81557480_81068338_08752e09; -defparam bootram.RAM1.INIT_32=256'h2ba00671_90067483_07077310_88067173_0672812a_71832a84_71872a07_852a8206; -defparam bootram.RAM1.INIT_33=256'h51525351_81d4800c_7081ff06_78872b07_06707207_852b80c0_81ff0676_73070770; -defparam bootram.RAM1.INIT_34=256'hff51ff98_ff9e3f81_5381ff51_81d00a07_74d00a06_04fe3d0d_52853d0d_55525555; -defparam bootram.RAM1.INIT_35=256'h81ff0652_72882a70_51ff813f_873f80e1_3fb251ff_9951ff8c_ff923f81_3f81aa51; -defparam bootram.RAM1.INIT_36=256'hdb3f7290_982a51fe_fee23f72_3f818151_b251fee8_51feed3f_7281ff06_52fef53f; -defparam bootram.RAM1.INIT_37=256'hfeba3fa0_bf3f8e51_3f8051fe_a151fec4_feca3f81_cf3fb051_065253fe_2a7081ff; -defparam bootram.RAM1.INIT_38=256'h8c0cf93d_398c0802_3d0d04ff_fea63f84_ab3f8051_3fa051fe_8051feb0_51feb53f; -defparam bootram.RAM1.INIT_39=256'h800b8c08_0888050c_0508308c_388c0888_088025ab_8c088805_08fc050c_0d800b8c; -defparam bootram.RAM1.INIT_3A=256'h088c0508_fc050c8c_05088c08_0c8c08f4_8c08f405_8838810b_08fc0508_f4050c8c; -defparam bootram.RAM1.INIT_3B=256'h38810b8c_fc050888_050c8c08_0b8c08f0_8c050c80_08308c08_8c088c05_8025ab38; -defparam bootram.RAM1.INIT_3C=256'h81a73f80_88050851_08528c08_8c088c05_050c8053_088c08fc_8c08f005_08f0050c; -defparam bootram.RAM1.INIT_3D=256'h8c08f805_08f8050c_0508308c_388c08f8_08802e8c_8c08fc05_f8050c54_08708c08; -defparam bootram.RAM1.INIT_3E=256'h88050880_050c8c08_0b8c08fc_fb3d0d80_08028c0c_8c0c048c_54893d0d_0870800c; -defparam bootram.RAM1.INIT_3F=256'h8c388c08_05088025_0c8c088c_8c08fc05_050c810b_308c0888_08880508_2593388c; -defparam bootram.RAM2.INIT_00=256'h8c08f805_3f800870_050851ad_528c0888_088c0508_0c81538c_8c088c05_8c050830; -defparam bootram.RAM2.INIT_01=256'h800c5487_f8050870_050c8c08_308c08f8_08f80508_2e8c388c_fc050880_0c548c08; -defparam bootram.RAM2.INIT_02=256'h088c0508_f8050c8c_800b8c08_08fc050c_0d810b8c_8c0cfd3d_048c0802_3d0d8c0c; -defparam bootram.RAM2.INIT_03=256'h088c0508_2499388c_088c0508_38800b8c_08802ea3_8c08fc05_0827ac38_8c088805; -defparam bootram.RAM2.INIT_04=256'h388c088c_802e80c9_08fc0508_0cc9398c_8c08fc05_fc050810_050c8c08_108c088c; -defparam bootram.RAM2.INIT_05=256'hf805088c_050c8c08_318c0888_088c0508_8805088c_a1388c08_88050826_05088c08; -defparam bootram.RAM2.INIT_06=256'h2a8c088c_8c050881_050c8c08_2a8c08fc_fc050881_050c8c08_078c08f8_08fc0508; -defparam bootram.RAM2.INIT_07=256'h8c08f805_0c518d39_8c08f405_88050870_8f388c08_0508802e_398c0890_050cffaf; -defparam bootram.RAM2.INIT_08=256'h56528372_78777956_04fc3d0d_3d0d8c0c_08800c85_8c08f405_f4050c51_08708c08; -defparam bootram.RAM2.INIT_09=256'h72712e09_74335253_a0387433_5271ff2e_b038ff12_5170802e_74078306_278c3874; -defparam bootram.RAM2.INIT_0A=256'h04747454_0c863d0d_38800b80_098106e2_5571ff2e_ff145455_81158115_8106bd38; -defparam bootram.RAM2.INIT_0B=256'h55ffaf39_38707355_718326e9_14545451_118414fc_068f3884_082e0981_51700873; -defparam bootram.RAM2.INIT_0C=256'h83065170_38727507_8f72278c_55555555_7670797b_04fc3d0d_0c863d0d_72713180; -defparam bootram.RAM2.INIT_0D=256'hff2e0981_ff125271_81055634_54337470_72708105_ff2e9838_ff125271_802ea738; -defparam bootram.RAM2.INIT_0E=256'h54087170_72708405_8405530c_54087170_72708405_0d047451_800c863d_06ea3874; -defparam bootram.RAM2.INIT_0F=256'hf0125271_8405530c_54087170_72708405_8405530c_54087170_72708405_8405530c; -defparam bootram.RAM2.INIT_10=256'h387054ff_718326ed_0cfc1252_70840553_05540871_38727084_83722795_8f26c938; -defparam bootram.RAM2.INIT_11=256'ha4528151_e3c63fae_0ce4a83f_3873b5cc_72812e98_84085454_0d800bae_8339fd3d; -defparam bootram.RAM2.INIT_12=256'h51843f00_a53f8008_528151e6_af3faea4_e4913fe3_72b5cc0c_08519b3f_e6bc3f80; -defparam bootram.RAM2.INIT_13=256'hff058171_18841908_d9388188_77802e80_085a545a_0882c811_0d7baea8_ff39f73d; -defparam bootram.RAM2.INIT_14=256'h77065372_81801908_88055656_822b7811_24b53873_e9388074_80742480_2b595559; -defparam bootram.RAM2.INIT_15=256'h57547380_812c5a57_17fc1779_2dff14fc_74085372_53537951_78167008_802eb538; -defparam bootram.RAM2.INIT_16=256'h2dff14fc_74085372_51f8c03f_08a53879_0853bc13_ad38aea8_085877ff_25d63877; -defparam bootram.RAM2.INIT_17=256'h53722d79_51bc1308_ff943972_d2398057_25ffa938_57547380_812c5a57_17fc1779; -defparam bootram.RAM2.INIT_18=256'h5270ff2e_12700852_38702dfc_70ff2e91_70085252_ac0bfc05_ff3d0db5_51f8943f; -defparam bootram.RAM2.INIT_19=256'h523a206d_4552524f_4f4b0000_00000040_3f040000_0404e398_38833d0d_098106f1; -defparam bootram.RAM2.INIT_1A=256'h49484558_20696e20_4261636b_65642120_7475726e_65207265_696d6167_61696e20; -defparam bootram.RAM2.INIT_1B=256'h6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00_64206d6f_206c6f61; -defparam bootram.RAM2.INIT_1C=256'h53746172_6e0a0000_6974696f_55206564_61205a50_756c7472_70657220_72207375; -defparam bootram.RAM2.INIT_1D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM2.INIT_1E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; -defparam bootram.RAM2.INIT_1F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; -defparam bootram.RAM2.INIT_20=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; -defparam bootram.RAM2.INIT_21=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; -defparam bootram.RAM2.INIT_22=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; -defparam bootram.RAM2.INIT_23=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; -defparam bootram.RAM2.INIT_24=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; -defparam bootram.RAM2.INIT_25=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; -defparam bootram.RAM2.INIT_26=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; -defparam bootram.RAM2.INIT_27=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; -defparam bootram.RAM2.INIT_28=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; -defparam bootram.RAM2.INIT_29=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM2.INIT_2A=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374; -defparam bootram.RAM2.INIT_2B=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; -defparam bootram.RAM2.INIT_2C=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576; -defparam bootram.RAM2.INIT_2D=256'h61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d_696f6e20; -defparam bootram.RAM2.INIT_2E=256'h00202020_0b0b0b0b_01b200d9_05160364_14580a2c_2e2e2e00_77617265_6669726d; -defparam bootram.RAM2.INIT_2F=256'h20881010_20202020_20202020_20202020_20202020_28282820_20202828_20202020; -defparam bootram.RAM2.INIT_30=256'h10104141_10101010_04040410_04040404_10040404_10101010_10101010_10101010; -defparam bootram.RAM2.INIT_31=256'h10104242_10101010_01010101_01010101_01010101_01010101_01010101_41414141; -defparam bootram.RAM2.INIT_32=256'h20000000_10101010_02020202_02020202_02020202_02020202_02020202_42424242; -defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181bc3f; +defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533aea0_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; +defparam bootram.RAM1.INIT_03=256'hfe3d0d80_833d0d04_0c545151_05702272_7610abdc_82908005_14708429_0d738429; +defparam bootram.RAM1.INIT_04=256'h3d0d04fc_25e73884_13538273_51cc3f81_13335272_c43faea4_33527251_53aea013; +defparam bootram.RAM1.INIT_05=256'h527351df_0687388d_812e0981_14335372_9438aea0_2e098106_5654748a_3d0d7678; +defparam bootram.RAM1.INIT_06=256'h3d0d04ff_8c150c86_2ef83874_08537280_55538414_82908005_14708429_3f738429; +defparam bootram.RAM1.INIT_07=256'h0c833d0d_90120880_802ef838_12085170_05535188_29829080_29147084_3d0d7384; +defparam bootram.RAM1.INIT_08=256'haea80570_84517010_71258338_06515184_a408708f_880c81b8_800b81a8_04ff3d0d; +defparam bootram.RAM1.INIT_09=256'h04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c_0c70882a_0681a880_227081ff; +defparam bootram.RAM1.INIT_0A=256'h06515151_862a7081_a8900870_81863881_5171802e_55535481_05970533_76780288; +defparam bootram.RAM1.INIT_0B=256'h51515170_2a708106_90087081_900c81a8_900b81a8_a88c0c81_10810781_70f13872; +defparam bootram.RAM1.INIT_0C=256'h3880e851_71802eb1_802eba38_51515170_70813251_2a708106_90087087_f13881a8; +defparam bootram.RAM1.INIT_0D=256'h81a88c08_5170f138_81065151_70812a70_81a89008_81a8900c_38a05170_71812e83; +defparam bootram.RAM1.INIT_0E=256'h3d0d04fd_70800c85_81a8900c_3980c00b_39815188_ff1252cc_81055634_51707470; +defparam bootram.RAM1.INIT_0F=256'h38721081_515170f1_70810651_0870862a_5481a890_05335553_02880597_3d0d7678; +defparam bootram.RAM1.INIT_10=256'h06515151_812a7081_a8900870_a8900c81_90517081_2e843881_d0517180_a88c0c81; +defparam bootram.RAM1.INIT_11=256'h2e80c538_cf387180_70802e80_51515151_06708132_872a7081_a8900870_70f13881; +defparam bootram.RAM1.INIT_12=256'h70810651_0870812a_0c81a890_7081a890_83389051_5171812e_8c0c80d0_733381a8; +defparam bootram.RAM1.INIT_13=256'h14ff1353_2e8e3881_51517080_81325151_70810670_0870872a_3881a890_515170f1; +defparam bootram.RAM1.INIT_14=256'h81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80_80c00b81_81518a39_54ffb739; +defparam bootram.RAM1.INIT_15=256'h31515186_ac087074_085381b8_3881b8ac_7174259b_a2387052_51525470_70810a06; +defparam bootram.RAM1.INIT_16=256'h06515252_117081ff_0533ffa9_3d0d028f_3d0d04ff_52e23985_f1388112_8d9f7127; +defparam bootram.RAM1.INIT_17=256'h800c833d_06515170_127081ff_268938d0_515171b9_7081ff06_9638c912_7180da26; +defparam bootram.RAM1.INIT_18=256'h17335353_38810b81_810682ef_71ba2e09_5358ff53_56807633_0d797b58_0d04f93d; +defparam bootram.RAM1.INIT_19=256'h51545271_51515153_7080c406_abed1133_72197033_7081ff06_38728114_71782eaa; +defparam bootram.RAM1.INIT_1A=256'h82173352_2b9ff006_3f800884_3351fefb_d8388116_33515271_38721670_802e82bd; +defparam bootram.RAM1.INIT_1B=256'h8a388316_fd537482_33575354_10178b11_84190c70_06720570_800881ff_52feec3f; +defparam bootram.RAM1.INIT_1C=256'h06730585_2b83fe80_3f800888_5253febb_06841733_2bbfe080_3f80088c_3351fecb; +defparam bootram.RAM1.INIT_1D=256'h06730588_800881ff_53fe983f_86173352_f0067305_08842b9f_fea93f80_17335253; +defparam bootram.RAM1.INIT_1E=256'h71773474_80081252_52fdf83f_88173352_2b9ff006_3f800884_3351fe87_180c8716; +defparam bootram.RAM1.INIT_1F=256'h5152fdcf_33555256_70810552_17711970_068c1908_057081ff_38741089_742780d2; +defparam bootram.RAM1.INIT_20=256'h701a7081_08157033_74348c17_08135372_fdc13f80_72335253_2b9ff006_3f800884; +defparam bootram.RAM1.INIT_21=256'h78337205_08881808_b0388417_087526ff_51528417_5a525b51_7081ff06_ff068119; +defparam bootram.RAM1.INIT_22=256'h3f800884_5354fcf3_56545b51_1a891133_ff067310_70307081_54730519_71882a05; +defparam bootram.RAM1.INIT_23=256'h06893885_722e0981_52fb5377_81ff0651_80081270_52fce43f_8a153352_2b9ff006; +defparam bootram.RAM1.INIT_24=256'h515170f1_70810651_0870882a_0d82e090_0d04803d_800c893d_39805372_39fe5383; +defparam bootram.RAM1.INIT_25=256'he0900870_07535382_0780c080_7a8c8006_7880ff06_02930533_04fe3d0d_38823d0d; +defparam bootram.RAM1.INIT_26=256'h0c718280_0682e098_0c7581ff_7182e090_82e0800c_70f13876_06515151_882a7081; +defparam bootram.RAM1.INIT_27=256'h82e08008_5170f138_81065151_70882a70_82e09008_802e9638_0c725172_0782e090; +defparam bootram.RAM1.INIT_28=256'hff873f86_80528051_88548053_0c888055_0b82e094_fc3d0d81_843d0d04_5170800c; +defparam bootram.RAM1.INIT_29=256'h840c7c88_8b0b82e0_82e0900c_0c88800b_0b82e098_fee43f80_3d0d7d56_3d0d04f6; +defparam bootram.RAM1.INIT_2A=256'h7e558054_0cfeb33f_0b82e090_900c8aa8_a80b82e0_e0980c88_0c810b82_2b82e080; +defparam bootram.RAM1.INIT_2B=256'h82e08808_e08c0858_fe983f82_82e0900c_0c8a800b_0b82e090_d3388880_73762780; +defparam bootram.RAM1.INIT_2C=256'h52717327_38705380_70732783_52579053_3d767531_80085b88_085a82e0_5982e084; +defparam bootram.RAM1.INIT_2D=256'h980c8c3d_800b82e0_54ffa939_ec397214_34811252_70810557_51703375_91387117; +defparam bootram.RAM1.INIT_2E=256'h70335154_57557417_84059d05_d23f8002_526851fe_545780c0_0d883d70_0d04ea3d; +defparam bootram.RAM1.INIT_2F=256'h85388154_2e098106_54738199_16703351_06943874_aa2e0981_9d387381_7381ff2e; +defparam bootram.RAM1.INIT_30=256'h527951fe_70545484_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527_8b398115; +defparam bootram.RAM1.INIT_31=256'h893d0d04_5574800c_06833881_752e0981_f73f8008_52735185_8453abe8_823f8055; +defparam bootram.RAM1.INIT_32=256'h72812a88_832a8406_872a0771_2a820671_05337085_3d0d0297_940c04fd_810b81e0; +defparam bootram.RAM1.INIT_33=256'h70720778_2b80c006_ff067685_07077081_a0067173_0674832b_07731090_06717307; +defparam bootram.RAM1.INIT_34=256'hd00a0681_fe3d0d74_853d0d04_52555552_52535155_c0800c51_81ff0682_872b0770; +defparam bootram.RAM1.INIT_35=256'hb251ff87_51ff8c3f_923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753; +defparam bootram.RAM1.INIT_36=256'h51fee83f_feed3fb2_81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151; +defparam bootram.RAM1.INIT_37=256'hca3f81a1_3fb051fe_5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe; +defparam bootram.RAM1.INIT_38=256'h3f8051fe_a051feab_51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f; +defparam bootram.RAM1.INIT_39=256'h8025ab38_08880508_fc050c8c_800b8c08_0cf93d0d_8c08028c_0d04ff39_a63f843d; +defparam bootram.RAM1.INIT_3A=256'h08f4050c_38810b8c_fc050888_050c8c08_0b8c08f4_88050c80_08308c08_8c088805; +defparam bootram.RAM1.INIT_3B=256'h050c800b_308c088c_088c0508_25ab388c_8c050880_050c8c08_088c08fc_8c08f405; +defparam bootram.RAM1.INIT_3C=256'h0c80538c_8c08fc05_08f00508_f0050c8c_810b8c08_05088838_0c8c08fc_8c08f005; +defparam bootram.RAM1.INIT_3D=256'h802e8c38_08fc0508_050c548c_708c08f8_a73f8008_05085181_528c0888_088c0508; +defparam bootram.RAM1.INIT_3E=256'h028c0cfb_0c048c08_893d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM1.INIT_3F=256'h0c810b8c_8c088805_88050830_93388c08_05088025_0c8c0888_8c08fc05_3d0d800b; +defparam bootram.RAM2.INIT_00=256'h8c050852_81538c08_088c050c_0508308c_388c088c_0880258c_8c088c05_08fc050c; +defparam bootram.RAM2.INIT_01=256'hf8050830_8c388c08_0508802e_548c08fc_08f8050c_8008708c_0851ad3f_8c088805; +defparam bootram.RAM2.INIT_02=256'h810b8c08_0cfd3d0d_8c08028c_0d8c0c04_0c54873d_05087080_0c8c08f8_8c08f805; +defparam bootram.RAM2.INIT_03=256'h802ea338_08fc0508_27ac388c_08880508_8c05088c_050c8c08_0b8c08f8_fc050c80; +defparam bootram.RAM2.INIT_04=256'h08fc050c_0508108c_0c8c08fc_8c088c05_8c050810_99388c08_8c050824_800b8c08; +defparam bootram.RAM2.INIT_05=256'h05088c08_388c0888_050826a1_088c0888_8c088c05_2e80c938_fc050880_c9398c08; +defparam bootram.RAM2.INIT_06=256'h0508812a_0c8c08fc_8c08f805_fc050807_05088c08_0c8c08f8_8c088805_8c050831; +defparam bootram.RAM2.INIT_07=256'h388c0888_08802e8f_8c089005_0cffaf39_8c088c05_0508812a_0c8c088c_8c08fc05; +defparam bootram.RAM2.INIT_08=256'h800c853d_08f40508_050c518c_708c08f4_08f80508_518d398c_08f4050c_0508708c; +defparam bootram.RAM2.INIT_09=256'h38ff1252_70802eb0_07830651_8c387474_52837227_77795656_fc3d0d78_0d8c0c04; +defparam bootram.RAM2.INIT_0A=256'h71ff2e09_14545555_158115ff_06bd3881_712e0981_33525372_38743374_71ff2ea0; +defparam bootram.RAM2.INIT_0B=256'h8414fc14_8f388411_2e098106_70087308_74745451_863d0d04_800b800c_8106e238; +defparam bootram.RAM2.INIT_0C=256'h70797b55_fc3d0d76_863d0d04_7131800c_ffaf3972_70735555_8326e938_54545171; +defparam bootram.RAM2.INIT_0D=256'h70810554_2e983872_125271ff_2ea738ff_06517080_72750783_72278c38_5555558f; +defparam bootram.RAM2.INIT_0E=256'h70840554_04745172_0c863d0d_ea387480_2e098106_125271ff_055634ff_33747081; +defparam bootram.RAM2.INIT_0F=256'h05530c72_08717084_70840554_05530c72_08717084_70840554_05530c72_08717084; +defparam bootram.RAM2.INIT_10=256'h54087170_72708405_72279538_26c93883_1252718f_05530cf0_08717084_70840554; +defparam bootram.RAM2.INIT_11=256'h812e9838_08545472_800bae94_39fd3d0d_7054ff83_8326ed38_fc125271_8405530c; +defparam bootram.RAM2.INIT_12=256'h823fe3a0_b5dc0ce4_519b3f72_ad3f8008_528151e6_b73faeb4_e4993fe3_73b5dc0c; +defparam bootram.RAM2.INIT_13=256'h5a545a77_82c81108_7baeb808_39f73d0d_843f00ff_3f800851_8151e696_3faeb452; +defparam bootram.RAM2.INIT_14=256'hb5387382_38807424_742480e9_59555980_0581712b_841908ff_38818818_802e80d9; +defparam bootram.RAM2.INIT_15=256'h0853722d_53795174_16700853_2eb53878_06537280_80190877_05565681_2b781188; +defparam bootram.RAM2.INIT_16=256'h53bc1308_38aeb808_5877ffad_d6387708_54738025_2c5a5757_fc177981_ff14fc17; +defparam bootram.RAM2.INIT_17=256'hffa938d2_54738025_2c5a5757_fc177981_ff14fc17_0853722d_f8c03f74_a5387951; +defparam bootram.RAM2.INIT_18=256'h08525270_0bfc0570_3d0db5bc_f8943fff_722d7951_bc130853_94397251_398057ff; +defparam bootram.RAM2.INIT_19=256'h04000000_04e3893f_833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138; +defparam bootram.RAM2.INIT_1A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040; +defparam bootram.RAM2.INIT_1B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120; +defparam bootram.RAM2.INIT_1C=256'h61205a50_756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250; +defparam bootram.RAM2.INIT_1D=256'h696e2073_50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564; +defparam bootram.RAM2.INIT_1E=256'h6f6d206d_6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520; +defparam bootram.RAM2.INIT_1F=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; +defparam bootram.RAM2.INIT_20=256'h61726520_69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065; +defparam bootram.RAM2.INIT_21=256'h6b2e2046_62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167; +defparam bootram.RAM2.INIT_22=256'h2e000000_2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20; +defparam bootram.RAM2.INIT_23=256'h6e204650_6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563; +defparam bootram.RAM2.INIT_24=256'h20465047_74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069; +defparam bootram.RAM2.INIT_25=256'h20626f6f_6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d; +defparam bootram.RAM2.INIT_26=256'h20696d61_46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000; +defparam bootram.RAM2.INIT_27=256'h2070726f_6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066; +defparam bootram.RAM2.INIT_28=256'h6f647563_64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374; +defparam bootram.RAM2.INIT_29=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; +defparam bootram.RAM2.INIT_2A=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; +defparam bootram.RAM2.INIT_2B=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; +defparam bootram.RAM2.INIT_2C=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM2.INIT_2D=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM2.INIT_2E=256'h14580a2c_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; +defparam bootram.RAM2.INIT_2F=256'h20202020_28282820_20202828_20202020_00202020_0b0b0b0b_01b200d9_05160364; +defparam bootram.RAM2.INIT_30=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; +defparam bootram.RAM2.INIT_31=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; +defparam bootram.RAM2.INIT_32=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_37=256'hffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000_792e6578_64756d6d; -defparam bootram.RAM2.INIT_38=256'h0018000f_ffff0031_05050400_01010100_00001ab4_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_39=256'h00000000_00001a4c_000019f0_00001994_00000000_0000172c_000016e0_000b0000; -defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_000016ec; +defparam bootram.RAM2.INIT_37=256'h43000000_65000000_792e6578_64756d6d_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_38=256'h00001ac4_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff; +defparam bootram.RAM2.INIT_39=256'h00000000_0000173c_000016f0_000b0000_0018000f_ffff0031_05050400_01010100; +defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00001a5c_00001a00_000019a4; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_000016fc_00000000_00000000_00000000_00000000; defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3E=256'h1234e66d_330eabcd_00000001_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_000b0000_deec0005; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001_00000000; defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; @@ -211,8 +211,8 @@ defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_ffffffff_00000000_ffffffff_00000000_00000000; -defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_ffffffff_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_ffffffff; defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v index ec54de73e..22e181caf 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -131,18 +131,22 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_MISC = 0; // Uses 9 regs - localparam SR_BUF_POOL = 64; // Uses 4 regs - localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP0 = 160; // 16 - localparam SR_RX_CTRL0 = 176; // 16 - localparam SR_TIME64 = 192; // 3 - localparam SR_SIMTIMER = 198; // 2 - localparam SR_TX_DSP = 208; // 16 - localparam SR_TX_CTRL = 224; // 16 - localparam SR_RX_DSP1 = 240; - localparam SR_RX_CTRL1 = 32; - + localparam SR_MISC = 0; // 7 regs + localparam SR_SIMTIMER = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_UDP_SM = 192; // 64 // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs @@ -203,22 +207,22 @@ module u2plus_core wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; wb_1master #(.decode_w(8), - .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM - .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool - .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI - .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C - .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO - .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback - .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC - .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) - .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC - .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused - .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART - .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR - .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused - .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP - .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash - .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // GPIO + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // ATR + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -256,55 +260,47 @@ module u2plus_core .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - ////////////////////////////////////////////////////////////////////////////////////////// + // //////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - reg cpu_bldr_ctrl_state; - localparam CPU_BLDR_CTRL_WAIT = 0; - localparam CPU_BLDR_CTRL_DONE = 1; - - wire bldr_done; - wire por_rst; - wire [aw-1:0] cpu_adr; - wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? - 16'hfff8 : //top of 8K boot ram re-purposed at 56K - 16'h1ff8 ; //top of 8K boot ram - - //When the main program runs, it will try to access system ram at 0. - //This logic re-maps the cpu address to force select the system ram. - assign m0_adr = - (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader - (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) - (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) - cpu_adr))); //otherwise - - system_control sysctrl ( - .wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) - ); - - always @(posedge wb_clk) - if(por_rst) begin + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + + // Swap boot ram and main ram when in bootloader mode + assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : + cpu_adr ^ 16'hC000; + + system_control sysctrl + (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); + + always @(posedge wb_clk) + if(por_rst) begin cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; wb_rst <= 1'b1; - end - else begin + end + else begin case(cpu_bldr_ctrl_state) - - CPU_BLDR_CTRL_WAIT: begin - wb_rst <= 1'b0; - if (bldr_done == 1'b1) begin //set by the bootloader + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; wb_rst <= 1'b1; - end - end - - CPU_BLDR_CTRL_DONE: begin //stay here forever - wb_rst <= 1'b0; - end - + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + endcase //cpu_bldr_ctrl_state - end - + end + // ///////////////////////////////////////////////////////////////////////// // Processor @@ -317,9 +313,8 @@ module u2plus_core .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); - - + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone @@ -327,8 +322,8 @@ module u2plus_core bootram bootram(.clk(wb_clk), .reset(wb_rst), .if_adr(13'b0), .if_data(), - .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + .dwb_adr_i(sf_adr[12:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); ////blinkenlights v0.1 //defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; @@ -339,8 +334,8 @@ module u2plus_core ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .if_adr(14'b0), .if_data(), - .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), - .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool, slave #1 @@ -416,7 +411,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd5; + localparam compat_num = 32'd6; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -433,7 +428,7 @@ module u2plus_core // Ethernet MAC Slave #6 simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), - .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), @@ -477,7 +472,7 @@ module u2plus_core .in(set_data),.out(adc_outs),.changed()); setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); - setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// @@ -492,7 +487,7 @@ module u2plus_core setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v index c642842f6..b4f6e55b8 100644 --- a/fpga/usrp2/udp/prot_eng_tx.v +++ b/fpga/usrp2/udp/prot_eng_tx.v @@ -1,146 +1,110 @@ -// The input FIFO contents should be 16 bits wide -// The first word is 1 for fast path (accelerated protocol) -// 0 for software implemented protocol -// The second word is the number of bytes in the packet, -// and must be valid even if we are in slow path mode -// Odd means the last word is half full -// Flags[1:0] is {eop, sop} -// Protocol word format is: -// 21 UDP Source Port Here -// 20 UDP Dest Port Here -// 19 Last Header Line -// 18 IP Header Checksum XOR -// 17 IP Length Here -// 16 UDP Length Here -// 15:0 data word to be sent - module prot_eng_tx #(parameter BASE=0) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [18:0] datain, input src_rdy_i, output dst_rdy_o, - output [18:0] dataout, output src_rdy_o, input dst_rdy_i); - - wire [2:0] flags_i = datain[18:16]; - reg [15:0] dataout_int; - reg fast_path, sof_o; - - wire [2:0] flags_o = {flags_i[2], flags_i[1], sof_o}; // OCC, EOF, SOF + input [35:0] datain, input src_rdy_i, output dst_rdy_o, + output [35:0] dataout, output src_rdy_o, input dst_rdy_i); - assign dataout = {flags_o[2:0], dataout_int[15:0]}; + wire src_rdy_int1, dst_rdy_int1; + wire src_rdy_int2, dst_rdy_int2; + wire [35:0] data_int1, data_int2; - reg [4:0] state; - wire do_payload = (state == 31); - - assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); - assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - - localparam HDR_WIDTH = 16 + 6; // 16 bits plus flags - localparam HDR_LEN = 32; // Up to 64 bytes of protocol + // Shortfifo on input to guarantee no deadlock + fifo_short #(.WIDTH(36)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), + .space(),.occupied() ); // Store header values in a small dual-port (distributed) ram - reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; - wire [HDR_WIDTH-1:0] header_word; - - reg [1:0] port_sel; - reg [31:0] per_port_data[0:3]; - reg [15:0] udp_src_port, udp_dst_port, chk_precompute; - - always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; - always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0]; - + reg [31:0] header_ram[0:63]; + reg [3:0] state; + reg [1:0] port_sel; + always @(posedge clk) - if(set_stb & ((set_addr & 8'hE0) == BASE)) - header_ram[set_addr[4:0]] <= set_data; + if(set_stb & ((set_addr & 8'hC0) == BASE)) + header_ram[set_addr[5:0]] <= set_data; - always @(posedge clk) - if(set_stb & (set_addr == (BASE + 14))) - chk_precompute <= set_data[15:0]; + wire [31:0] header_word = header_ram[{port_sel[1:0],state[3:0]}]; + reg [15:0] pre_checksums [0:3]; always @(posedge clk) - if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) - per_port_data[set_addr[1:0]] <= set_data; - - wire do_udp_src_port = header_word[21]; - wire do_udp_dst_port = header_word[20]; - wire last_hdr_line = header_word[19]; - wire do_ip_chk = header_word[18]; - wire do_ip_len = header_word[17]; - wire do_udp_len = header_word[16]; + if(set_stb & ((set_addr & 8'hCF)== (BASE+7))) + pre_checksums[set_addr[5:4]] <= set_data[15:0]; + + wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]]; - assign header_word = header_ram[state]; - // Protocol State Machine reg [15:0] length; wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR wire [15:0] udp_length = length + 8; // UDP HDR - + reg sof_o; + reg [31:0] prot_data; + always @(posedge clk) if(reset) begin - state <= 0; - fast_path <= 0; + state <= 0; sof_o <= 0; end else - if(src_rdy_i & dst_rdy_i) + if(src_rdy_int1 & dst_rdy_int2) case(state) 0 : begin - fast_path <= datain[0]; - port_sel <= datain[2:1]; - state <= 1; - end - 1 : - begin - length <= datain[15:0]; + port_sel <= data_int1[18:17]; + length <= data_int1[15:0]; sof_o <= 1; - if(fast_path) - state <= 2; + if(data_int1[16]) + state <= 1; else - state <= 30; // Skip 1 word for alignment + state <= 12; end - 30 : - state <= 31; - 31 : + 12 : begin sof_o <= 0; - if(flags_i[1]) // eop + if(data_int1[33]) // eof state <= 0; end default : begin sof_o <= 0; - if(~last_hdr_line) - state <= state + 1; - else - state <= 31; + state <= state + 1; end endcase // case (state) - wire [15:0] checksum; + wire [15:0] ip_checksum; add_onescomp #(.WIDTH(16)) add_onescomp - (.A(chk_precompute),.B(ip_length),.SUM(checksum)); - - reg [15:0] checksum_reg; - always @(posedge clk) - checksum_reg <= checksum; + (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum)); + reg [15:0] ip_checksum_reg; + always @(posedge clk) ip_checksum_reg <= ip_checksum; always @* - if(do_payload) - dataout_int <= datain[15:0]; - else if(do_ip_chk) - dataout_int <= 16'hFFFF ^ checksum_reg; - else if(do_ip_len) - dataout_int <= ip_length; - else if(do_udp_len) - dataout_int <= udp_length; - else if(do_udp_src_port) - dataout_int <= udp_src_port; - else if(do_udp_dst_port) - dataout_int <= udp_dst_port; - else - dataout_int <= header_word[15:0]; + case(state) + 1 : prot_data <= header_word; // ETH, top half ignored + 2 : prot_data <= header_word; // ETH + 3 : prot_data <= header_word; // ETH + 4 : prot_data <= header_word; // ETH + 5 : prot_data <= { header_word[31:16], ip_length }; // IP + 6 : prot_data <= header_word; // IP + 7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP + 8 : prot_data <= header_word; // IP + 9 : prot_data <= header_word; // IP + 10: prot_data <= header_word; // UDP + 11: prot_data <= { udp_length, header_word[15:0]}; // UDP + default : prot_data <= data_int1[31:0]; + endcase // case (state) + + assign data_int2 = { data_int1[35:33] & {3{state[3]}}, sof_o, prot_data }; + assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12)); + assign src_rdy_int2 = src_rdy_int1 & (state != 0); + + // Shortfifo on output to guarantee no deadlock + fifo_short #(.WIDTH(36)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(),.occupied() ); endmodule // prot_eng_tx diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v index c8fffe605..138794e57 100644 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ b/fpga/usrp2/udp/prot_eng_tx_tb.v @@ -8,40 +8,45 @@ module prot_eng_tx_tb(); always #50 clk = ~clk; reg [31:0] f36_data; - reg [1:0] f36_occ; - reg f36_sof, f36_eof; - + reg [1:0] f36_occ; + reg f36_sof, f36_eof; wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - reg [15:0] count; + reg src_rdy_f36i = 0; + wire dst_rdy_f36i; + wire [35:0] casc_do; - wire [18:0] final_out, prot_out; + wire src_rdy_f36o, dst_rdy_f36o; - wire src_rdy_final, dst_rdy_final, src_rdy_prot; - reg dst_rdy_prot =0; - - wire dst_rdy_f36o ; - fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 - (.clk(clk),.reset(rst),.clear(clear), - .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); + wire [35:0] prot_out; + wire src_rdy_prot, dst_rdy_prot; - fifo36_to_fifo19 fifo_converter - (.clk(clk),.reset(rst),.clear(clear), - .f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o), - .f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final)); + wire [35:0] realign_out; + wire src_rdy_realign; + reg dst_rdy_realign = 1; + + reg [15:0] count; reg set_stb; reg [7:0] set_addr; reg [31:0] set_data; + fifo_short #(.WIDTH(36)) fifo_cascade36 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); + prot_eng_tx #(.BASE(BASE)) prot_eng_tx - (.clk(clk), .reset(rst), + (.clk(clk), .reset(rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final), - .dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); - + .datain(casc_do),.src_rdy_i(src_rdy_f36o),.dst_rdy_o(dst_rdy_f36o), + .dataout(prot_out),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); + + ethtx_realign ethtx_realign + (.clk(clk), .reset(rst), .clear(0), + .datain(prot_out),.src_rdy_i(src_rdy_prot),.dst_rdy_o(dst_rdy_prot), + .dataout(realign_out),.src_rdy_o(src_rdy_realign),.dst_rdy_i(dst_rdy_realign)); + reg [35:0] printer; task WriteSREG; @@ -58,17 +63,22 @@ module prot_eng_tx_tb(); end endtask // WriteSREG + always @(posedge clk) + if(src_rdy_realign) + $display("Read: %h",realign_out); + + task ReadFromFIFO36; begin $display("Read from FIFO36"); - #1 dst_rdy_prot <= 1; + #1 dst_rdy_realign <= 1; while(~src_rdy_prot) @(posedge clk); while(1) begin while(~src_rdy_prot) @(posedge clk); - $display("Read: %h",prot_out); + $display("Read: %h",realign_out); @(posedge clk); end end @@ -80,7 +90,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0003_000c; + f36_data <= 32'h0001_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -132,37 +142,34 @@ module prot_eng_tx_tb(); begin #10000; @(posedge clk); - ReadFromFIFO36; + //ReadFromFIFO36; end initial begin @(negedge rst); @(posedge clk); - WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); - WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); - WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); - WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); - WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); - WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); - WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); - WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); - WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); - WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); + WriteSREG(BASE, 32'h89AB_CDEF); + WriteSREG(BASE+1, 32'h1111_2222); + WriteSREG(BASE+2, 32'h3333_4444); + WriteSREG(BASE+3, 32'h5555_6666); + WriteSREG(BASE+4, 32'h7777_8888); + WriteSREG(BASE+5, 32'h9999_aaaa); + WriteSREG(BASE+6, 32'hbbbb_cccc); + WriteSREG(BASE+7, 32'hdddd_eeee); + WriteSREG(BASE+8, 32'h0f0f_0011); + WriteSREG(BASE+9, 32'h0022_0033); + WriteSREG(BASE+10, 32'h0044_0055); + WriteSREG(BASE+11, 32'h0066_0077); + WriteSREG(BASE+12, 32'h0088_0099); @(posedge clk); - WriteSREG(BASE+24, 16'h6666); - WriteSREG(BASE+25, 16'h7777); - WriteSREG(BASE+26, 16'h8888); - WriteSREG(BASE+27, 16'h9999); - PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); #10000; @(posedge clk); - PutPacketInFIFO36(32'hE0F0A0B0,36); + //PutPacketInFIFO36(32'hE0F0A0B0,36); @(posedge clk); @(posedge clk); @(posedge clk); diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 68c49cafc..9b49610d9 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -30,8 +30,8 @@ extern "C" { #endif //fpga and firmware compatibility numbers -#define USRP2_FPGA_COMPAT_NUM 5 -#define USRP2_FW_COMPAT_NUM 9 +#define USRP2_FPGA_COMPAT_NUM 6 +#define USRP2_FW_COMPAT_NUM 10 //used to differentiate control packets over data port #define USRP2_INVALID_VRT_HEADER 0 diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp index 66c3ac137..57ae36857 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.cpp +++ b/host/lib/usrp/usrp2/usrp2_regs.cpp @@ -18,106 +18,119 @@ #include "usrp2_regs.hpp" #include "usrp2_iface.hpp" -int sr_addr(int misc_output_base, int sr) { - return misc_output_base + 4 * sr; -} +//////////////////////////////////////////////////////////////////////// +// Define slave bases +//////////////////////////////////////////////////////////////////////// +#define ROUTER_RAM_BASE 0x4000 +#define SPI_BASE 0x5000 +#define I2C_BASE 0x5400 +#define GPIO_BASE 0x5800 +#define READBACK_BASE 0x5C00 +#define ETH_BASE 0x6000 +#define SETTING_REGS_BASE 0x7000 +#define PIC_BASE 0x8000 +#define UART_BASE 0x8800 +#define ATR_BASE 0x8C00 + +//////////////////////////////////////////////////////////////////////// +// Setting register offsets +//////////////////////////////////////////////////////////////////////// +#define SR_MISC 0 // 7 regs +#define SR_SIMTIMER 8 // 2 +#define SR_TIME64 10 // 6 +#define SR_BUF_POOL 16 // 4 + +#define SR_RX_FRONT 24 // 5 +#define SR_RX_CTRL0 32 // 9 +#define SR_RX_DSP0 48 // 7 +#define SR_RX_CTRL1 80 // 9 +#define SR_RX_DSP1 96 // 7 -usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) { +#define SR_TX_FRONT 128 // ? +#define SR_TX_CTRL 144 // 6 +#define SR_TX_DSP 160 // 5 - //how about you just make this dependent on hw_rev instead of doing the init before main, and give up the const globals, since the application won't ever need both. - const int misc_output_base = (use_n2xx_map) ? USRP2P_MISC_OUTPUT_BASE : USRP2_MISC_OUTPUT_BASE, - gpio_base = (use_n2xx_map) ? USRP2P_GPIO_BASE : USRP2_GPIO_BASE, - atr_base = (use_n2xx_map) ? USRP2P_ATR_BASE : USRP2_ATR_BASE, - bp_base = (use_n2xx_map) ? USRP2P_BP_STATUS_BASE : USRP2_BP_STATUS_BASE; +#define SR_UDP_SM 192 // 64 + +int sr_addr(int sr) { + return SETTING_REGS_BASE + (4 * sr); +} +usrp2_regs_t usrp2_get_regs(bool) { usrp2_regs_t x; - x.sr_misc = 0; - x.sr_tx_prot_eng = 32; - x.sr_rx_prot_eng = 48; - x.sr_buffer_pool_ctrl = 64; - x.sr_udp_sm = 96; - x.sr_tx_dsp = 208; - x.sr_tx_ctrl = 224; - x.sr_rx_dsp0 = 160; - x.sr_rx_ctrl0 = 176; - x.sr_rx_dsp1 = 240; - x.sr_rx_ctrl1 = 32; - x.sr_time64 = 192; - x.sr_simtimer = 198; - x.sr_last = 255; - x.misc_ctrl_clock = sr_addr(misc_output_base, 0); - x.misc_ctrl_serdes = sr_addr(misc_output_base, 1); - x.misc_ctrl_adc = sr_addr(misc_output_base, 2); - x.misc_ctrl_leds = sr_addr(misc_output_base, 3); - x.misc_ctrl_phy = sr_addr(misc_output_base, 4); - x.misc_ctrl_dbg_mux = sr_addr(misc_output_base, 5); - x.misc_ctrl_ram_page = sr_addr(misc_output_base, 6); - x.misc_ctrl_flush_icache = sr_addr(misc_output_base, 7); - x.misc_ctrl_led_src = sr_addr(misc_output_base, 8); - x.time64_secs = sr_addr(misc_output_base, x.sr_time64 + 0); - x.time64_ticks = sr_addr(misc_output_base, x.sr_time64 + 1); - x.time64_flags = sr_addr(misc_output_base, x.sr_time64 + 2); - x.time64_imm = sr_addr(misc_output_base, x.sr_time64 + 3); - x.time64_tps = sr_addr(misc_output_base, x.sr_time64 + 4); - x.time64_mimo_sync = sr_addr(misc_output_base, x.sr_time64 + 5); - x.status = bp_base + 4*8; - x.time64_secs_rb_imm = bp_base + 4*10; - x.time64_ticks_rb_imm = bp_base + 4*11; - x.compat_num_rb = bp_base + 4*12; - x.time64_secs_rb_pps = bp_base + 4*14; - x.time64_ticks_rb_pps = bp_base + 4*15; - x.dsp_tx_freq = sr_addr(misc_output_base, x.sr_tx_dsp + 0); - x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1); - x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2); - x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4); - x.dsp_rx[0].freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0); - x.dsp_rx[0].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1); - x.dsp_rx[0].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2); - x.dsp_rx[0].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3); - x.dsp_rx[0].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4); - x.dsp_rx[0].mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5); - x.dsp_rx[1].freq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 0); - x.dsp_rx[1].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 1); - x.dsp_rx[1].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp1 + 2); - x.dsp_rx[1].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp1 + 3); - x.dsp_rx[1].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp1 + 4); - x.dsp_rx[1].mux = sr_addr(misc_output_base, x.sr_rx_dsp1 + 5); - x.gpio_io = gpio_base + 0; - x.gpio_ddr = gpio_base + 4; - x.gpio_tx_sel = gpio_base + 8; - x.gpio_rx_sel = gpio_base + 12; - x.atr_idle_txside = atr_base + 0; - x.atr_idle_rxside = atr_base + 2; - x.atr_intx_txside = atr_base + 4; - x.atr_intx_rxside = atr_base + 6; - x.atr_inrx_txside = atr_base + 8; - x.atr_inrx_rxside = atr_base + 10; - x.atr_full_txside = atr_base + 12; - x.atr_full_rxside = atr_base + 14; - x.rx_ctrl[0].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0); - x.rx_ctrl[0].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1); - x.rx_ctrl[0].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2); - x.rx_ctrl[0].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3); - x.rx_ctrl[0].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4); - x.rx_ctrl[0].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5); - x.rx_ctrl[0].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6); - x.rx_ctrl[0].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7); - x.rx_ctrl[0].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8); - x.rx_ctrl[1].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 0); - x.rx_ctrl[1].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 1); - x.rx_ctrl[1].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 2); - x.rx_ctrl[1].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 3); - x.rx_ctrl[1].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 4); - x.rx_ctrl[1].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 5); - x.rx_ctrl[1].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 6); - x.rx_ctrl[1].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 7); - x.rx_ctrl[1].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 8); - x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0); - x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1); - x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2); - x.tx_ctrl_policy = sr_addr(misc_output_base, x.sr_tx_ctrl + 3); - x.tx_ctrl_cycles_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 4); - x.tx_ctrl_packets_per_up = sr_addr(misc_output_base, x.sr_tx_ctrl + 5); + x.misc_ctrl_clock = sr_addr(0); + x.misc_ctrl_serdes = sr_addr(1); + x.misc_ctrl_adc = sr_addr(2); + x.misc_ctrl_leds = sr_addr(3); + x.misc_ctrl_phy = sr_addr(4); + x.misc_ctrl_dbg_mux = sr_addr(5); + x.misc_ctrl_ram_page = sr_addr(6); + x.misc_ctrl_flush_icache = sr_addr(7); + x.misc_ctrl_led_src = sr_addr(8); + x.time64_secs = sr_addr(SR_TIME64 + 0); + x.time64_ticks = sr_addr(SR_TIME64 + 1); + x.time64_flags = sr_addr(SR_TIME64 + 2); + x.time64_imm = sr_addr(SR_TIME64 + 3); + x.time64_tps = sr_addr(SR_TIME64 + 4); + x.time64_mimo_sync = sr_addr(SR_TIME64 + 5); + x.status = READBACK_BASE + 4*8; + x.time64_secs_rb_imm = READBACK_BASE + 4*10; + x.time64_ticks_rb_imm = READBACK_BASE + 4*11; + x.compat_num_rb = READBACK_BASE + 4*12; + x.time64_secs_rb_pps = READBACK_BASE + 4*14; + x.time64_ticks_rb_pps = READBACK_BASE + 4*15; + x.dsp_tx_freq = sr_addr(SR_TX_DSP + 0); + x.dsp_tx_scale_iq = sr_addr(SR_TX_DSP + 1); + x.dsp_tx_interp_rate = sr_addr(SR_TX_DSP + 2); + x.dsp_tx_mux = sr_addr(SR_TX_DSP + 4); + x.dsp_rx[0].freq = sr_addr(SR_RX_DSP0 + 0); + x.dsp_rx[0].scale_iq = sr_addr(SR_RX_DSP0 + 1); + x.dsp_rx[0].decim_rate = sr_addr(SR_RX_DSP0 + 2); + x.dsp_rx[0].dcoffset_i = sr_addr(SR_RX_DSP0 + 3); + x.dsp_rx[0].dcoffset_q = sr_addr(SR_RX_DSP0 + 4); + x.dsp_rx[0].mux = sr_addr(SR_RX_DSP0 + 5); + x.dsp_rx[1].freq = sr_addr(SR_RX_DSP1 + 0); + x.dsp_rx[1].scale_iq = sr_addr(SR_RX_DSP1 + 1); + x.dsp_rx[1].decim_rate = sr_addr(SR_RX_DSP1 + 2); + x.dsp_rx[1].dcoffset_i = sr_addr(SR_RX_DSP1 + 3); + x.dsp_rx[1].dcoffset_q = sr_addr(SR_RX_DSP1 + 4); + x.dsp_rx[1].mux = sr_addr(SR_RX_DSP1 + 5); + x.gpio_io = GPIO_BASE + 0; + x.gpio_ddr = GPIO_BASE + 4; + x.gpio_tx_sel = GPIO_BASE + 8; + x.gpio_rx_sel = GPIO_BASE + 12; + x.atr_idle_txside = ATR_BASE + 0; + x.atr_idle_rxside = ATR_BASE + 2; + x.atr_intx_txside = ATR_BASE + 4; + x.atr_intx_rxside = ATR_BASE + 6; + x.atr_inrx_txside = ATR_BASE + 8; + x.atr_inrx_rxside = ATR_BASE + 10; + x.atr_full_txside = ATR_BASE + 12; + x.atr_full_rxside = ATR_BASE + 14; + x.rx_ctrl[0].stream_cmd = sr_addr(SR_RX_CTRL0 + 0); + x.rx_ctrl[0].time_secs = sr_addr(SR_RX_CTRL0 + 1); + x.rx_ctrl[0].time_ticks = sr_addr(SR_RX_CTRL0 + 2); + x.rx_ctrl[0].clear_overrun = sr_addr(SR_RX_CTRL0 + 3); + x.rx_ctrl[0].vrt_header = sr_addr(SR_RX_CTRL0 + 4); + x.rx_ctrl[0].vrt_stream_id = sr_addr(SR_RX_CTRL0 + 5); + x.rx_ctrl[0].vrt_trailer = sr_addr(SR_RX_CTRL0 + 6); + x.rx_ctrl[0].nsamps_per_pkt = sr_addr(SR_RX_CTRL0 + 7); + x.rx_ctrl[0].nchannels = sr_addr(SR_RX_CTRL0 + 8); + x.rx_ctrl[1].stream_cmd = sr_addr(SR_RX_CTRL1 + 0); + x.rx_ctrl[1].time_secs = sr_addr(SR_RX_CTRL1 + 1); + x.rx_ctrl[1].time_ticks = sr_addr(SR_RX_CTRL1 + 2); + x.rx_ctrl[1].clear_overrun = sr_addr(SR_RX_CTRL1 + 3); + x.rx_ctrl[1].vrt_header = sr_addr(SR_RX_CTRL1 + 4); + x.rx_ctrl[1].vrt_stream_id = sr_addr(SR_RX_CTRL1 + 5); + x.rx_ctrl[1].vrt_trailer = sr_addr(SR_RX_CTRL1 + 6); + x.rx_ctrl[1].nsamps_per_pkt = sr_addr(SR_RX_CTRL1 + 7); + x.rx_ctrl[1].nchannels = sr_addr(SR_RX_CTRL1 + 8); + x.tx_ctrl_num_chan = sr_addr(SR_TX_CTRL + 0); + x.tx_ctrl_clear_state = sr_addr(SR_TX_CTRL + 1); + x.tx_ctrl_report_sid = sr_addr(SR_TX_CTRL + 2); + x.tx_ctrl_policy = sr_addr(SR_TX_CTRL + 3); + x.tx_ctrl_cycles_per_up = sr_addr(SR_TX_CTRL + 4); + x.tx_ctrl_packets_per_up = sr_addr(SR_TX_CTRL + 5); return x; } diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 01f5ee65a..e7803d9ee 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -18,33 +18,7 @@ #ifndef INCLUDED_USRP2_REGS_HPP #define INCLUDED_USRP2_REGS_HPP -#include <boost/cstdint.hpp> - -#define USRP2_MISC_OUTPUT_BASE 0xD400 -#define USRP2_GPIO_BASE 0xC800 -#define USRP2_ATR_BASE 0xE400 -#define USRP2_BP_STATUS_BASE 0xCC00 - -#define USRP2P_MISC_OUTPUT_BASE 0x5000 -#define USRP2P_GPIO_BASE 0x6200 -#define USRP2P_ATR_BASE 0x6800 -#define USRP2P_BP_STATUS_BASE 0x6300 - typedef struct { - int sr_misc; - int sr_tx_prot_eng; - int sr_rx_prot_eng; - int sr_buffer_pool_ctrl; - int sr_udp_sm; - int sr_tx_dsp; - int sr_tx_ctrl; - int sr_rx_dsp0; - int sr_rx_ctrl0; - int sr_rx_dsp1; - int sr_rx_ctrl1; - int sr_time64; - int sr_simtimer; - int sr_last; int misc_ctrl_clock; int misc_ctrl_serdes; int misc_ctrl_adc; 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