diff options
| -rw-r--r-- | usrp2/gpif/gpif.v | 19 | ||||
| -rw-r--r-- | usrp2/gpif/gpif_rd.v | 2 | ||||
| -rw-r--r-- | usrp2/gpif/packet_splitter.v | 7 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus.v | 8 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 4 |
5 files changed, 24 insertions, 16 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index d003c6b1c..3649654ed 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -38,7 +38,7 @@ module gpif wire [15:0] gpif_d_copy = gpif_d; - wire [31:0] debug_rd, debug_wr; + wire [31:0] debug_rd, debug_wr, debug_split0, debug_split1; // //////////////////////////////////////////////////////////////////// // TX Data Path @@ -105,7 +105,8 @@ module gpif (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .frames_per_packet(frames_per_packet), .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), - .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy)); + .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy), + .debug0(debug_split0), .debug1(debug_split1)); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -226,12 +227,14 @@ module gpif // //////////////////////////////////////////// // DEBUG - assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], - gpif_d_copy[15:0] }; + //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + // gpif_d_copy[15:0] }; - assign debug1 = { { debug_rd[15:8] }, - { debug_rd[7:0] }, - { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, - { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + //assign debug1 = { { debug_rd[15:8] }, + // { debug_rd[7:0] }, + // { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + // { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] }; + assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] }; endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index 728b8be78..1639f0132 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -89,6 +89,6 @@ module gpif_rd assign debug = { { 16'd0 }, { data_int[17:16], data_o[17:16], packet_count[3:0] }, - { 2'b0,final_rdy_data, final_rdy_resp, consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; + { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; endmodule // gpif_rd diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v index 1c289c2fa..a55f4cb4f 100644 --- a/usrp2/gpif/packet_splitter.v +++ b/usrp2/gpif/packet_splitter.v @@ -10,7 +10,9 @@ module packet_splitter output dst_rdy_o, output [18:0] data_o, output src_rdy_o, - input dst_rdy_i); + input dst_rdy_i, + output [31:0] debug0, + output [31:0] debug1); reg [1:0] state; reg [15:0] length; @@ -98,4 +100,7 @@ module packet_splitter wire [15:0] data_out = data_i[15:0]; assign data_o = {occ_out, eof_out, sof_out, data_out}; + assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] }; + assign debug1 = { length[15:0], frame_len[15:0] }; + endmodule // packet_splitter diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v index 7e1bd2ea7..9aafef3ce 100644 --- a/usrp2/top/u1plus/u1plus.v +++ b/usrp2/top/u1plus/u1plus.v @@ -126,13 +126,13 @@ module u1plus always @(posedge clk_fpga) if(rxsync_0) begin - rx_i <= rx_a; - rx_q <= rx_b; + rx_i <= rx_b; + rx_q <= rx_a; end else begin - rx_i <= rx_b; - rx_q <= rx_a; + rx_i <= rx_a; + rx_q <= rx_b; end // ///////////////////////////////////////////////////////////////////////// diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 26565afa6..898f5950c 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -329,7 +329,7 @@ module u1plus_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( /*{io_tx,io_rx}*/ ) ); + .gpio( {io_tx,io_rx} ) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #8 + 9 @@ -387,6 +387,6 @@ module u1plus_core assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - assign {io_tx,io_rx} = vr_debug; + //assign {io_tx,io_rx} = {debug1}; endmodule // u1plus_core |