diff options
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 2 | ||||
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 26 |
2 files changed, 8 insertions, 20 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index eb07ed42f..84b5e21f9 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -152,7 +152,7 @@ module u2_core // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 9; + localparam DSP_RX_FIFOSIZE = 10; localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 2f9869930..312955945 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -147,7 +147,7 @@ module u2plus_core // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo - localparam DSP_RX_FIFOSIZE = 9; + localparam DSP_RX_FIFOSIZE = 10; localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; @@ -574,8 +574,7 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; - wire [35:0] rx0_data; - wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy; + wire clear_rx0, strobe_rx0; always @(posedge dsp_clk) run_rx0_d1 <= run_rx0; @@ -592,24 +591,18 @@ module u2plus_core .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(),.changed(clear_rx0)); - vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0 + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0 (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), - .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), - .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy), - .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - // ///////////////////////////////////////////////////////////////////////// // DSP RX 1 wire [31:0] sample_rx1; - wire [35:0] rx1_data; - wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy; + wire clear_rx1, strobe_rx1; always @(posedge dsp_clk) run_rx1_d1 <= run_rx1; @@ -626,19 +619,14 @@ module u2plus_core .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), .out(),.changed(clear_rx1)); - vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1 + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(1),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1 (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), - .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1 - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), - .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o)); - // /////////////////////////////////////////////////////////////////////////////////// // DSP TX |