diff options
| -rw-r--r-- | usrp2/control_lib/fifo_to_wb.v | 22 | ||||
| -rw-r--r-- | usrp2/gpif/gpif.v | 30 | ||||
| -rw-r--r-- | usrp2/gpif/gpif_rd.v | 14 | ||||
| -rw-r--r-- | usrp2/gpif/gpif_wr.v | 20 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 19 |
5 files changed, 53 insertions, 52 deletions
diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v index fc0f29f2d..b2a2fd18b 100644 --- a/usrp2/control_lib/fifo_to_wb.v +++ b/usrp2/control_lib/fifo_to_wb.v @@ -2,23 +2,23 @@ module fifo_to_wb #(parameter PKT_LEN = 16) (input clk, input reset, input clear, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - output [17:0] data_o, output src_rdy_o, input dst_rdy_i, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, input [7:0] triggers, output [31:0] debug0, output [31:0] debug1); - wire [17:0] ctrl_data; - reg [17:0] resp_data; + wire [18:0] ctrl_data; + reg [18:0] resp_data; wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; - fifo_short #(.WIDTH(18)) ctrl_sfifo + fifo_short #(.WIDTH(19)) ctrl_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); - fifo_short #(.WIDTH(18)) resp_sfifo + fifo_short #(.WIDTH(19)) resp_sfifo (.clk(clk), .reset(reset), .clear(clear), .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); @@ -133,11 +133,11 @@ module fifo_to_wb always @* case(resp_state) - RESP_RCMD : resp_data <= { 2'b01, 8'hAA, seqnum }; - RESP_RLEN : resp_data <= { 2'b00, length }; - RESP_RADDR_LSW : resp_data <= { 2'b00, base_addr }; - RESP_RADDR_MSW : resp_data <= { 2'b00, 16'd0 }; - default : resp_data <= { (count==1), 1'b0, wb_dat_miso }; + RESP_RCMD : resp_data <= { 3'b001, 8'hAA, seqnum }; + RESP_RLEN : resp_data <= { 3'b000, length }; + RESP_RADDR_LSW : resp_data <= { 3'b000, base_addr }; + RESP_RADDR_MSW : resp_data <= { 3'b000, 16'd0 }; + default : resp_data <= { 1'b0, (count==1), 1'b0, wb_dat_miso }; endcase // case (resp_state) assign ctrl_dst_rdy = (resp_state == RESP_IDLE) | diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index d53487535..14ed2690f 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -40,12 +40,12 @@ module gpif // //////////////////////////////////////////////////////////////////// // TX Side - wire [17:0] tx18_data; - wire tx18_src_rdy, tx18_dst_rdy; + wire [18:0] tx19_data; + wire tx19_src_rdy, tx19_dst_rdy; wire [35:0] tx36_data; wire tx36_src_rdy, tx36_dst_rdy; - wire [17:0] ctrl_data; + wire [18:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; gpif_wr gpif_wr @@ -54,13 +54,13 @@ module gpif .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), .debug(debug_wr) ); - fifo19_to_fifo36 #(.LE(1)) f18_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy), + .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 @@ -73,9 +73,9 @@ module gpif wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; - wire [17:0] rx18_data; - wire rx18_src_rdy, rx18_dst_rdy; - wire [17:0] resp_data, resp_int; + wire [18:0] rx19_data; + wire rx19_src_rdy, rx19_dst_rdy; + wire [18:0] resp_data, resp_int; wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 @@ -83,10 +83,10 @@ module gpif .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 #(.LE(1)) f36_to_f18 // FIXME Endianness? + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f19_dataout(rx18_data), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); gpif_rd gpif_rd (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -94,7 +94,7 @@ module gpif .gpif_empty_d(DE), .gpif_empty_c(CE), .sys_clk(fifo_clk), .sys_rst(fifo_rst), - .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), .debug(debug_rd) ); @@ -111,7 +111,7 @@ module gpif .debug0(), .debug1()); fifo19_pad #(.LENGTH(16)) fifo19_pad - (.clk(fifo_clk), .reset(fifo_rst), .clear(clear), + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); @@ -126,7 +126,7 @@ module gpif assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, - { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, resp_src_rdy, resp_dst_rdy}, - { tx_src_rdy_o, tx_dst_rdy_i, tx18_src_rdy, tx18_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; endmodule // gpif diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v index c6e503fce..76db72d8a 100644 --- a/usrp2/gpif/gpif_rd.v +++ b/usrp2/gpif/gpif_rd.v @@ -5,12 +5,12 @@ module gpif_rd output reg gpif_empty_d, output reg gpif_empty_c, input sys_clk, input sys_rst, - input [17:0] data_i, input src_rdy_i, output dst_rdy_o, - input [17:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, output [31:0] debug ); - wire [17:0] data_o, resp_o; + wire [18:0] data_o, resp_o; wire final_rdy_data, final_rdy_resp; // 33/257 Bug Fix @@ -24,9 +24,9 @@ module gpif_rd read_count <= 0; // Data Path - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk (.wclk(sys_clk), .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(sys_rst)); @@ -34,7 +34,7 @@ module gpif_rd // FIXME -- handle short packets wire send_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; - fifo_cascade #(.WIDTH(18), .SIZE(9)) rd_fifo + fifo_cascade #(.WIDTH(19), .SIZE(9)) rd_fifo (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(send_data_line), .occupied()); @@ -63,7 +63,7 @@ module gpif_rd wire [15:0] resp_fifolevel; wire send_resp_line = gpif_rd & gpif_ep & ~read_count[4]; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) resp_fifo_2clk (.wclk(sys_clk), .datain(resp_i), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), .rclk(~gpif_clk), .dataout(resp_o), .src_rdy_o(final_rdy_resp), .dst_rdy_i(send_resp_line), .occupied(resp_fifolevel), diff --git a/usrp2/gpif/gpif_wr.v b/usrp2/gpif/gpif_wr.v index 813e27290..e9b3c72ea 100644 --- a/usrp2/gpif/gpif_wr.v +++ b/usrp2/gpif/gpif_wr.v @@ -5,8 +5,8 @@ module gpif_wr output reg gpif_full_d, output reg gpif_full_c, input sys_clk, input sys_rst, - output [17:0] data_o, output src_rdy_o, input dst_rdy_i, - output [17:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, output [31:0] debug ); reg wr_reg, ep_reg; @@ -44,17 +44,17 @@ module gpif_wr else gpif_full_d <= fifo_space < 256; - wire [17:0] data_int; + wire [18:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_cascade #(.WIDTH(18), .SIZE(9)) wr_fifo + fifo_cascade #(.WIDTH(19), .SIZE(9)) wr_fifo (.clk(gpif_clk), .reset(gpif_rst), .clear(0), - .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .datain({1'b0,eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) wr_fifo_2clk (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), - .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .rclk(sys_clk), .dataout(data_o[18:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(sys_rst)); // Control Path @@ -65,10 +65,10 @@ module gpif_wr else gpif_full_c <= ctrl_fifo_space < 16; - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) ctrl_fifo_2clk - (.wclk(gpif_clk), .datain({eop_ctrl,sop,gpif_data_reg}), + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk + (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), - .rclk(sys_clk), .dataout(ctrl_o[17:0]), + .rclk(sys_clk), .dataout(ctrl_o[18:0]), .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), .arst(sys_rst)); diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 6a479cc83..0fbc2f593 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -10,7 +10,7 @@ module u1plus_core input [2:0] gpif_misc, input gpif_clk, inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, + output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, inout [15:0] io_tx, inout [15:0] io_rx, @@ -54,7 +54,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; - localparam aw = 11; + localparam aw = 16; localparam sw = 2; wire [dw-1:0] m0_dat_mosi, m0_dat_miso; @@ -108,7 +108,7 @@ module u1plus_core wire [31:0] sample_rx, sample_tx; wire strobe_rx, strobe_tx; wire rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx1_data; + wire [100:0] rx1_data; wire run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; @@ -123,7 +123,7 @@ module u1plus_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(rx_overrun_dsp), + .vita_time(vita_time), .overrun(), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -158,8 +158,8 @@ module u1plus_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(tx_underrun_dsp), .run(run_tx), - .debug(debug_vt)); + .underrun(), .run(run_tx), + .debug()); assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -337,7 +337,7 @@ module u1plus_core // only have 64 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); @@ -346,7 +346,7 @@ module u1plus_core atr_controller16 atr_controller16 (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); @@ -378,7 +378,8 @@ module u1plus_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry |