diff options
20 files changed, 348 insertions, 100 deletions
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v index 2f530109f..ae2edddc7 100644 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v @@ -36,42 +36,49 @@ module fifo19_to_fifo36 if(f19_src_rdy_i & ((state != 2)|xfer_out)) f36_eof <= f19_eof; - always @(posedge clk) // FIXME check this - if(f19_eof) - f36_occ <= {state[0],f19_occ}; - else - f36_occ <= 0; - always @(posedge clk) if(reset) - state <= 0; + begin + state <= 0; + f36_occ <= 0; + end else if(f19_src_rdy_i) case(state) 0 : - if(f19_eof) - state <= 2; - else - state <= 1; + begin + dat0 <= f19_datain; + if(f19_eof) + begin + state <= 2; + f36_occ <= f19_occ ? 2'b01 : 2'b10; + end + else + state <= 1; + end 1 : - state <= 2; + begin + dat1 <= f19_datain; + state <= 2; + if(f19_eof) + f36_occ <= f19_occ ? 2'b11 : 2'b00; + end 2 : if(xfer_out) - if(~f19_eof) - state <= 1; - // remain in state 2 if we are at eof + begin + dat0 <= f19_datain; + if(f19_eof) // remain in state 2 if we are at eof + f36_occ <= f19_occ ? 2'b01 : 2'b10; + else + state <= 1; + end endcase // case(state) else if(xfer_out) - state <= 0; - - always @(posedge clk) - if(f19_src_rdy_i & (state==1)) - dat1 <= f19_datain; - - always @(posedge clk) - if(f19_src_rdy_i & ((state==0) | xfer_out)) - dat0 <= f19_datain; + begin + state <= 0; + f36_occ <= 0; + end assign f19_dst_rdy_o = xfer_out | (state != 2); assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v index 517a2a476..e016fe2c6 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v @@ -16,7 +16,7 @@ module fifo36_to_fifo19 wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; + wire [1:0] f36_occ = f36_datain[35:34]; reg phase; diff --git a/fpga/usrp2/fifo/fifo_19to36_tb.v b/fpga/usrp2/fifo/fifo_19to36_tb.v new file mode 100644 index 000000000..c585392c3 --- /dev/null +++ b/fpga/usrp2/fifo/fifo_19to36_tb.v @@ -0,0 +1,82 @@ +module fifo_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [18:0] f19a; + wire [18:0] f19b, f19c, f19d; + wire [35:0] f36a, f36b; + + reg f19a_sr = 0; + wire f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr; + wire f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr; + + fifo_short #(.WIDTH(19)) fifo_short1 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr), + .dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk),.reset(rst),.clear(clear), + .f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr), + .f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) ); + + fifo_short #(.WIDTH(36)) fifo_short2 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr), + .dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) ); + + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr), + .f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) ); + + fifo_short #(.WIDTH(19)) fifo_short3 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr), + .dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) ); + + assign f19d_dr = 1; + + always @(posedge clk) + if(f19a_sr & f19a_dr) + $display("18IN: %h", f19a); + + always @(posedge clk) + if(f19d_sr & f19d_dr) + $display(" 18OUT: %h", f19d); + + always @(posedge clk) + if(f36b_sr & f36b_dr) + $display(" 36: %h", f36b); + + initial $dumpfile("fifo_tb.vcd"); + initial $dumpvars(0,fifo_tb); + + initial + begin + @(negedge rst); + @(posedge clk); + repeat (2) + begin + f19a <= 19'h1_AA01; + f19a_sr <= 1; + @(posedge clk); + f19a <= 19'h0_AA02; + repeat (4) + begin + @(posedge clk); + f19a <= f19a + 1; + end + f19a[18:16] <= 3'b010; + @(posedge clk); + f19a_sr <= 0; + f19a <= 19'h7_FFFF; + @(posedge clk); + end + #20000 $finish; + end +endmodule // longfifo_tb diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index d0c576ee5..6b2ac4e64 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -65,8 +65,6 @@ ENDIF(NOT CMAKE_BUILD_TYPE) IF(CMAKE_COMPILER_IS_GNUCXX) ADD_DEFINITIONS(-Wall) ADD_DEFINITIONS(-Wextra) - #causes trouble when compiling libusb1.0 on macintosh - #comment out until mac ports libusb gets its act together #ADD_DEFINITIONS(-pedantic) #ADD_DEFINITIONS(-ansi) #only export symbols that are declared to be part of the uhd api: @@ -79,7 +77,6 @@ IF(MSVC) ADD_DEFINITIONS(-DNOMINMAX) #disables stupidity and enables std::min and std::max ADD_DEFINITIONS(-D_SCL_SECURE_NO_WARNINGS) #avoid warnings from boost::split ADD_DEFINITIONS(-DBOOST_ALL_DYN_LINK) #setup boost auto-linking in msvc - ADD_DEFINITIONS(/arch:SSE2 /G7) #processor optimization flags ENDIF(MSVC) ######################################################################## @@ -186,6 +183,8 @@ IF(ENABLE_UTILS) ADD_SUBDIRECTORY(utils) ENDIF(ENABLE_UTILS) +ADD_SUBDIRECTORY(usrp_e_utils) + ######################################################################## # Print Summary ######################################################################## diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt index ace48f008..0c2cadfc2 100644 --- a/host/docs/CMakeLists.txt +++ b/host/docs/CMakeLists.txt @@ -29,7 +29,6 @@ SET(manual_sources transport.rst usrp1.rst usrp2.rst - usrp_nxxx.rst ) ######################################################################## diff --git a/host/docs/build.rst b/host/docs/build.rst index 74ebc9ee4..de7c544f2 100644 --- a/host/docs/build.rst +++ b/host/docs/build.rst @@ -30,10 +30,13 @@ On windows, install cygwin with git support to checkout the repository, or install msysgit from http://code.google.com/p/msysgit/downloads/list ^^^^^^^^^^^^^^^^ -C++ +C++ compiler ^^^^^^^^^^^^^^^^ -On Unix, this is GCC 4.0 and above. On Windows, this is MSVC 2008. -Other compilers have not been tested yet or confirmed working. +The following compilers are known to work: + +* GCC +* Clang +* MSVC ^^^^^^^^^^^^^^^^ CMake @@ -78,6 +81,10 @@ Cheetah * **Download URL:** http://www.cheetahtemplate.org/download.html * **Download URL (windows installer):** http://feisley.com/python/cheetah/ +**Alternative method:** +Install setuptools, and use the easy_install command to install Cheetah. +http://pypi.python.org/pypi/setuptools + ^^^^^^^^^^^^^^^^ Doxygen ^^^^^^^^^^^^^^^^ diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst index 3031a0075..2ee49646f 100644 --- a/host/docs/usrp2.rst +++ b/host/docs/usrp2.rst @@ -50,6 +50,8 @@ Load the images onto the on-board flash (USRP-N Series only) ------------------------------------------------------------------------ The USRP-N Series can be reprogrammed over the network to update or change the firmware and FPGA images. +When updating images, always burn both the FPGA and firmware images before power cycling. +This ensures that when the device reboots, it has a compatible set of images to boot into. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Use the net burner tool (unix) @@ -75,8 +77,11 @@ Its possible to put the device into an unusable state by loading bad images. Fortunately, the USRP-N Series can be booted into a safe (read-only) image. Once booted into the safe image, the user can once again load images onto the device. -To boot into the safe image, hold down the reset button while power-cycling the device. -The reset button is a pushbutton switch (S2) located inside the enclosure. +The safe-mode button is a pushbutton switch (S2) located inside the enclosure. +To boot into the safe image, hold-down the safe-mode button while power-cycling the device. +Continue to hold-down the button until the front-panel LEDs blink and remain solid. + +When in safe-mode, the USRP-N Series will always have the IP address 192.168.10.2 ------------------------------------------------------------------------ Setup networking @@ -163,13 +168,15 @@ The USRP2 will reply to icmp echo requests. ping 192.168.10.2 -**Monitor the USRP2:** -You can read the serial port on the rear of the USRP2 -to get debug verbose from the embedded microcontroller. +**Monitor the serial output:** +Read the serial port to get debug verbose from the embedded microcontroller. Use a standard USB to 3.3v-level serial converter at 230400 baud. The microcontroller prints useful information about IP addresses, MAC addresses, control packets, and fast-path settings. +* **USRP2:** Serial port located on the rear edge +* **N210:** Serial port located on the left side + **Monitor the host network traffic:** Use wireshark to monitor packets sent to and received from the USRP2. diff --git a/host/docs/usrp_nxxx.rst b/host/docs/usrp_nxxx.rst deleted file mode 100644 index 733078915..000000000 --- a/host/docs/usrp_nxxx.rst +++ /dev/null @@ -1,5 +0,0 @@ -======================================================================== -UHD - USRP-N Series Application Notes -======================================================================== - -* `USRP2 and N Series Application Notes <./usrp2.html>`_ diff --git a/host/lib/transport/libusb1_zero_copy.cpp b/host/lib/transport/libusb1_zero_copy.cpp index adc590284..311a8953b 100644 --- a/host/lib/transport/libusb1_zero_copy.cpp +++ b/host/lib/transport/libusb1_zero_copy.cpp @@ -271,6 +271,7 @@ void usb_endpoint::print_transfer_status(libusb_transfer *lut){ } libusb_transfer *usb_endpoint::get_lut_with_wait(double timeout){ + boost::this_thread::disable_interruption di; //disable because the wait can throw libusb_transfer *lut; if (_completed_list->pop_with_timed_wait(lut, timeout)) return lut; return NULL; diff --git a/host/lib/usrp/usrp1/soft_time_ctrl.cpp b/host/lib/usrp/usrp1/soft_time_ctrl.cpp index 4d6abe218..856faf89d 100644 --- a/host/lib/usrp/usrp1/soft_time_ctrl.cpp +++ b/host/lib/usrp/usrp1/soft_time_ctrl.cpp @@ -20,14 +20,12 @@ #include <boost/any.hpp> #include <boost/thread.hpp> #include <boost/date_time/posix_time/posix_time.hpp> -#include <boost/date_time/local_time/local_time.hpp> #include <iostream> using namespace uhd; using namespace uhd::usrp; using namespace uhd::transport; namespace pt = boost::posix_time; -namespace lt = boost::local_time; static const time_spec_t TWIDDLE(0.0015); diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp index a57fe5171..7dc3a4ba8 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -17,7 +17,6 @@ // Slave pointers #define UE_REG_SLAVE(n) ((n)<<7) -#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) ///////////////////////////////////////////////////// // Slave 0 -- Misc Regs @@ -89,16 +88,6 @@ #define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric #define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric - -//////////////////////////////////////////////////// -// Slave 5 -- Settings Bus -// -// Output-only, no readback, 32 registers total -// Each register must be written 32 bits at a time -// First the address xxx_xx00 and then xxx_xx10 - -#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) - /////////////////////////////////////////////////// // Slave 6 -- ATR Controller // 16 regs @@ -123,48 +112,64 @@ #define UE_REG_RB_TIME_NOW_TICKS UE_REG_RB_MUX_32_BASE + 4 #define UE_REG_RB_TIME_PPS_SECS UE_REG_RB_MUX_32_BASE + 8 #define UE_REG_RB_TIME_PPS_TICKS UE_REG_RB_MUX_32_BASE + 12 +#define UE_REG_RB_MISC_TEST32 UE_REG_RB_MUX_32_BASE + 16 + +//////////////////////////////////////////////////// +// Slave 8 -- Settings Bus +// +// Output-only, no readback, 64 registers total +// Each register must be written 64 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE_ADDR(n) (UE_REG_SLAVE(8) + (4*(n))) + +#define UE_REG_SR_MISC_TEST32 UE_REG_SETTINGS_BASE_ADDR(52) ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// -#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) -#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} -#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate -#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) +#define UE_REG_DSP_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(16) + (4*(n))) +#define UE_REG_DSP_RX_FREQ UE_REG_DSP_RX_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_DSP_RX_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_DSP_RX_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_DSP_RX_ADDR(5) /////////////////////////////////////////////////// // VITA RX CTRL regs /////////////////////////////////////////////////// +#define UE_REG_CTRL_RX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(0) + (4*(n))) // The following 3 are logically a single command register. // They are clocked into the underlying fifo when time_ticks is written. -#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) -#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) -#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun -#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter -#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. -#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) -#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) -#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_CTRL_RX_ADDR(1) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_CTRL_RX_ADDR(2) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_CTRL_RX_ADDR(3) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_CTRL_RX_ADDR(4) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_CTRL_RX_ADDR(5) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_CTRL_RX_ADDR(6) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_CTRL_RX_ADDR(7) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// -#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) -#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} -#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) -#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) -#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) +#define UE_REG_DSP_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(32) + (4*(n))) +#define UE_REG_DSP_TX_FREQ UE_REG_DSP_TX_ADDR(0) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_DSP_TX_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_DSP_TX_ADDR(2) +#define UE_REG_DSP_TX_UNUSED UE_REG_DSP_TX_ADDR(3) +#define UE_REG_DSP_TX_MUX UE_REG_DSP_TX_ADDR(4) ///////////////////////////////////////////////// // VITA TX CTRL regs //////////////////////////////////////////////// -#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) -#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) -#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) +#define UE_REG_CTRL_TX_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(24) + (4*(n))) +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_CTRL_TX_ADDR(0) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_CTRL_TX_ADDR(1) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_CTRL_TX_ADDR(2) +#define UE_REG_CTRL_TX_POLICY UE_REG_CTRL_TX_ADDR(3) #define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) #define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) @@ -189,11 +194,12 @@ * * </pre> */ -#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS -#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS -#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above -#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) +#define UE_REG_TIME64_ADDR(n) (UE_REG_SETTINGS_BASE_ADDR(40) + (4*(n))) +#define UE_REG_TIME64_SECS UE_REG_TIME64_ADDR(0) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_TIME64_ADDR(1) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_TIME64_ADDR(2) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_TIME64_ADDR(3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_TIME64_ADDR(4) // clock ticks per second (counter rollover) //pps flags (see above) #define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) diff --git a/host/usrp_e_utils/CMakeLists.txt b/host/usrp_e_utils/CMakeLists.txt new file mode 100644 index 000000000..96842a684 --- /dev/null +++ b/host/usrp_e_utils/CMakeLists.txt @@ -0,0 +1,51 @@ +# +# Copyright 2011 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +######################################################################## +# USRP embedded utilities that get installed into the share path +######################################################################## +IF(CMAKE_SYSTEM_NAME STREQUAL "Linux") + SET(LINUX_TARGET TRUE) +ENDIF(CMAKE_SYSTEM_NAME STREQUAL "Linux") + +LIBUHD_REGISTER_COMPONENT("USRP-E Utils" ENABLE_USRP_E_UTILS OFF "LINUX_TARGET" OFF) + +IF(ENABLE_USRP_E_UTILS) + ENABLE_LANGUAGE(C) + INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100) + INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include) + INCLUDE_DIRECTORIES(${CMAKE_BINARY_DIR}/lib/ic_reg_maps) + + SET(usrp_e_utils_sources + fpga-downloader.cpp + clkgen-config.cpp + usrp-e-loopback.c + usrp-e-wb-test.cpp + usrp-e-debug-pins.c + usrp-e-i2c.c + usrp-e-spi.c + ) + + #for each source: build an executable and install + FOREACH(util_source ${usrp_e_utils_sources}) + GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE) + ADD_EXECUTABLE(${util_name} ${util_source}) + TARGET_LINK_LIBRARIES(${util_name} -lpthread) + INSTALL(TARGETS ${util_name} RUNTIME DESTINATION ${PKG_DATA_DIR}/usrp_e_utils) + ENDFOREACH(util_source) + +ENDIF(ENABLE_USRP_E_UTILS) diff --git a/host/utils/clkgen-config.cpp b/host/usrp_e_utils/clkgen-config.cpp index 8d29efff1..8d29efff1 100644 --- a/host/utils/clkgen-config.cpp +++ b/host/usrp_e_utils/clkgen-config.cpp diff --git a/host/utils/fpga-downloader.cpp b/host/usrp_e_utils/fpga-downloader.cpp index 80ee71600..80ee71600 100644 --- a/host/utils/fpga-downloader.cpp +++ b/host/usrp_e_utils/fpga-downloader.cpp diff --git a/host/utils/usrp-e-debug-pins.c b/host/usrp_e_utils/usrp-e-debug-pins.c index 94f898b67..94f898b67 100644 --- a/host/utils/usrp-e-debug-pins.c +++ b/host/usrp_e_utils/usrp-e-debug-pins.c diff --git a/host/utils/usrp-e-i2c.c b/host/usrp_e_utils/usrp-e-i2c.c index c6fd4c632..c6fd4c632 100644 --- a/host/utils/usrp-e-i2c.c +++ b/host/usrp_e_utils/usrp-e-i2c.c diff --git a/host/utils/usrp-e-loopback.c b/host/usrp_e_utils/usrp-e-loopback.c index 454d81ba7..454d81ba7 100644 --- a/host/utils/usrp-e-loopback.c +++ b/host/usrp_e_utils/usrp-e-loopback.c diff --git a/host/utils/usrp-e-spi.c b/host/usrp_e_utils/usrp-e-spi.c index 5203f56a8..5203f56a8 100644 --- a/host/utils/usrp-e-spi.c +++ b/host/usrp_e_utils/usrp-e-spi.c diff --git a/host/usrp_e_utils/usrp-e-wb-test.cpp b/host/usrp_e_utils/usrp-e-wb-test.cpp new file mode 100644 index 000000000..871cc46cc --- /dev/null +++ b/host/usrp_e_utils/usrp-e-wb-test.cpp @@ -0,0 +1,111 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <cstdlib> +#include <cstdio> +#include <ctime> +#include <iostream> + +#include <sys/ioctl.h> //ioctl +#include <fcntl.h> //open, close + +#include <linux/usrp_e.h> +#include "usrp_e100_regs.hpp" + +static const size_t num_test_iters = 432; + +static int fp; + +static int peek16(int reg){ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + return d.buf[0]; +} + +static void poke16(int reg, int val){ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); +} + +static int peek32(int reg){ + int ret; + struct usrp_e_ctl32 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL32, &d); + return d.buf[0]; +} + +static void poke32(int reg, int val){ + int ret; + struct usrp_e_ctl32 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL32, &d); +} + +int main(int, char *[]){ + + srandom(time(NULL)); //seed random() + + if ((fp = ::open("/dev/usrp_e0", O_RDWR)) < 0){ + std::cerr << "Open failed" << std::endl; + return -1; + } + + size_t num_pass = 0, num_fail = 0; + for (size_t i = 0; i < num_test_iters; i++){ + //make random values + int random_test32 = ::random(); + int random_test16 = ::random() & 0xffff; + int random_secs = ::random(); + + //set a bunch of registers + poke16(UE_REG_MISC_TEST, random_test16); + poke32(UE_REG_SR_MISC_TEST32, random_test32); + poke32(UE_REG_TIME64_TICKS, 0); + poke32(UE_REG_TIME64_IMM, 1); //immediate + poke32(UE_REG_TIME64_SECS, random_secs); + + //read a bunch of registers + if ( + (peek16(UE_REG_MISC_TEST) == random_test16) and + (peek32(UE_REG_RB_MISC_TEST32) == random_test32) and + (peek32(UE_REG_RB_TIME_NOW_SECS) == random_secs) and + (peek32(UE_REG_RB_TIME_NOW_TICKS) < 1000000) and + true) num_pass++; + else num_fail++; + } + + std::cout << "num pass: " << num_pass << std::endl; + std::cout << "num fail: " << num_fail << std::endl; + + ::close(fp); + return 0; +} diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index 8f6451c4f..53527c03d 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright 2010 Ettus Research LLC +# Copyright 2010-2011 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -45,21 +45,6 @@ IF(ENABLE_USRP1) ) ENDIF(ENABLE_USRP1) -IF(ENABLE_USRP_E100) - ENABLE_LANGUAGE(C) - INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100) - INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include) - INCLUDE_DIRECTORIES(${CMAKE_BINARY_DIR}/lib/ic_reg_maps) - LIST(APPEND util_share_sources - fpga-downloader.cpp - clkgen-config.cpp - usrp-e-loopback.c - usrp-e-debug-pins.c - usrp-e-i2c.c - usrp-e-spi.c - ) -ENDIF(ENABLE_USRP_E100) - #for each source: build an executable and install FOREACH(util_source ${util_share_sources}) GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE) |