diff options
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx.v | 43 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_dcoffset.v | 2 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_frontend.v | 75 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 15 |
4 files changed, 91 insertions, 44 deletions
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 0e69e53f7..9aee52131 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -21,8 +21,8 @@ module dsp_core_rx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, + input [17:0] adc_i, input adc_ovf_a, + input [17:0] adc_q, input adc_ovf_b, output [31:0] sample, input run, @@ -60,40 +60,6 @@ module dsp_core_rx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); - rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [7:0] muxctrl; - setting_reg #(.my_addr(BASE+5), .width(8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(BASE+6), .width(2)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - always @(posedge clk) - case(muxctrl[3:0]) // The I mapping - 0: adc_i <= adc_a_ofs; - 1: adc_i <= adc_b_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case (muxctrl[3:0]) - - always @(posedge clk) - case(muxctrl[7:4]) // The Q mapping - 0: adc_q <= adc_a_ofs; - 1: adc_q <= adc_b_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case (muxctrl[7:4]) - always @(posedge clk) if(rst) phase <= 0; @@ -119,7 +85,6 @@ module dsp_core_rx .CE(1), // Clock enable input .R(rst) // Synchronous reset input ); - cordic_z24 #(.bitwidth(24)) cordic(.clock(clk), .reset(rst), .enable(run), @@ -164,10 +129,6 @@ module dsp_core_rx round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - reg [31:0] sample_reg; - always @(posedge clk) - sample_reg <= {i_out,q_out}; - assign sample = sample_reg; assign strobe = strobe_hb2; assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index 35dfb07ae..52f8cd5be 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -62,6 +62,6 @@ module rx_dcoffset (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop)); add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg - (.clk(clk), .in1(in), .in2(-quantized), .sum(out)); + (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out)); endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v new file mode 100644 index 000000000..f5271a207 --- /dev/null +++ b/usrp2/sdr_lib/rx_frontend.v @@ -0,0 +1,75 @@ + +module rx_frontend + #(parameter BASE = 0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [15:0] adc_a, input adc_ovf_a, + input [15:0] adc_b, input adc_ovf_b, + + output [17:0] i_out, output [17:0] q_out, + input run, + output [31:0] debug + ); + + reg [15:0] adc_i, adc_q; + wire [17:0] adc_i_ofs, adc_q_ofs; + wire [35:0] corr_i, corr_q; + wire [17:0] scale_i, scale_q; + wire [7:0] muxctrl; + wire [23:0] i_final, q_final; + + setting_reg #(.my_addr(BASE), .width(8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); + + always @(posedge clk) + case(muxctrl[3:0]) // The I mapping + 0: adc_i <= adc_a; + 1: adc_i <= adc_b; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case (muxctrl[3:0]) + + always @(posedge clk) + case(muxctrl[7:4]) // The Q mapping + 0: adc_q <= adc_a; + 1: adc_q <= adc_b; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case (muxctrl[7:4]) + + setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(scale_i),.changed()); + + setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(scale_q),.changed()); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_i,2'b00}),.out(adc_i_ofs)); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_q,2'b00}),.out(adc_q_ofs)); + + MULT18X18S mult_i + (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) ); + + MULT18X18S mult_q + (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_i + (.clk(clk), .rst(rst), + .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final)); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_q + (.clk(clk), .rst(rst), + .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final)); + + assign i_out = i_final[23:6]; + assign q_out = q_final[23:6]; + +endmodule // rx_frontend diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index ca9762ac5..691b60c1c 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -583,6 +583,17 @@ module u2_core assign sd_dat_i[31:8] = 0; // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [17:0] adc_i, adc_q; + + rx_frontend #(.BASE()) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; wire clear_rx0, strobe_rx0; @@ -593,7 +604,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -621,7 +632,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); 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