diff options
| -rw-r--r-- | usrp2/sdr_lib/add2_and_clip.v | 12 | ||||
| -rw-r--r-- | usrp2/sdr_lib/add2_and_clip_reg.v | 20 | ||||
| -rw-r--r-- | usrp2/sdr_lib/round.v | 4 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_dcoffset.v | 51 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_dcoffset_tb.v | 20 |
5 files changed, 80 insertions, 27 deletions
diff --git a/usrp2/sdr_lib/add2_and_clip.v b/usrp2/sdr_lib/add2_and_clip.v new file mode 100644 index 000000000..663f5d004 --- /dev/null +++ b/usrp2/sdr_lib/add2_and_clip.v @@ -0,0 +1,12 @@ + +module add2_and_clip + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip + (.in(sum_int),.out(sum)); + +endmodule // add2_and_clip diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v new file mode 100644 index 000000000..7070f1cea --- /dev/null +++ b/usrp2/sdr_lib/add2_and_clip_reg.v @@ -0,0 +1,20 @@ + +module add2_and_clip_reg + #(parameter WIDTH=16) + (input clk, + input rst, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + if(rst) + sum <= 0; + else + sum <= sum_int; + +endmodule // add2_and_clip_reg diff --git a/usrp2/sdr_lib/round.v b/usrp2/sdr_lib/round.v index c4f9ec9cd..7a137d702 100644 --- a/usrp2/sdr_lib/round.v +++ b/usrp2/sdr_lib/round.v @@ -26,8 +26,10 @@ module round #(parameter bits_in=0, parameter bits_out=0) (input [bits_in-1:0] in, - output [bits_out-1:0] out); + output [bits_out-1:0] out, + output [bits_in-bits_out:0] err); assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + assign err = in - {out,{(bits_in-bits_out){1'b0}}}; endmodule // round diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index 64ff4110d..35dfb07ae 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -18,43 +18,50 @@ module rx_dcoffset - #(parameter WIDTH=14, - parameter ADDR=8'd0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out); - - // Because of some extra delays to make timing easier, the transfer function is: - // (z-1)/(z^2-z-alpha) where alpha is 1/2^n + #(parameter WIDTH=16, + parameter ADDR=8'd0, + parameter alpha_shift=16) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [WIDTH-1:0] in, output [WIDTH-1:0] out); - wire set_now = set_stb & (ADDR == set_addr); + wire set_now = set_stb & (ADDR == set_addr); - reg fixed; // uses fixed offset - wire signed [WIDTH-1:0] fixed_dco; - reg signed [31:0] integrator; + reg fixed; // uses fixed offset + wire [WIDTH-1:0] fixed_dco; + localparam int_width = WIDTH + alpha_shift; + reg [int_width-1:0] integrator; + always @(posedge clk) if(rst) begin fixed <= 0; - integrator <= 32'd0; + integrator <= {int_width{1'b0}}; end else if(set_now) begin - integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}}; + //integrator <= {set_data[30:0],{(31-int_width){1'b0}}}; fixed <= set_data[31]; end else if(~fixed) - integrator <= integrator + adc_out; - - wire [WIDTH:0] scaled_integrator; + integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out}; + + wire [WIDTH-1:0] quantized; + wire [int_width-WIDTH:0] q_err; + wire [int_width-1:0] q_err_ext; + wire [int_width-1:0] q_loop; + + round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer + (.in(q_loop), .out(quantized), .err(q_err)); - round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator)); + sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend + (.in(q_err), .out(q_err_ext)); - wire [WIDTH:0] adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator; - - clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc - (.clk(clk),.in(adc_out_int),.out(adc_out)); + add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed + (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop)); + add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg + (.clk(clk), .in1(in), .in2(-quantized), .sum(out)); endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/rx_dcoffset_tb.v b/usrp2/sdr_lib/rx_dcoffset_tb.v index b0dd8cb05..b4fb66ad7 100644 --- a/usrp2/sdr_lib/rx_dcoffset_tb.v +++ b/usrp2/sdr_lib/rx_dcoffset_tb.v @@ -29,14 +29,26 @@ module rx_dcoffset_tb(); initial $dumpfile("rx_dcoffset_tb.vcd"); initial $dumpvars(0,rx_dcoffset_tb); - reg [13:0] adc_in = 7; + reg [13:0] adc_in; wire [13:0] adc_out; always @(posedge clk) - $display("%d\t%d",adc_in,adc_out); + begin + if(adc_in[13]) + $write("-%d,",-adc_in); + else + $write("%d,",adc_in); + if(adc_out[13]) + $write("-%d\n",-adc_out); + else + $write("%d\n",adc_out); + end - rx_dcoffset #(.WIDTH(14),.ADDR(0)) + rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8)) rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), - .adc_in(adc_in),.adc_out(adc_out)); + .in(adc_in),.out(adc_out)); + + always @(posedge clk) + adc_in <= (($random % 473) + 23)/4; endmodule // longfifo_tb |