diff options
| -rw-r--r-- | usrp2/fifo/dsp_framer36.v | 3 | ||||
| -rw-r--r-- | usrp2/fifo/packet_router.v | 3 | 
2 files changed, 4 insertions, 2 deletions
| diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index fbdc9fbd7..e44f91305 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -29,6 +29,7 @@ module dsp_framer36      //The header is generated here from the count.      wire [31:0] dsp_frm_data_bram;      wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; +    wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1;      assign out_data =          (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (          (dsp_frm_addr == dsp_frm_count)           ? {4'b0010, dsp_frm_data_bram}    : ( @@ -44,7 +45,7 @@ module dsp_framer36          .ENA(inp_ready),.SSRA(0),.WEA(inp_ready),          //port B = DSP framer interface (reads from BRAM)          .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0), -        .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0) +        .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0)      );      always @(posedge clk) diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index df1ba7351..5118c69b3 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -328,6 +328,7 @@ module packet_router          (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : (      4'b0000)); +    wire cpu_inp_enb = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? (cpu_inp_ready & cpu_inp_valid) : 1'b1;      assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0;      assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; @@ -337,7 +338,7 @@ module packet_router          .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i),          //port B = packet router interface from CPU (output only)          .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), -        .ENB(cpu_inp_ready & cpu_inp_valid),.SSRB(0),.WEB(1'b0) +        .ENB(cpu_inp_enb),.SSRB(0),.WEB(1'b0)      );      always @(posedge stream_clk) | 
