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-rw-r--r--usrp2/control_lib/Makefile.srcs4
-rw-r--r--usrp2/control_lib/bootram.v250
-rw-r--r--usrp2/control_lib/quad_uart.v71
-rw-r--r--usrp2/control_lib/ram_harvard2.v77
-rw-r--r--usrp2/control_lib/s3a_icap_wb.v56
-rw-r--r--usrp2/control_lib/v5icap_wb.v54
-rw-r--r--usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v4
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_defines.v4
-rw-r--r--usrp2/top/Makefile.common7
-rwxr-xr-xusrp2/top/python/check_inout.py62
-rw-r--r--usrp2/top/safe_u2plus/.gitignore2
-rw-r--r--usrp2/top/safe_u2plus/Makefile246
-rw-r--r--usrp2/top/safe_u2plus/safe_u2plus.v23
-rwxr-xr-xusrp2/top/safe_u2plus/u2plus.ucf401
-rw-r--r--usrp2/top/u2plus/.gitignore1
-rw-r--r--usrp2/top/u2plus/Makefile97
-rw-r--r--usrp2/top/u2plus/capture_ddrlvds.v39
-rwxr-xr-xusrp2/top/u2plus/u2plus.ucf544
-rw-r--r--usrp2/top/u2plus/u2plus.v322
-rw-r--r--usrp2/top/u2plus/u2plus_core.v824
20 files changed, 2691 insertions, 397 deletions
diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index bc8e4d5bc..666ac344c 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -21,6 +21,7 @@ nsgpio.v \
ram_2port.v \
ram_harv_cache.v \
ram_harvard.v \
+ram_harvard2.v \
ram_loader.v \
setting_reg.v \
settings_bus.v \
@@ -29,6 +30,7 @@ srl.v \
system_control.v \
wb_1master.v \
wb_readback_mux.v \
+quad_uart.v \
simple_uart.v \
simple_uart_tx.v \
simple_uart_rx.v \
@@ -42,4 +44,6 @@ pic.v \
longfifo.v \
shortfifo.v \
medfifo.v \
+s3a_icap_wb.v \
+bootram.v \
))
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v
new file mode 100644
index 000000000..668012504
--- /dev/null
+++ b/usrp2/control_lib/bootram.v
@@ -0,0 +1,250 @@
+
+// Boot RAM for S3A, 8KB, dual port
+
+// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
+// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
+
+module bootram
+ (input clk, input reset,
+ input [12:0] if_adr,
+ output [31:0] if_data,
+
+ input [12:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output reg dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
+ wire [31:0] DOA0, DOA1, DOA2, DOA3;
+ wire [31:0] DOB0, DOB1, DOB2, DOB3;
+ wire ENB0, ENB1, ENB2, ENB3;
+ wire [3:0] WEB;
+
+ reg [1:0] delayed_if_bank;
+ always @(posedge clk)
+ delayed_if_bank <= if_adr[12:11];
+
+ assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0);
+ assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0);
+
+ always @(posedge clk)
+ if(reset)
+ dwb_ack_o <= 0;
+ else
+ dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
+
+ assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
+ assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
+ assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
+ assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+
+ assign WEB = {4{dwb_we_i}} & dwb_sel_i;
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM0
+ (.DOA(DOA0), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB0), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB0), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM1
+ (.DOA(DOA1), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB1), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB1), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM2
+ (.DOA(DOA2), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB2), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB2), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+ RAMB16BWE_S36_S36
+ #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+ .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+ .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+ .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+ .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
+ .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE
+ RAM3
+ (.DOA(DOA3), // Port A 32-bit Data Output
+ .DOPA(), // Port A 4-bit Parity Output
+ .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+ .CLKA(clk), // Port A 1-bit Clock
+ .DIA(32'd0), // Port A 32-bit Data Input
+ .DIPA(4'd0), // Port A 4-bit parity Input
+ .ENA(1'b1), // Port A 1-bit RAM Enable Input
+ .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input
+ .WEA(1'b0), // Port A 4-bit Write Enable Input
+
+ .DOB(DOB3), // Port B 32-bit Data Output
+ .DOPB(), // Port B 4-bit Parity Output
+ .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+ .CLKB(clk), // Port B 1-bit Clock
+ .DIB(dwb_dat_i), // Port B 32-bit Data Input
+ .DIPB(4'd0), // Port-B 4-bit parity Input
+ .ENB(ENB3), // Port B 1-bit RAM Enable Input
+ .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input
+ .WEB(WEB) // Port B 4-bit Write Enable Input
+ ); // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram
+
+/*
+ // The following INIT_xx declarations specify the initial contents of the RAM
+ // Address 0 to 127
+ .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 128 to 255
+ .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 256 to 383
+ .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // Address 384 to 511
+ .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+ // The next set of INITP_xx are for the parity bits
+ // Address 0 to 127
+ .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 128 to 255
+ .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 256 to 383
+ .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ // Address 384 to 511
+ .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
+ .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
+*/
diff --git a/usrp2/control_lib/quad_uart.v b/usrp2/control_lib/quad_uart.v
new file mode 100644
index 000000000..afa6fae1d
--- /dev/null
+++ b/usrp2/control_lib/quad_uart.v
@@ -0,0 +1,71 @@
+
+module quad_uart
+ #(parameter TXDEPTH = 1,
+ parameter RXDEPTH = 1)
+ (input clk_i, input rst_i,
+ input we_i, input stb_i, input cyc_i, output reg ack_o,
+ input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+ output [3:0] rx_int_o, output [3:0] tx_int_o,
+ output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
+ );
+
+ // Register Map
+ localparam SUART_CLKDIV = 0;
+ localparam SUART_TXLEVEL = 1;
+ localparam SUART_RXLEVEL = 2;
+ localparam SUART_TXCHAR = 3;
+ localparam SUART_RXCHAR = 4;
+
+ wire wb_acc = cyc_i & stb_i; // WISHBONE access
+ wire wb_wr = wb_acc & we_i; // WISHBONE write access
+
+ reg [15:0] clkdiv[0:3];
+ wire [7:0] rx_char[0:3];
+ wire [3:0] tx_fifo_full, rx_fifo_empty;
+ wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
+
+ always @(posedge clk_i)
+ if (rst_i)
+ ack_o <= 1'b0;
+ else
+ ack_o <= wb_acc & ~ack_o;
+
+ integer i;
+ always @(posedge clk_i)
+ if (rst_i)
+ for(i=0;i<4;i=i+1)
+ clkdiv[i] <= 0;
+ else if (wb_wr)
+ case(adr_i[2:0])
+ SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
+ endcase // case(adr_i)
+
+ always @(posedge clk_i)
+ case (adr_i[2:0])
+ SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
+ SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
+ SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
+ endcase // case(adr_i)
+
+ genvar j;
+ generate
+ for(j=0;j<4;j=j+1)
+ begin : gen_uarts
+ simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+ (.clk(clk_i),.rst(rst_i),
+ .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
+ .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
+ .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
+
+ simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+ (.clk(clk_i),.rst(rst_i),
+ .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
+ .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
+ .clkdiv(clkdiv[j]),.rx(rx_i[j]));
+ end // block: gen_uarts
+ endgenerate
+
+ assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space
+ assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data
+
+endmodule // quad_uart
diff --git a/usrp2/control_lib/ram_harvard2.v b/usrp2/control_lib/ram_harvard2.v
new file mode 100644
index 000000000..67777af2a
--- /dev/null
+++ b/usrp2/control_lib/ram_harvard2.v
@@ -0,0 +1,77 @@
+
+
+// Dual ported, Harvard architecture
+
+module ram_harvard2
+ #(parameter AWIDTH=15,
+ parameter RAM_SIZE=32768)
+ (input wb_clk_i,
+ input wb_rst_i,
+ // Instruction fetch port.
+ input [AWIDTH-1:0] if_adr,
+ output reg [31:0] if_data,
+ // Data access port.
+ input [AWIDTH-1:0] dwb_adr_i,
+ input [31:0] dwb_dat_i,
+ output reg [31:0] dwb_dat_o,
+ input dwb_we_i,
+ output dwb_ack_o,
+ input dwb_stb_i,
+ input [3:0] dwb_sel_i);
+
+ reg ack_d1;
+ reg stb_d1;
+
+ assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ ack_d1 <= 1'b0;
+ else
+ ack_d1 <= dwb_ack_o;
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ stb_d1 <= 0;
+ else
+ stb_d1 <= dwb_stb_i;
+
+ reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
+ reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
+
+ // Port 1, Read only
+ always @(posedge wb_clk_i)
+ if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
+
+ // Port 2, R/W
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
+ always @(posedge wb_clk_i)
+ if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
+
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
+ ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
+ ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
+ ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
+ always @(posedge wb_clk_i)
+ if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
+ ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
+
+endmodule // ram_harvard
diff --git a/usrp2/control_lib/s3a_icap_wb.v b/usrp2/control_lib/s3a_icap_wb.v
new file mode 100644
index 000000000..9a9db0f96
--- /dev/null
+++ b/usrp2/control_lib/s3a_icap_wb.v
@@ -0,0 +1,56 @@
+
+
+module s3a_icap_wb
+ (input clk, input reset,
+ input cyc_i, input stb_i, input we_i, output ack_o,
+ input [31:0] dat_i, output [31:0] dat_o);
+
+ assign dat_o[31:8] = 24'd0;
+
+ wire BUSY, CE, WRITE;
+
+ reg [2:0] icap_state;
+ localparam ICAP_IDLE = 0;
+ localparam ICAP_WR0 = 1;
+ localparam ICAP_WR1 = 2;
+ localparam ICAP_RD0 = 3;
+ localparam ICAP_RD1 = 4;
+
+ always @(posedge clk)
+ if(reset)
+ icap_state <= ICAP_IDLE;
+ else
+ case(icap_state)
+ ICAP_IDLE :
+ begin
+ if(stb_i & cyc_i)
+ if(we_i)
+ icap_state <= ICAP_WR0;
+ else
+ icap_state <= ICAP_RD0;
+ end
+ ICAP_WR0 :
+ icap_state <= ICAP_WR1;
+ ICAP_WR1 :
+ icap_state <= ICAP_IDLE;
+ ICAP_RD0 :
+ icap_state <= ICAP_RD1;
+ ICAP_RD1 :
+ icap_state <= ICAP_IDLE;
+ endcase // case (icap_state)
+
+ assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+ assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
+
+ assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+
+ ICAP_SPARTAN3A ICAP_SPARTAN3A_inst
+ (.BUSY(BUSY), // Busy output
+ .O(dat_o[7:0]), // 32-bit data output
+ .CE(~CE), // Clock enable input
+ .CLK(clk), // Clock input
+ .I(dat_i[7:0]), // 32-bit data input
+ .WRITE(~WRITE) // Write input
+ );
+
+endmodule // s3a_icap_wb
diff --git a/usrp2/control_lib/v5icap_wb.v b/usrp2/control_lib/v5icap_wb.v
new file mode 100644
index 000000000..c8800285a
--- /dev/null
+++ b/usrp2/control_lib/v5icap_wb.v
@@ -0,0 +1,54 @@
+
+
+module v5icap_wb
+ (input clk, input reset,
+ input cyc_i, input stb_i, input we_i, output ack_o,
+ input [31:0] dat_i, output [31:0] dat_o);
+
+ wire BUSY, CE, WRITE;
+
+ reg [2:0] icap_state;
+ localparam ICAP_IDLE = 0;
+ localparam ICAP_WR0 = 1;
+ localparam ICAP_WR1 = 2;
+ localparam ICAP_RD0 = 3;
+ localparam ICAP_RD1 = 4;
+
+ always @(posedge clk)
+ if(reset)
+ icap_state <= ICAP_IDLE;
+ else
+ case(icap_state)
+ ICAP_IDLE :
+ begin
+ if(stb_i & cyc_i)
+ if(we_i)
+ icap_state <= ICAP_WR0;
+ else
+ icap_state <= ICAP_RD0;
+ end
+ ICAP_WR0 :
+ icap_state <= ICAP_WR1;
+ ICAP_WR1 :
+ icap_state <= ICAP_IDLE;
+ ICAP_RD0 :
+ icap_state <= ICAP_RD1;
+ ICAP_RD1 :
+ icap_state <= ICAP_IDLE;
+ endcase // case (icap_state)
+
+ assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+ assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
+
+ assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+
+ ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst
+ (.BUSY(BUSY), // Busy output
+ .O(dat_o), // 32-bit data output
+ .CE(~CE), // Clock enable input
+ .CLK(clk), // Clock input
+ .I(dat_i), // 32-bit data input
+ .WRITE(~WRITE) // Write input
+ );
+
+endmodule // v5icap_wb
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
index 38ca3a023..6c066d5d9 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -11,7 +11,7 @@ module aeMB_core_BE
(input sys_clk_i,
input sys_rst_i,
// Instruction port
- output [14:0] if_adr,
+ output [ISIZ-1:0] if_adr,
input [31:0] if_dat,
// Data port
output dwb_we_o,
@@ -34,7 +34,7 @@ module aeMB_core_BE
assign dwb_cyc_o = dwb_stb_o;
assign iwb_ack_i = 1'b1;
- assign if_adr = iwb_adr_o[14:0];
+ assign if_adr = iwb_adr_o[ISIZ-1:0];
assign iwb_dat_i = if_dat;
// Note some "wishbone" instruction fetch signals pruned on external interface
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..25c08214b 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -102,8 +102,8 @@
// Number of device select signals. Use SPI_SS_NB for fine tuning the
// exact number.
//
-`define SPI_SS_NB_8
-//`define SPI_SS_NB_16
+//`define SPI_SS_NB_8
+`define SPI_SS_NB_16
//`define SPI_SS_NB_24
//`define SPI_SS_NB_32
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 4da64ac28..1114c731e 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -13,8 +13,10 @@ else
endif
BASE_DIR = $(abspath ..)
ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
+BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
##################################################
@@ -25,12 +27,13 @@ all: bin
proj: $(ISE_FILE)
check: $(ISE_FILE)
+ $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf
$(ISE_HELPER) "Check Syntax"
synth: $(ISE_FILE)
$(ISE_HELPER) "Synthesize - XST"
-bin: $(BIN_FILE)
+bin: check $(BIN_FILE)
mcs: $(MCS_FILE)
@@ -53,6 +56,6 @@ $(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
touch $@
$(MCS_FILE): $(BIN_FILE)
- promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE)
+ promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE)
.EXPORT_ALL_VARIABLES:
diff --git a/usrp2/top/python/check_inout.py b/usrp2/top/python/check_inout.py
new file mode 100755
index 000000000..ff371d378
--- /dev/null
+++ b/usrp2/top/python/check_inout.py
@@ -0,0 +1,62 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Description:
+# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
+# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
+
+import sys
+import re
+
+if __name__=='__main__':
+ if len(sys.argv) == 2:
+ print "Usage: %s <top level Verilog file> <pin definition UCF>"
+ sys.exit(-1)
+
+ verilog_filename = sys.argv[1]
+ ucf_filename = sys.argv[2]
+
+ verilog_file = open(verilog_filename, 'r')
+ ucf_file = open(ucf_filename, 'r')
+
+ verilog_iolist = list()
+ ucf_iolist = list()
+
+ #read in all input, inout, and output declarations and compile a list
+ for line in verilog_file:
+ for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
+ verilog_iolist.append(match)
+
+ for line in ucf_file:
+ m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
+ if m is not None:
+ ucf_iolist.append(m.group(1))
+
+ #now find corresponding matches and error when you don't find one
+ #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
+ err = False
+
+ for item in verilog_iolist:
+ if item not in ucf_iolist:
+ print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+ err = True
+
+ if err:
+ sys.exit(-1)
+
+ print "No errors found."
+ sys.exit(0)
diff --git a/usrp2/top/safe_u2plus/.gitignore b/usrp2/top/safe_u2plus/.gitignore
new file mode 100644
index 000000000..a96f0be92
--- /dev/null
+++ b/usrp2/top/safe_u2plus/.gitignore
@@ -0,0 +1,2 @@
+build*
+*impact*
diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile
new file mode 100644
index 000000000..62a02ff40
--- /dev/null
+++ b/usrp2/top/safe_u2plus/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := safe_u2plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2plus/capture_ddrlvds.v \
+top/safe_u2plus/u2plus.ucf \
+top/safe_u2plus/safe_u2plus.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v
new file mode 100644
index 000000000..dca9688c5
--- /dev/null
+++ b/usrp2/top/safe_u2plus/safe_u2plus.v
@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module safe_u2plus
+ (
+ input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+ output [5:1] leds, // LED4 is shared w/INIT_B
+ output ETH_LED
+ );
+
+ wire clk_fpga;
+
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ reg [31:0] ctr;
+
+ always @(posedge clk_fpga)
+ ctr <= ctr + 1;
+
+ assign {leds,ETH_LED} = ~ctr[29:24];
+
+endmodule // safe_u2plus
diff --git a/usrp2/top/safe_u2plus/u2plus.ucf b/usrp2/top/safe_u2plus/u2plus.ucf
new file mode 100755
index 000000000..0a9460d86
--- /dev/null
+++ b/usrp2/top/safe_u2plus/u2plus.ucf
@@ -0,0 +1,401 @@
+## Main 100 MHz Clock
+NET "CLK_FPGA_P" LOC = "AA13" ;
+NET "CLK_FPGA_N" LOC = "Y13" ;
+
+## ADC
+#NET "ADC_clkout_p" LOC = "P1" ;
+#NET "ADC_clkout_n" LOC = "P2" ;
+#NET "ADCA_12_p" LOC = "Y1" ;
+#NET "ADCA_12_n" LOC = "Y2" ;
+#NET "ADCA_10_p" LOC = "W3" ;
+#NET "ADCA_10_n" LOC = "W4" ;
+#NET "ADCA_8_p" LOC = "T7" ;
+#NET "ADCA_8_n" LOC = "U6" ;
+#NET "ADCA_6_p" LOC = "U5" ;
+#NET "ADCA_6_n" LOC = "V5" ;
+#NET "ADCA_4_p" LOC = "T10" ;
+#NET "ADCA_4_n" LOC = "T9" ;
+#NET "ADCA_2_p" LOC = "V1" ;
+#NET "ADCA_2_n" LOC = "V2" ;
+#NET "ADCA_0_p" LOC = "R8" ;
+#NET "ADCA_0_n" LOC = "R7" ;
+#NET "ADCB_2_p" LOC = "U7" ;
+#NET "ADCB_2_n" LOC = "U8" ;
+#NET "ADCB_0_p" LOC = "AA2" ;
+#NET "ADCB_0_n" LOC = "AA3" ;
+#NET "ADCB_4_p" LOC = "AE1" ;
+#NET "ADCB_4_n" LOC = "AE2" ;
+#NET "ADCB_6_p" LOC = "W1" ;
+#NET "ADCB_6_n" LOC = "W2" ;
+#NET "ADCB_8_p" LOC = "U3" ;
+#NET "ADCB_8_n" LOC = "V4" ;
+#NET "ADCB_10_p" LOC = "J1" ;
+#NET "ADCB_10_n" LOC = "K1" ;
+#NET "ADCB_12_p" LOC = "J3" ;
+#NET "ADCB_12_n" LOC = "J2" ;
+
+## DAC
+#NET "DAC_LOCK" LOC = "P4" ;
+#NET "DACA<0>" LOC = "P8" ;
+#NET "DACA<1>" LOC = "P9" ;
+#NET "DACA<2>" LOC = "R5" ;
+#NET "DACA<3>" LOC = "R6" ;
+#NET "DACA<4>" LOC = "P7" ;
+#NET "DACA<5>" LOC = "P6" ;
+#NET "DACA<6>" LOC = "T3" ;
+#NET "DACA<7>" LOC = "T4" ;
+#NET "DACA<8>" LOC = "R3" ;
+#NET "DACA<9>" LOC = "R4" ;
+#NET "DACA<10>" LOC = "R2" ;
+#NET "DACA<11>" LOC = "N1" ;
+#NET "DACA<12>" LOC = "N2" ;
+#NET "DACA<13>" LOC = "N5" ;
+#NET "DACA<14>" LOC = "N4" ;
+#NET "DACA<15>" LOC = "M2" ;
+#NET "DACB<0>" LOC = "M5" ;
+#NET "DACB<1>" LOC = "M6" ;
+#NET "DACB<2>" LOC = "M4" ;
+#NET "DACB<3>" LOC = "M3" ;
+#NET "DACB<4>" LOC = "M8" ;
+#NET "DACB<5>" LOC = "M7" ;
+#NET "DACB<6>" LOC = "L4" ;
+#NET "DACB<7>" LOC = "L3" ;
+#NET "DACB<8>" LOC = "K3" ;
+#NET "DACB<9>" LOC = "K2" ;
+#NET "DACB<10>" LOC = "K5" ;
+#NET "DACB<11>" LOC = "K4" ;
+#NET "DACB<12>" LOC = "M10" ;
+#NET "DACB<13>" LOC = "M9" ;
+#NET "DACB<14>" LOC = "J5" ;
+#NET "DACB<15>" LOC = "J4" ;
+
+## TX DB GPIO
+#NET "io_tx<15>" LOC = "K6" ;
+#NET "io_tx<14>" LOC = "L7" ;
+#NET "io_tx<13>" LOC = "H2" ;
+#NET "io_tx<12>" LOC = "H1" ;
+#NET "io_tx<11>" LOC = "L10" ;
+#NET "io_tx<10>" LOC = "L9" ;
+#NET "io_tx<9>" LOC = "G3" ;
+#NET "io_tx<8>" LOC = "F3" ;
+#NET "io_tx<7>" LOC = "K7" ;
+#NET "io_tx<6>" LOC = "J6" ;
+#NET "io_tx<5>" LOC = "E1" ;
+#NET "io_tx<4>" LOC = "F2" ;
+#NET "io_tx<3>" LOC = "J7" ;
+#NET "io_tx<2>" LOC = "H6" ;
+#NET "io_tx<1>" LOC = "F5" ;
+#NET "io_tx<0>" LOC = "G4" ;
+
+## RX DB GPIO
+#NET "io_rx<15>" LOC = "AD1" ;
+#NET "io_rx<14>" LOC = "AD2" ;
+#NET "io_rx<13>" LOC = "AC2" ;
+#NET "io_rx<12>" LOC = "AC3" ;
+#NET "io_rx<11>" LOC = "W7" ;
+#NET "io_rx<10>" LOC = "W6" ;
+#NET "io_rx<9>" LOC = "U9" ;
+#NET "io_rx<8>" LOC = "V8" ;
+#NET "io_rx<7>" LOC = "AB1" ;
+#NET "io_rx<6>" LOC = "AC1" ;
+#NET "io_rx<5>" LOC = "V7" ;
+#NET "io_rx<4>" LOC = "V6" ;
+#NET "io_rx<3>" LOC = "Y5" ;
+#NET "io_rx<2>" LOC = "R10" ;
+#NET "io_rx<1>" LOC = "R1" ;
+#NET "io_rx<0>" LOC = "M1" ;
+
+## MISC
+NET "leds<5>" LOC = "AF25" ;
+NET "leds<4>" LOC = "AE25" ;
+NET "leds<3>" LOC = "AF23" ;
+NET "leds<2>" LOC = "AE23" ;
+NET "leds<1>" LOC = "AB18" ;
+#NET "FPGA_RESET" LOC = "K24" ;
+
+## Debug
+#NET "debug_clk<0>" LOC = "AA10" ;
+#NET "debug_clk<1>" LOC = "AD11" ;
+#NET "debug<0>" LOC = "AC19" ;
+#NET "debug<1>" LOC = "AF20" ;
+#NET "debug<2>" LOC = "AE20" ;
+#NET "debug<3>" LOC = "AC16" ;
+#NET "debug<4>" LOC = "AB16" ;
+#NET "debug<5>" LOC = "AF19" ;
+#NET "debug<6>" LOC = "AE19" ;
+#NET "debug<7>" LOC = "V15" ;
+#NET "debug<8>" LOC = "U15" ;
+#NET "debug<9>" LOC = "AE17" ;
+#NET "debug<10>" LOC = "AD17" ;
+#NET "debug<11>" LOC = "V14" ;
+#NET "debug<12>" LOC = "W15" ;
+#NET "debug<13>" LOC = "AC15" ;
+#NET "debug<14>" LOC = "AD14" ;
+#NET "debug<15>" LOC = "AC14" ;
+#NET "debug<16>" LOC = "AC11" ;
+#NET "debug<17>" LOC = "AB12" ;
+#NET "debug<18>" LOC = "AC12" ;
+#NET "debug<19>" LOC = "V13" ;
+#NET "debug<20>" LOC = "W13" ;
+#NET "debug<21>" LOC = "AE8" ;
+#NET "debug<22>" LOC = "AF8" ;
+#NET "debug<23>" LOC = "V12" ;
+#NET "debug<24>" LOC = "W12" ;
+#NET "debug<25>" LOC = "AB9" ;
+#NET "debug<26>" LOC = "AC9" ;
+#NET "debug<27>" LOC = "AC8" ;
+#NET "debug<28>" LOC = "AB7" ;
+#NET "debug<29>" LOC = "V11" ;
+#NET "debug<30>" LOC = "U11" ;
+#NET "debug<31>" LOC = "Y10" ;
+
+## UARTS
+#NET "TXD<3>" LOC = "AD20" ;
+#NET "TXD<2>" LOC = "AC20" ;
+#NET "TXD<1>" LOC = "AD19" ;
+#NET "RXD<3>" LOC = "AF17" ;
+#NET "RXD<2>" LOC = "AF15" ;
+#NET "RXD<1>" LOC = "AD12" ;
+
+## AD9510
+#NET "CLK_STATUS" LOC = "AD22" ;
+#NET "CLK_FUNC" LOC = "AC21" ;
+#NET "clk_sel<0>" LOC = "AE21" ;
+#NET "clk_sel<1>" LOC = "AD21" ;
+#NET "clk_en<1>" LOC = "AA17" ;
+#NET "clk_en<0>" LOC = "Y17" ;
+
+## I2C
+#NET "SDA" LOC = "V16" ;
+#NET "SCL" LOC = "U16" ;
+
+## Timing
+#NET "PPS_IN" LOC = "AB6" ;
+#NET "PPS2_IN" LOC = "AA20" ;
+
+## SPI
+#NET "SEN_CLK" LOC = "AA18" ;
+#NET "MOSI_CLK" LOC = "W17" ;
+#NET "SCLK_CLK" LOC = "V17" ;
+#NET "MISO_CLK" LOC = "AC10" ;
+
+#NET "SEN_DAC" LOC = "AE7" ;
+#NET "SCLK_DAC" LOC = "AF5" ;
+#NET "MOSI_DAC" LOC = "AE6" ;
+#NET "MISO_DAC" LOC = "Y3" ;
+
+#NET "SCLK_ADC" LOC = "B1" ;
+#NET "MOSI_ADC" LOC = "J8" ;
+#NET "SEN_ADC" LOC = "J9" ;
+
+#NET "MOSI_TX_ADC" LOC = "V10" ;
+#NET "SEN_TX_ADC" LOC = "W10" ;
+#NET "SCLK_TX_ADC" LOC = "AC6" ;
+#NET "MISO_TX_ADC" LOC = "G1" ;
+
+#NET "MOSI_TX_DAC" LOC = "AD6" ;
+#NET "SEN_TX_DAC" LOC = "AE4" ;
+#NET "SCLK_TX_DAC" LOC = "AF4" ;
+
+#NET "SCLK_TX_DB" LOC = "AE3" ;
+#NET "MOSI_TX_DB" LOC = "AF3" ;
+#NET "SEN_TX_DB" LOC = "W9" ;
+#NET "MISO_TX_DB" LOC = "AA5" ;
+
+#NET "MOSI_RX_ADC" LOC = "E3" ;
+#NET "SCLK_RX_ADC" LOC = "F4" ;
+#NET "SEN_RX_ADC" LOC = "D3" ;
+#NET "MISO_RX_ADC" LOC = "C1" ;
+
+#NET "SCLK_RX_DAC" LOC = "E4" ;
+#NET "SEN_RX_DAC" LOC = "K9" ;
+#NET "MOSI_RX_DAC" LOC = "K8" ;
+
+#NET "SCLK_RX_DB" LOC = "G6" ;
+#NET "MOSI_RX_DB" LOC = "H7" ;
+#NET "SEN_RX_DB" LOC = "B2" ;
+#NET "MISO_RX_DB" LOC = "H4" ;
+
+## ETH PHY
+#NET "CLK_TO_MAC" LOC = "P26" ;
+
+#NET "GMII_TXD<7>" LOC = "G21" ;
+#NET "GMII_TXD<6>" LOC = "C26" ;
+#NET "GMII_TXD<5>" LOC = "C25" ;
+#NET "GMII_TXD<4>" LOC = "J21" ;
+#NET "GMII_TXD<3>" LOC = "H21" ;
+#NET "GMII_TXD<2>" LOC = "D25" ;
+#NET "GMII_TXD<1>" LOC = "D24" ;
+#NET "GMII_TXD<0>" LOC = "E26" ;
+#NET "GMII_TX_EN" LOC = "D26" ;
+#NET "GMII_TX_ER" LOC = "J19" ;
+#NET "GMII_GTX_CLK" LOC = "J20" ;
+#NET "GMII_TX_CLK" LOC = "P25" ;
+
+#NET "GMII_RX_CLK" LOC = "P21" ;
+#NET "GMII_RXD<7>" LOC = "G22" ;
+#NET "GMII_RXD<6>" LOC = "K19" ;
+#NET "GMII_RXD<5>" LOC = "K18" ;
+#NET "GMII_RXD<4>" LOC = "E24" ;
+#NET "GMII_RXD<3>" LOC = "F23" ;
+#NET "GMII_RXD<2>" LOC = "L18" ;
+#NET "GMII_RXD<1>" LOC = "L17" ;
+#NET "GMII_RXD<0>" LOC = "F25" ;
+#NET "GMII_RX_DV" LOC = "F24" ;
+#NET "GMII_RX_ER" LOC = "L20" ;
+#NET "GMII_CRS" LOC = "K20" ;
+#NET "GMII_COL" LOC = "G23" ;
+
+#NET "PHY_INTn" LOC = "L22" ;
+#NET "MDIO" LOC = "K21" ;
+#NET "MDC" LOC = "J23" ;
+#NET "PHY_RESETn" LOC = "J22" ;
+NET "ETH_LED" LOC = "H20" ;
+
+## MIMO Interface
+#NET "exp_time_out_p" LOC = "Y14" ;
+#NET "exp_time_out_n" LOC = "AA14" ;
+#NET "exp_time_in_p" LOC = "N18" ;
+#NET "exp_time_in_n" LOC = "N17" ;
+#NET "exp_user_out_p" LOC = "AF14" ;
+#NET "exp_user_out_n" LOC = "AE14" ;
+#NET "exp_user_in_p" LOC = "L24" ;
+#NET "exp_user_in_n" LOC = "M23" ;
+
+## SERDES
+#NET "ser_enable" LOC = "R20" ;
+#NET "ser_prbsen" LOC = "U23" ;
+#NET "ser_loopen" LOC = "R19" ;
+#NET "ser_rx_en" LOC = "Y21" ;
+#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK
+#NET "ser_t<15>" LOC = "V23" ;
+#NET "ser_t<14>" LOC = "U22" ;
+#NET "ser_t<13>" LOC = "V24" ;
+#NET "ser_t<12>" LOC = "V25" ;
+#NET "ser_t<11>" LOC = "W23" ;
+#NET "ser_t<10>" LOC = "V22" ;
+#NET "ser_t<9>" LOC = "T18" ;
+#NET "ser_t<8>" LOC = "T17" ;
+#NET "ser_t<7>" LOC = "Y24" ;
+#NET "ser_t<6>" LOC = "Y25" ;
+#NET "ser_t<5>" LOC = "U21" ;
+#NET "ser_t<4>" LOC = "T20" ;
+#NET "ser_t<3>" LOC = "Y22" ;
+#NET "ser_t<2>" LOC = "Y23" ;
+#NET "ser_t<1>" LOC = "U19" ;
+#NET "ser_t<0>" LOC = "U18" ;
+#NET "ser_tkmsb" LOC = "AA24" ;
+#NET "ser_tklsb" LOC = "AA25" ;
+#NET "ser_rx_clk" LOC = "P18" ;
+#NET "ser_r<15>" LOC = "V21" ;
+#NET "ser_r<14>" LOC = "U20" ;
+#NET "ser_r<13>" LOC = "AA22" ;
+#NET "ser_r<12>" LOC = "AA23" ;
+#NET "ser_r<11>" LOC = "V18" ;
+#NET "ser_r<10>" LOC = "V19" ;
+#NET "ser_r<9>" LOC = "AB23" ;
+#NET "ser_r<8>" LOC = "AC26" ;
+#NET "ser_r<7>" LOC = "AB26" ;
+#NET "ser_r<6>" LOC = "AD26" ;
+#NET "ser_r<5>" LOC = "AC25" ;
+#NET "ser_r<4>" LOC = "W20" ;
+#NET "ser_r<3>" LOC = "W21" ;
+#NET "ser_r<2>" LOC = "AC23" ;
+#NET "ser_r<1>" LOC = "AC24" ;
+#NET "ser_r<0>" LOC = "AE26" ;
+#NET "ser_rkmsb" LOC = "AD25" ;
+#NET "ser_rklsb" LOC = "Y20" ;
+
+## SRAM
+#NET "RAM_D<35>" LOC = "K16" ;
+#NET "RAM_D<34>" LOC = "D20" ;
+#NET "RAM_D<33>" LOC = "C20" ;
+#NET "RAM_D<32>" LOC = "E21" ;
+#NET "RAM_D<31>" LOC = "D21" ;
+#NET "RAM_D<30>" LOC = "C21" ;
+#NET "RAM_D<29>" LOC = "B21" ;
+#NET "RAM_D<28>" LOC = "H17" ;
+#NET "RAM_D<27>" LOC = "G17" ;
+#NET "RAM_D<26>" LOC = "B23" ;
+#NET "RAM_D<25>" LOC = "A22" ;
+#NET "RAM_D<24>" LOC = "D23" ;
+#NET "RAM_D<23>" LOC = "C23" ;
+#NET "RAM_D<22>" LOC = "D22" ;
+#NET "RAM_D<21>" LOC = "C22" ;
+#NET "RAM_D<20>" LOC = "F19" ;
+#NET "RAM_D<19>" LOC = "G20" ;
+#NET "RAM_D<18>" LOC = "F20" ;
+#NET "RAM_D<17>" LOC = "F7" ;
+#NET "RAM_D<16>" LOC = "E7" ;
+#NET "RAM_D<15>" LOC = "G9" ;
+#NET "RAM_D<14>" LOC = "H9" ;
+#NET "RAM_D<13>" LOC = "G10" ;
+#NET "RAM_D<12>" LOC = "H10" ;
+#NET "RAM_D<11>" LOC = "A4" ;
+#NET "RAM_D<10>" LOC = "B4" ;
+#NET "RAM_D<9>" LOC = "C5" ;
+#NET "RAM_D<8>" LOC = "D6" ;
+#NET "RAM_D<7>" LOC = "J11" ;
+#NET "RAM_D<6>" LOC = "K11" ;
+#NET "RAM_D<5>" LOC = "B7" ;
+#NET "RAM_D<4>" LOC = "C7" ;
+#NET "RAM_D<3>" LOC = "B6" ;
+#NET "RAM_D<2>" LOC = "C6" ;
+#NET "RAM_D<1>" LOC = "C8" ;
+#NET "RAM_D<0>" LOC = "D8" ;
+#NET "RAM_A<0>" LOC = "C11" ;
+#NET "RAM_A<1>" LOC = "E12" ;
+#NET "RAM_A<2>" LOC = "F12" ;
+#NET "RAM_A<3>" LOC = "D13" ;
+#NET "RAM_A<4>" LOC = "C12" ;
+#NET "RAM_A<5>" LOC = "A12" ;
+#NET "RAM_A<6>" LOC = "B12" ;
+#NET "RAM_A<7>" LOC = "E14" ;
+#NET "RAM_A<8>" LOC = "F14" ;
+#NET "RAM_A<9>" LOC = "B15" ;
+#NET "RAM_A<10>" LOC = "A15" ;
+#NET "RAM_A<11>" LOC = "D16" ;
+#NET "RAM_A<12>" LOC = "C15" ;
+#NET "RAM_A<13>" LOC = "D17" ;
+#NET "RAM_A<14>" LOC = "C16" ;
+#NET "RAM_A<15>" LOC = "F15" ;
+#NET "RAM_A<16>" LOC = "C17" ;
+#NET "RAM_A<17>" LOC = "B17" ;
+#NET "RAM_A<18>" LOC = "B18" ;
+#NET "RAM_A<19>" LOC = "A18" ;
+#NET "RAM_A<20>" LOC = "D18" ;
+#NET "RAM_BWn<3>" LOC = "D9" ;
+#NET "RAM_BWn<2>" LOC = "A9" ;
+#NET "RAM_BWn<1>" LOC = "B9" ;
+#NET "RAM_BWn<0>" LOC = "G12" ;
+#NET "RAM_ZZ" LOC = "J12" ;
+#NET "RAM_LDn" LOC = "H12" ;
+#NET "RAM_OEn" LOC = "C10" ;
+#NET "RAM_WEn" LOC = "D10" ;
+#NET "RAM_CENn" LOC = "B10" ;
+#NET "RAM_CLK" LOC = "A10" ;
+
+## SPI Flash
+#NET "flash_miso" LOC = "AF24" ;
+#NET "flash_clk" LOC = "AE24" ;
+#NET "flash_mosi" LOC = "AB15" ;
+#NET "flash_cs" LOC = "AA7" ;
+
+## MISC FPGA, unused for now
+##NET "PROG_B" LOC = "A2" ;
+##NET "PUDC_B" LOC = "G8" ;
+##NET "DONE" LOC = "AB21" ;
+##NET "INIT_B" LOC = "AA15" ;
+
+
+##NET "unnamed_net19" LOC = "AE9" ; # VS1
+##NET "unnamed_net18" LOC = "AF9" ; # VS0
+##NET "unnamed_net17" LOC = "AA12" ; # VS2
+##NET "unnamed_net16" LOC = "Y7" ; # M2
+##NET "unnamed_net15" LOC = "AC4" ; # M1
+##NET "unnamed_net14" LOC = "AD4" ; # M0
+##NET "unnamed_net13" LOC = "D4" ; # TMS
+##NET "unnamed_net12" LOC = "E23" ; # TDO
+##NET "unnamed_net11" LOC = "G7" ; # TDI
+##NET "unnamed_net10" LOC = "A25" ; # TCK
+##NET "unnamed_net20" LOC = "V20" ; # SUSPEND
diff --git a/usrp2/top/u2plus/.gitignore b/usrp2/top/u2plus/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/usrp2/top/u2plus/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile
new file mode 100644
index 000000000..23eb8908e
--- /dev/null
+++ b/usrp2/top/u2plus/Makefile
@@ -0,0 +1,97 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v
new file mode 100644
index 000000000..b9f53ff8c
--- /dev/null
+++ b/usrp2/top/u2plus/capture_ddrlvds.v
@@ -0,0 +1,39 @@
+
+
+module capture_ddrlvds
+ #(parameter WIDTH=7)
+ (input clk,
+ input ssclk_p,
+ input ssclk_n,
+ input [WIDTH-1:0] in_p,
+ input [WIDTH-1:0] in_n,
+ output reg [(2*WIDTH)-1:0] out);
+
+ wire [WIDTH-1:0] ddr_dat;
+ wire ssclk_regional;
+ wire ssclk_io;
+ wire ssclk;
+ wire [(2*WIDTH)-1:0] out_pre1;
+ reg [(2*WIDTH)-1:0] out_pre2;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+
+ genvar i;
+ generate
+ for(i = 0; i < WIDTH; i = i + 1)
+ begin : gen_lvds_pins
+ IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds
+ (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
+ IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2
+ (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk),
+ .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
+ end
+ endgenerate
+
+ always @(negedge clk)
+ out_pre2 <= out_pre1;
+
+ always @(posedge clk)
+ out <= out_pre2;
+
+endmodule // capture_ddrlvds
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 091eb2005..aee9e57bf 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -1,157 +1,137 @@
-NET "DAC_LOCK" LOC = "P4" ;
+## Main 100 MHz Clock
+NET "CLK_FPGA_P" LOC = "AA13" ;
+NET "CLK_FPGA_N" LOC = "Y13" ;
+
+## ADC
NET "ADC_clkout_p" LOC = "P1" ;
NET "ADC_clkout_n" LOC = "P2" ;
-NET "io_rx<15>" LOC = "AD1" ;
-NET "io_rx<14>" LOC = "AD2" ;
-NET "io_rx<13>" LOC = "AC2" ;
-NET "io_rx<12>" LOC = "AC3" ;
-NET "io_rx<11>" LOC = "W7" ;
-NET "io_rx<10>" LOC = "W6" ;
-NET "io_rx<09>" LOC = "U9" ;
-NET "io_rx<08>" LOC = "V8" ;
-NET "io_rx<07>" LOC = "AB1" ;
-NET "io_rx<06>" LOC = "AC1" ;
-NET "io_rx<05>" LOC = "V7" ;
-NET "io_rx<04>" LOC = "V6" ;
-NET "io_rx<03>" LOC = "Y5" ;
-NET "ADCB_2_3_p" LOC = "U7" ;
-NET "ADCB_2_3_n" LOC = "U8" ;
-NET "ADCB_0_1_p" LOC = "AA2" ;
-NET "ADCB_0_1_n" LOC = "AA3" ;
-NET "ADCA_12_13_p" LOC = "Y1" ;
-NET "ADCA_12_13_n" LOC = "Y2" ;
-NET "ADCA_10_11_p" LOC = "W3" ;
-NET "ADCA_10_11_n" LOC = "W4" ;
-NET "ADCA_8_9_p" LOC = "T7" ;
-NET "ADCA_8_9_n" LOC = "U6" ;
-NET "ADCA_6_7_p" LOC = "U5" ;
-NET "ADCA_6_7_n" LOC = "V5" ;
-NET "ADCA_4_5_p" LOC = "T10" ;
-NET "ADCA_4_5_n" LOC = "T9" ;
-NET "ADCA_2_3_p" LOC = "V1" ;
-NET "ADCA_2_3_n" LOC = "V2" ;
-NET "ADCA_0_1_p" LOC = "R8" ;
-NET "ADCA_0_1_n" LOC = "R7" ;
-NET "TX00_A" LOC = "P8" ;
-NET "TX01_A" LOC = "P9" ;
-NET "TX02_A" LOC = "R5" ;
-NET "TX03_A" LOC = "R6" ;
-NET "TX04_A" LOC = "P7" ;
-NET "TX05_A" LOC = "P6" ;
-NET "TX06_A" LOC = "T3" ;
-NET "TX07_A" LOC = "T4" ;
-NET "TX08_A" LOC = "R3" ;
-NET "TX09_A" LOC = "R4" ;
-NET "TX10_A" LOC = "R2" ;
-NET "TX11_A" LOC = "N1" ;
-NET "TX12_A" LOC = "N2" ;
-NET "TX13_A" LOC = "N5" ;
-NET "TX14_A" LOC = "N4" ;
-NET "TX15_A" LOC = "M2" ;
-NET "TX00_B" LOC = "M5" ;
-NET "TX01_B" LOC = "M6" ;
-NET "TX02_B" LOC = "M4" ;
-NET "TX03_B" LOC = "M3" ;
-NET "TX04_B" LOC = "M8" ;
-NET "TX05_B" LOC = "M7" ;
-NET "TX06_B" LOC = "L4" ;
-NET "TX07_B" LOC = "L3" ;
-NET "TX08_B" LOC = "K3" ;
-NET "TX09_B" LOC = "K2" ;
-NET "TX10_B" LOC = "K5" ;
-NET "TX11_B" LOC = "K4" ;
-NET "TX12_B" LOC = "M10" ;
-NET "TX13_B" LOC = "M9" ;
-NET "TX14_B" LOC = "J5" ;
-NET "TX15_B" LOC = "J4" ;
+NET "ADCA_12_p" LOC = "Y1" ;
+NET "ADCA_12_n" LOC = "Y2" ;
+NET "ADCA_10_p" LOC = "W3" ;
+NET "ADCA_10_n" LOC = "W4" ;
+NET "ADCA_8_p" LOC = "T7" ;
+NET "ADCA_8_n" LOC = "U6" ;
+NET "ADCA_6_p" LOC = "U5" ;
+NET "ADCA_6_n" LOC = "V5" ;
+NET "ADCA_4_p" LOC = "T10" ;
+NET "ADCA_4_n" LOC = "T9" ;
+NET "ADCA_2_p" LOC = "V1" ;
+NET "ADCA_2_n" LOC = "V2" ;
+NET "ADCA_0_p" LOC = "R8" ;
+NET "ADCA_0_n" LOC = "R7" ;
+NET "ADCB_2_p" LOC = "U7" ;
+NET "ADCB_2_n" LOC = "U8" ;
+NET "ADCB_0_p" LOC = "AA2" ;
+NET "ADCB_0_n" LOC = "AA3" ;
+NET "ADCB_4_p" LOC = "AE1" ;
+NET "ADCB_4_n" LOC = "AE2" ;
+NET "ADCB_6_p" LOC = "W1" ;
+NET "ADCB_6_n" LOC = "W2" ;
+NET "ADCB_8_p" LOC = "U3" ;
+NET "ADCB_8_n" LOC = "V4" ;
+NET "ADCB_10_p" LOC = "J1" ;
+NET "ADCB_10_n" LOC = "K1" ;
+NET "ADCB_12_p" LOC = "J3" ;
+NET "ADCB_12_n" LOC = "J2" ;
+
+## DAC
+NET "DAC_LOCK" LOC = "P4" ;
+NET "DACA<0>" LOC = "P8" ;
+NET "DACA<1>" LOC = "P9" ;
+NET "DACA<2>" LOC = "R5" ;
+NET "DACA<3>" LOC = "R6" ;
+NET "DACA<4>" LOC = "P7" ;
+NET "DACA<5>" LOC = "P6" ;
+NET "DACA<6>" LOC = "T3" ;
+NET "DACA<7>" LOC = "T4" ;
+NET "DACA<8>" LOC = "R3" ;
+NET "DACA<9>" LOC = "R4" ;
+NET "DACA<10>" LOC = "R2" ;
+NET "DACA<11>" LOC = "N1" ;
+NET "DACA<12>" LOC = "N2" ;
+NET "DACA<13>" LOC = "N5" ;
+NET "DACA<14>" LOC = "N4" ;
+NET "DACA<15>" LOC = "M2" ;
+NET "DACB<0>" LOC = "M5" ;
+NET "DACB<1>" LOC = "M6" ;
+NET "DACB<2>" LOC = "M4" ;
+NET "DACB<3>" LOC = "M3" ;
+NET "DACB<4>" LOC = "M8" ;
+NET "DACB<5>" LOC = "M7" ;
+NET "DACB<6>" LOC = "L4" ;
+NET "DACB<7>" LOC = "L3" ;
+NET "DACB<8>" LOC = "K3" ;
+NET "DACB<9>" LOC = "K2" ;
+NET "DACB<10>" LOC = "K5" ;
+NET "DACB<11>" LOC = "K4" ;
+NET "DACB<12>" LOC = "M10" ;
+NET "DACB<13>" LOC = "M9" ;
+NET "DACB<14>" LOC = "J5" ;
+NET "DACB<15>" LOC = "J4" ;
+
+## TX DB GPIO
NET "io_tx<15>" LOC = "K6" ;
NET "io_tx<14>" LOC = "L7" ;
NET "io_tx<13>" LOC = "H2" ;
NET "io_tx<12>" LOC = "H1" ;
NET "io_tx<11>" LOC = "L10" ;
NET "io_tx<10>" LOC = "L9" ;
-NET "io_tx<09>" LOC = "G3" ;
-NET "io_tx<08>" LOC = "F3" ;
-NET "io_tx<07>" LOC = "K7" ;
-NET "io_tx<06>" LOC = "J6" ;
-NET "io_tx<05>" LOC = "E1" ;
-NET "io_tx<04>" LOC = "F2" ;
-NET "io_tx<03>" LOC = "J7" ;
-NET "io_tx<02>" LOC = "H6" ;
-NET "io_tx<01>" LOC = "F5" ;
-NET "io_tx<00>" LOC = "G4" ;
-NET "MOSI_RX_ADC" LOC = "E3" ;
-NET "SCLK_RX_ADC" LOC = "F4" ;
-NET "SEN_RX_ADC" LOC = "D3" ;
-NET "SCLK_RX_DAC" LOC = "E4" ;
-NET "SEN_RX_DAC" LOC = "K9" ;
-NET "MOSI_RX_DAC" LOC = "K8" ;
-NET "SCLK_RX_DB" LOC = "G6" ;
-NET "MOSI_RX_DB" LOC = "H7" ;
-NET "SEN_RX_DB" LOC = "B2" ;
-NET "SCLK_ADC" LOC = "B1" ;
-NET "MOSI_ADC" LOC = "J8" ;
-NET "SEN_ADC" LOC = "J9" ;
-NET "ADCB_4_5_p" LOC = "AE1" ;
-NET "ADCB_4_5_n" LOC = "AE2" ;
-NET "ADCB_6_7_p" LOC = "W1" ;
-NET "ADCB_6_7_n" LOC = "W2" ;
-NET "ADCB_8_9_p" LOC = "U3" ;
-NET "ADCB_8_9_n" LOC = "V4" ;
-NET "ADCB_10_11_p" LOC = "J1" ;
-NET "ADCB_10_11_n" LOC = "K1" ;
-NET "ADCB_12_13_p" LOC = "J3" ;
-NET "ADCB_12_13_n" LOC = "J2" ;
-NET "MISO_RX_DB" LOC = "H4" ;
-NET "MISO_RX_ADC" LOC = "C1" ;
-NET "MISO_TX_DB" LOC = "AA5" ;
-NET "MISO_DAC" LOC = "Y3" ;
-NET "MISO_TX_ADC" LOC = "G1" ;
-NET "io_rx<02>" LOC = "R10" ;
-NET "io_rx<01>" LOC = "R1" ;
-NET "io_rx<00>" LOC = "M1" ;
-NET "exp_user_out_p" LOC = "AF14" ;
-NET "exp_user_out_n" LOC = "AE14" ;
-NET "exp_time_out_p" LOC = "Y14" ;
-NET "exp_time_out_n" LOC = "AA14" ;
-NET "CLK_FPGA_P" LOC = "AA13" ;
-NET "CLK_FPGA_N" LOC = "Y13" ;
+NET "io_tx<9>" LOC = "G3" ;
+NET "io_tx<8>" LOC = "F3" ;
+NET "io_tx<7>" LOC = "K7" ;
+NET "io_tx<6>" LOC = "J6" ;
+NET "io_tx<5>" LOC = "E1" ;
+NET "io_tx<4>" LOC = "F2" ;
+NET "io_tx<3>" LOC = "J7" ;
+NET "io_tx<2>" LOC = "H6" ;
+NET "io_tx<1>" LOC = "F5" ;
+NET "io_tx<0>" LOC = "G4" ;
+
+## RX DB GPIO
+NET "io_rx<15>" LOC = "AD1" ;
+NET "io_rx<14>" LOC = "AD2" ;
+NET "io_rx<13>" LOC = "AC2" ;
+NET "io_rx<12>" LOC = "AC3" ;
+NET "io_rx<11>" LOC = "W7" ;
+NET "io_rx<10>" LOC = "W6" ;
+NET "io_rx<9>" LOC = "U9" ;
+NET "io_rx<8>" LOC = "V8" ;
+NET "io_rx<7>" LOC = "AB1" ;
+NET "io_rx<6>" LOC = "AC1" ;
+NET "io_rx<5>" LOC = "V7" ;
+NET "io_rx<4>" LOC = "V6" ;
+NET "io_rx<3>" LOC = "Y5" ;
+NET "io_rx<2>" LOC = "R10" ;
+NET "io_rx<1>" LOC = "R1" ;
+NET "io_rx<0>" LOC = "M1" ;
+
+## MISC
NET "leds<5>" LOC = "AF25" ;
NET "leds<4>" LOC = "AE25" ;
NET "leds<3>" LOC = "AF23" ;
NET "leds<2>" LOC = "AE23" ;
NET "leds<1>" LOC = "AB18" ;
-NET "SEN_CLK" LOC = "AA18" ;
-NET "MOSI_CLK" LOC = "W17" ;
-NET "SCLK_CLK" LOC = "V17" ;
-NET "CLK_STATUS" LOC = "AD22" ;
-NET "CLK_FUNC" LOC = "AC21" ;
-NET "clk_sel<0>" LOC = "AE21" ;
-NET "clk_sel<1>" LOC = "AD21" ;
-NET "clk_en<1>" LOC = "AA17" ;
-NET "clk_en<0>" LOC = "Y17" ;
-NET "SDA" LOC = "V16" ;
-NET "SCL" LOC = "U16" ;
-NET "TXD3" LOC = "AD20" ;
-NET "TXD2" LOC = "AC20" ;
-NET "TXD1" LOC = "AD19" ;
-NET "debug<00>" LOC = "AC19" ;
-NET "debug<01>" LOC = "AF20" ;
-NET "debug<02>" LOC = "AE20" ;
-NET "debug<03>" LOC = "AC16" ;
-NET "debug<04>" LOC = "AB16" ;
-NET "debug<05>" LOC = "AF19" ;
-NET "debug<06>" LOC = "AE19" ;
-NET "debug<07>" LOC = "V15" ;
-NET "debug<08>" LOC = "U15" ;
-NET "debug<09>" LOC = "AE17" ;
+NET "FPGA_RESET" LOC = "K24" ;
+
+## Debug
+NET "debug_clk<0>" LOC = "AA10" ;
+NET "debug_clk<1>" LOC = "AD11" ;
+NET "debug<0>" LOC = "AC19" ;
+NET "debug<1>" LOC = "AF20" ;
+NET "debug<2>" LOC = "AE20" ;
+NET "debug<3>" LOC = "AC16" ;
+NET "debug<4>" LOC = "AB16" ;
+NET "debug<5>" LOC = "AF19" ;
+NET "debug<6>" LOC = "AE19" ;
+NET "debug<7>" LOC = "V15" ;
+NET "debug<8>" LOC = "U15" ;
+NET "debug<9>" LOC = "AE17" ;
NET "debug<10>" LOC = "AD17" ;
NET "debug<11>" LOC = "V14" ;
NET "debug<12>" LOC = "W15" ;
NET "debug<13>" LOC = "AC15" ;
NET "debug<14>" LOC = "AD14" ;
NET "debug<15>" LOC = "AC14" ;
-NET "debug_clk<1>" LOC = "AD11" ;
NET "debug<16>" LOC = "AC11" ;
NET "debug<17>" LOC = "AB12" ;
NET "debug<18>" LOC = "AC12" ;
@@ -168,103 +148,183 @@ NET "debug<28>" LOC = "AB7" ;
NET "debug<29>" LOC = "V11" ;
NET "debug<30>" LOC = "U11" ;
NET "debug<31>" LOC = "Y10" ;
-NET "debug_clk<0>" LOC = "AA10" ;
+
+## UARTS
+NET "TXD<3>" LOC = "AD20" ;
+NET "TXD<2>" LOC = "AC20" ;
+NET "TXD<1>" LOC = "AD19" ;
+NET "RXD<3>" LOC = "AF17" ;
+NET "RXD<2>" LOC = "AF15" ;
+NET "RXD<1>" LOC = "AD12" ;
+
+## AD9510
+NET "CLK_STATUS" LOC = "AD22" ;
+NET "CLK_FUNC" LOC = "AC21" ;
+NET "clk_sel<0>" LOC = "AE21" ;
+NET "clk_sel<1>" LOC = "AD21" ;
+NET "clk_en<1>" LOC = "AA17" ;
+NET "clk_en<0>" LOC = "Y17" ;
+
+## I2C
+NET "SDA" LOC = "V16" ;
+NET "SCL" LOC = "U16" ;
+
+## Timing
+NET "PPS_IN" LOC = "AB6" ;
+NET "PPS2_IN" LOC = "AA20" ;
+
+## SPI
+NET "SEN_CLK" LOC = "AA18" ;
+NET "MOSI_CLK" LOC = "W17" ;
+NET "SCLK_CLK" LOC = "V17" ;
+NET "MISO_CLK" LOC = "AC10" ;
+
NET "SEN_DAC" LOC = "AE7" ;
NET "SCLK_DAC" LOC = "AF5" ;
NET "MOSI_DAC" LOC = "AE6" ;
+NET "MISO_DAC" LOC = "Y3" ;
+
+NET "SCLK_ADC" LOC = "B1" ;
+NET "MOSI_ADC" LOC = "J8" ;
+NET "SEN_ADC" LOC = "J9" ;
+
NET "MOSI_TX_ADC" LOC = "V10" ;
NET "SEN_TX_ADC" LOC = "W10" ;
NET "SCLK_TX_ADC" LOC = "AC6" ;
+NET "MISO_TX_ADC" LOC = "G1" ;
+
NET "MOSI_TX_DAC" LOC = "AD6" ;
NET "SEN_TX_DAC" LOC = "AE4" ;
NET "SCLK_TX_DAC" LOC = "AF4" ;
+
NET "SCLK_TX_DB" LOC = "AE3" ;
NET "MOSI_TX_DB" LOC = "AF3" ;
NET "SEN_TX_DB" LOC = "W9" ;
-NET "RXD3" LOC = "AF17" ;
-NET "RXD2" LOC = "AF15" ;
-NET "RXD1" LOC = "AD12" ;
-NET "MISO_CLK" LOC = "AC10" ;
-NET "PPS_IN" LOC = "AB6" ;
-NET "PPS2_IN" LOC = "AA20" ;
-NET "ser_rx_clk" LOC = "P18" ;
-NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK
+NET "MISO_TX_DB" LOC = "AA5" ;
+
+NET "MOSI_RX_ADC" LOC = "E3" ;
+NET "SCLK_RX_ADC" LOC = "F4" ;
+NET "SEN_RX_ADC" LOC = "D3" ;
+NET "MISO_RX_ADC" LOC = "C1" ;
+
+NET "SCLK_RX_DAC" LOC = "E4" ;
+NET "SEN_RX_DAC" LOC = "K9" ;
+NET "MOSI_RX_DAC" LOC = "K8" ;
+
+NET "SCLK_RX_DB" LOC = "G6" ;
+NET "MOSI_RX_DB" LOC = "H7" ;
+NET "SEN_RX_DB" LOC = "B2" ;
+NET "MISO_RX_DB" LOC = "H4" ;
+
+## ETH PHY
NET "CLK_TO_MAC" LOC = "P26" ;
-NET "GMII_TX_CLK" LOC = "P25" ;
-NET "GMII_RX_CLK" LOC = "P21" ;
-NET "ETH_LED" LOC = "H20" ;
-NET "GMII_TXD7" LOC = "G21" ;
-NET "GMII_TXD6" LOC = "C26" ;
-NET "GMII_TXD5" LOC = "C25" ;
-NET "GMII_TXD4" LOC = "J21" ;
-NET "GMII_TXD3" LOC = "H21" ;
-NET "GMII_TXD2" LOC = "D25" ;
-NET "GMII_TXD1" LOC = "D24" ;
-NET "GMII_TXD0" LOC = "E26" ;
+
+NET "GMII_TXD<7>" LOC = "G21" ;
+NET "GMII_TXD<6>" LOC = "C26" ;
+NET "GMII_TXD<5>" LOC = "C25" ;
+NET "GMII_TXD<4>" LOC = "J21" ;
+NET "GMII_TXD<3>" LOC = "H21" ;
+NET "GMII_TXD<2>" LOC = "D25" ;
+NET "GMII_TXD<1>" LOC = "D24" ;
+NET "GMII_TXD<0>" LOC = "E26" ;
NET "GMII_TX_EN" LOC = "D26" ;
NET "GMII_TX_ER" LOC = "J19" ;
NET "GMII_GTX_CLK" LOC = "J20" ;
-NET "GMII_RXD7" LOC = "G22" ;
-NET "GMII_RXD6" LOC = "K19" ;
-NET "GMII_RXD5" LOC = "K18" ;
-NET "GMII_RXD4" LOC = "E24" ;
-NET "GMII_RXD3" LOC = "F23" ;
-NET "GMII_RXD2" LOC = "L18" ;
-NET "GMII_RXD1" LOC = "L17" ;
-NET "GMII_RXD0" LOC = "F25" ;
+NET "GMII_TX_CLK" LOC = "P25" ;
+
+NET "GMII_RX_CLK" LOC = "P21" ;
+NET "GMII_RXD<7>" LOC = "G22" ;
+NET "GMII_RXD<6>" LOC = "K19" ;
+NET "GMII_RXD<5>" LOC = "K18" ;
+NET "GMII_RXD<4>" LOC = "E24" ;
+NET "GMII_RXD<3>" LOC = "F23" ;
+NET "GMII_RXD<2>" LOC = "L18" ;
+NET "GMII_RXD<1>" LOC = "L17" ;
+NET "GMII_RXD<0>" LOC = "F25" ;
NET "GMII_RX_DV" LOC = "F24" ;
NET "GMII_RX_ER" LOC = "L20" ;
NET "GMII_CRS" LOC = "K20" ;
NET "GMII_COL" LOC = "G23" ;
+
NET "PHY_INTn" LOC = "L22" ;
NET "MDIO" LOC = "K21" ;
NET "MDC" LOC = "J23" ;
-NET "PHY_RESET" LOC = "J22" ;
+NET "PHY_RESETn" LOC = "J22" ;
+NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+
+## MIMO Interface
+NET "exp_time_out_p" LOC = "Y14" ;
+NET "exp_time_out_n" LOC = "AA14" ;
NET "exp_time_in_p" LOC = "N18" ;
NET "exp_time_in_n" LOC = "N17" ;
+NET "exp_user_out_p" LOC = "AF14" ;
+NET "exp_user_out_n" LOC = "AE14" ;
NET "exp_user_in_p" LOC = "L24" ;
NET "exp_user_in_n" LOC = "M23" ;
+
+## SERDES
+NET "ser_enable" LOC = "R20" ;
NET "ser_prbsen" LOC = "U23" ;
NET "ser_loopen" LOC = "R19" ;
-NET "ser_enable" LOC = "R20" ;
+NET "ser_rx_en" LOC = "Y21" ;
+NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK
NET "ser_t<15>" LOC = "V23" ;
NET "ser_t<14>" LOC = "U22" ;
NET "ser_t<13>" LOC = "V24" ;
NET "ser_t<12>" LOC = "V25" ;
NET "ser_t<11>" LOC = "W23" ;
NET "ser_t<10>" LOC = "V22" ;
-NET "ser_t<09>" LOC = "T18" ;
-NET "ser_t<08>" LOC = "T17" ;
-NET "ser_t<07>" LOC = "Y24" ;
-NET "ser_t<06>" LOC = "Y25" ;
-NET "ser_t<05>" LOC = "U21" ;
-NET "ser_t<04>" LOC = "T20" ;
-NET "ser_t<03>" LOC = "Y22" ;
-NET "ser_t<02>" LOC = "Y23" ;
-NET "ser_t<01>" LOC = "U19" ;
-NET "ser_t<00>" LOC = "U18" ;
+NET "ser_t<9>" LOC = "T18" ;
+NET "ser_t<8>" LOC = "T17" ;
+NET "ser_t<7>" LOC = "Y24" ;
+NET "ser_t<6>" LOC = "Y25" ;
+NET "ser_t<5>" LOC = "U21" ;
+NET "ser_t<4>" LOC = "T20" ;
+NET "ser_t<3>" LOC = "Y22" ;
+NET "ser_t<2>" LOC = "Y23" ;
+NET "ser_t<1>" LOC = "U19" ;
+NET "ser_t<0>" LOC = "U18" ;
NET "ser_tkmsb" LOC = "AA24" ;
NET "ser_tklsb" LOC = "AA25" ;
+NET "ser_rx_clk" LOC = "P18" ;
NET "ser_r<15>" LOC = "V21" ;
NET "ser_r<14>" LOC = "U20" ;
NET "ser_r<13>" LOC = "AA22" ;
NET "ser_r<12>" LOC = "AA23" ;
NET "ser_r<11>" LOC = "V18" ;
NET "ser_r<10>" LOC = "V19" ;
-NET "ser_r<09>" LOC = "AB23" ;
-NET "ser_r<08>" LOC = "AC26" ;
-NET "ser_r<07>" LOC = "AB26" ;
-NET "ser_r<06>" LOC = "AD26" ;
-NET "ser_r<05>" LOC = "AC25" ;
-NET "ser_r<04>" LOC = "W20" ;
-NET "ser_r<03>" LOC = "W21" ;
-NET "ser_r<02>" LOC = "AC23" ;
-NET "ser_r<01>" LOC = "AC24" ;
-NET "ser_r<00>" LOC = "AE26" ;
+NET "ser_r<9>" LOC = "AB23" ;
+NET "ser_r<8>" LOC = "AC26" ;
+NET "ser_r<7>" LOC = "AB26" ;
+NET "ser_r<6>" LOC = "AD26" ;
+NET "ser_r<5>" LOC = "AC25" ;
+NET "ser_r<4>" LOC = "W20" ;
+NET "ser_r<3>" LOC = "W21" ;
+NET "ser_r<2>" LOC = "AC23" ;
+NET "ser_r<1>" LOC = "AC24" ;
+NET "ser_r<0>" LOC = "AE26" ;
NET "ser_rkmsb" LOC = "AD25" ;
NET "ser_rklsb" LOC = "Y20" ;
-NET "ser_rx_en" LOC = "Y21" ;
-NET "FPGA_RESET" LOC = "K24" ;
+
+## SRAM
+NET "RAM_D<35>" LOC = "K16" ;
+NET "RAM_D<34>" LOC = "D20" ;
+NET "RAM_D<33>" LOC = "C20" ;
+NET "RAM_D<32>" LOC = "E21" ;
+NET "RAM_D<31>" LOC = "D21" ;
+NET "RAM_D<30>" LOC = "C21" ;
+NET "RAM_D<29>" LOC = "B21" ;
+NET "RAM_D<28>" LOC = "H17" ;
+NET "RAM_D<27>" LOC = "G17" ;
+NET "RAM_D<26>" LOC = "B23" ;
+NET "RAM_D<25>" LOC = "A22" ;
+NET "RAM_D<24>" LOC = "D23" ;
+NET "RAM_D<23>" LOC = "C23" ;
+NET "RAM_D<22>" LOC = "D22" ;
+NET "RAM_D<21>" LOC = "C22" ;
+NET "RAM_D<20>" LOC = "F19" ;
+NET "RAM_D<19>" LOC = "G20" ;
+NET "RAM_D<18>" LOC = "F20" ;
NET "RAM_D<17>" LOC = "F7" ;
NET "RAM_D<16>" LOC = "E7" ;
NET "RAM_D<15>" LOC = "G9" ;
@@ -273,36 +333,26 @@ NET "RAM_D<13>" LOC = "G10" ;
NET "RAM_D<12>" LOC = "H10" ;
NET "RAM_D<11>" LOC = "A4" ;
NET "RAM_D<10>" LOC = "B4" ;
-NET "RAM_D<09>" LOC = "C5" ;
-NET "RAM_D<08>" LOC = "D6" ;
-NET "RAM_D<07>" LOC = "J11" ;
-NET "RAM_D<06>" LOC = "K11" ;
-NET "RAM_D<05>" LOC = "B7" ;
-NET "RAM_D<04>" LOC = "C7" ;
-NET "RAM_D<03>" LOC = "B6" ;
-NET "RAM_D<02>" LOC = "C6" ;
-NET "RAM_D<01>" LOC = "C8" ;
-NET "RAM_D<00>" LOC = "D8" ;
-NET "RAM_ZZ" LOC = "J12" ;
-NET "RAM_BWn<3>" LOC = "D9" ;
-NET "RAM_BWn<2>" LOC = "A9" ;
-NET "RAM_BWn<1>" LOC = "B9" ;
-NET "RAM_BWn<0>" LOC = "G12" ;
-NET "RAM_LDn" LOC = "H12" ;
-NET "RAM_OEn" LOC = "C10" ;
-NET "RAM_WEn" LOC = "D10" ;
-NET "RAM_CLK" LOC = "A10" ;
-NET "RAM_CENn" LOC = "B10" ;
-NET "RAM_A<00>" LOC = "C11" ;
-NET "RAM_A<01>" LOC = "E12" ;
-NET "RAM_A<02>" LOC = "F12" ;
-NET "RAM_A<03>" LOC = "D13" ;
-NET "RAM_A<04>" LOC = "C12" ;
-NET "RAM_A<05>" LOC = "A12" ;
-NET "RAM_A<06>" LOC = "B12" ;
-NET "RAM_A<07>" LOC = "E14" ;
-NET "RAM_A<08>" LOC = "F14" ;
-NET "RAM_A<09>" LOC = "B15" ;
+NET "RAM_D<9>" LOC = "C5" ;
+NET "RAM_D<8>" LOC = "D6" ;
+NET "RAM_D<7>" LOC = "J11" ;
+NET "RAM_D<6>" LOC = "K11" ;
+NET "RAM_D<5>" LOC = "B7" ;
+NET "RAM_D<4>" LOC = "C7" ;
+NET "RAM_D<3>" LOC = "B6" ;
+NET "RAM_D<2>" LOC = "C6" ;
+NET "RAM_D<1>" LOC = "C8" ;
+NET "RAM_D<0>" LOC = "D8" ;
+NET "RAM_A<0>" LOC = "C11" ;
+NET "RAM_A<1>" LOC = "E12" ;
+NET "RAM_A<2>" LOC = "F12" ;
+NET "RAM_A<3>" LOC = "D13" ;
+NET "RAM_A<4>" LOC = "C12" ;
+NET "RAM_A<5>" LOC = "A12" ;
+NET "RAM_A<6>" LOC = "B12" ;
+NET "RAM_A<7>" LOC = "E14" ;
+NET "RAM_A<8>" LOC = "F14" ;
+NET "RAM_A<9>" LOC = "B15" ;
NET "RAM_A<10>" LOC = "A15" ;
NET "RAM_A<11>" LOC = "D16" ;
NET "RAM_A<12>" LOC = "C15" ;
@@ -314,41 +364,53 @@ NET "RAM_A<17>" LOC = "B17" ;
NET "RAM_A<18>" LOC = "B18" ;
NET "RAM_A<19>" LOC = "A18" ;
NET "RAM_A<20>" LOC = "D18" ;
-NET "RAM_D<35>" LOC = "K16" ;
-NET "RAM_D<34>" LOC = "D20" ;
-NET "RAM_D<33>" LOC = "C20" ;
-NET "RAM_D<32>" LOC = "E21" ;
-NET "RAM_D<31>" LOC = "D21" ;
-NET "RAM_D<30>" LOC = "C21" ;
-NET "RAM_D<29>" LOC = "B21" ;
-NET "RAM_D<28>" LOC = "H17" ;
-NET "RAM_D<27>" LOC = "G17" ;
-NET "RAM_D<26>" LOC = "B23" ;
-NET "RAM_D<25>" LOC = "A22" ;
-NET "RAM_D<24>" LOC = "D23" ;
-NET "RAM_D<23>" LOC = "C23" ;
-NET "RAM_D<22>" LOC = "D22" ;
-NET "RAM_D<21>" LOC = "C22" ;
-NET "RAM_D<20>" LOC = "F19" ;
-NET "RAM_D<19>" LOC = "G20" ;
-NET "RAM_D<18>" LOC = "F20" ;
-#NET "unnamed_net20" LOC = "V20" ; # SUSPEND
-NET "PROG_B" LOC = "A2" ;
-NET "PUDC_B" LOC = "G8" ;
-NET "DONE" LOC = "AB21" ;
+NET "RAM_BWn<3>" LOC = "D9" ;
+NET "RAM_BWn<2>" LOC = "A9" ;
+NET "RAM_BWn<1>" LOC = "B9" ;
+NET "RAM_BWn<0>" LOC = "G12" ;
+NET "RAM_ZZ" LOC = "J12" ;
+NET "RAM_LDn" LOC = "H12" ;
+NET "RAM_OEn" LOC = "C10" ;
+NET "RAM_WEn" LOC = "D10" ;
+NET "RAM_CENn" LOC = "B10" ;
+NET "RAM_CLK" LOC = "A10" ;
+
+## SPI Flash
NET "flash_miso" LOC = "AF24" ;
NET "flash_clk" LOC = "AE24" ;
-NET "INIT_B" LOC = "AA15" ;
NET "flash_mosi" LOC = "AB15" ;
+NET "flash_cs" LOC = "AA7" ;
+
+## MISC FPGA, unused for now
+#NET "PROG_B" LOC = "A2" ;
+#NET "PUDC_B" LOC = "G8" ;
+#NET "DONE" LOC = "AB21" ;
+#NET "INIT_B" LOC = "AA15" ;
+
+
#NET "unnamed_net19" LOC = "AE9" ; # VS1
#NET "unnamed_net18" LOC = "AF9" ; # VS0
#NET "unnamed_net17" LOC = "AA12" ; # VS2
#NET "unnamed_net16" LOC = "Y7" ; # M2
-NET "flash_cs" LOC = "AA7" ;
#NET "unnamed_net15" LOC = "AC4" ; # M1
#NET "unnamed_net14" LOC = "AD4" ; # M0
#NET "unnamed_net13" LOC = "D4" ; # TMS
#NET "unnamed_net12" LOC = "E23" ; # TDO
#NET "unnamed_net11" LOC = "G7" ; # TDI
#NET "unnamed_net10" LOC = "A25" ; # TCK
+#NET "unnamed_net20" LOC = "V20" ; # SUSPEND
+
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index e95445867..3641ce962 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -3,46 +3,93 @@
module u2plus
(
+ input CLK_FPGA_P, input CLK_FPGA_N, // Diff
+
+ // ADC
+ input ADC_clkout_p, input ADC_clkout_n,
+ input ADCA_12_p, input ADCA_12_n,
+ input ADCA_10_p, input ADCA_10_n,
+ input ADCA_8_p, input ADCA_8_n,
+ input ADCA_6_p, input ADCA_6_n,
+ input ADCA_4_p, input ADCA_4_n,
+ input ADCA_2_p, input ADCA_2_n,
+ input ADCA_0_p, input ADCA_0_n,
+ input ADCB_12_p, input ADCB_12_n,
+ input ADCB_10_p, input ADCB_10_n,
+ input ADCB_8_p, input ADCB_8_n,
+ input ADCB_6_p, input ADCB_6_n,
+ input ADCB_4_p, input ADCB_4_n,
+ input ADCB_2_p, input ADCB_2_n,
+ input ADCB_0_p, input ADCB_0_n,
+
+ // DAC
+ output reg [15:0] DACA,
+ output reg [15:0] DACB,
+ input DAC_LOCK, // unused for now
+
+ // DB IO Pins
+ inout [15:0] io_tx,
+ inout [15:0] io_rx,
+
// Misc, debug
- output [4:0] leds, // LED4 is shared w/INIT_B
- input [3:0] dipsw,
- output [31:0] debug,
+ output [5:1] leds, // LED4 is shared w/INIT_B
+ input FPGA_RESET,
output [1:0] debug_clk,
- output uart_tx_o,
- input uart_rx_i,
-
- // Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
+ output [31:0] debug,
+ output [3:1] TXD, input [3:1] RXD, // UARTs
+ //input [3:0] dipsw, // Forgot DIP Switches...
- // GMII
- // GMII-CTRL
- input GMII_COL,
- input GMII_CRS,
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input CLK_FUNC, // FIXME is an input to control the 9510
+ input CLK_STATUS,
+
+ inout SCL, inout SDA, // I2C
+
+ // PPS
+ input PPS_IN, input PPS2_IN,
+
+ // SPI
+ output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK,
+ output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC,
+ output SEN_ADC, output SCLK_ADC, output MOSI_ADC,
+ output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,
+ output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC,
+ output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC,
+ output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
+ output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC,
+ output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC,
+
+ // GigE PHY
+ input CLK_TO_MAC,
- // GMII-TX
output reg [7:0] GMII_TXD,
output reg GMII_TX_EN,
output reg GMII_TX_ER,
output GMII_GTX_CLK,
input GMII_TX_CLK, // 100mbps clk
- // GMII-RX
- input [7:0] GMII_RXD,
input GMII_RX_CLK,
+ input [7:0] GMII_RXD,
input GMII_RX_DV,
input GMII_RX_ER,
+ input GMII_COL,
+ input GMII_CRS,
- // GMII-Management
+ input PHY_INTn, // open drain
inout MDIO,
output MDC,
- input PHY_INTn, // open drain
output PHY_RESETn,
- input PHY_CLK, // possibly use on-board osc
- input clk_to_mac,
- output eth_led,
+ output ETH_LED,
+
+// input POR,
+
+ // Expansion
+ input exp_time_in_p, input exp_time_in_n, // Diff
+ output exp_time_out_p, output exp_time_out_n, // Diff
+ input exp_user_in_p, input exp_user_in_n, // Diff
+ output exp_user_out_p, output exp_user_out_n, // Diff
// SERDES
output ser_enable,
@@ -59,75 +106,18 @@ module u2plus
input [15:0] ser_r,
input ser_rklsb,
input ser_rkmsb,
-
- // ADC
- input [13:0] adc_a,
- input adc_ovf_a,
- output adc_oen_a,
- output adc_pdn_a,
-
- input [13:0] adc_b,
- input adc_ovf_b,
- output adc_oen_b,
- output adc_pdn_b,
-
- // DAC
- output [15:0] dac_a,
- output [15:0] dac_b,
- input dac_lock, // unused for now
-
- // I2C
- inout SCL,
- inout SDA,
-
- // Clock Gen Control
- output [1:0] clk_en,
- output [1:0] clk_sel,
- input clk_func, // FIXME is an input to control the 9510
- input clk_status,
- // Clocks
- input clk_fpga_p, // Diff
- input clk_fpga_n, // Diff
- input pps_in,
- input POR,
+ // SRAM
+ inout [35:0] RAM_D,
+ output [20:0] RAM_A,
+ output [3:0] RAM_BWn,
+ output RAM_ZZ,
+ output RAM_LDn,
+ output RAM_OEn,
+ output RAM_WEn,
+ output RAM_CENn,
+ output RAM_CLK,
- // AD9510 SPI
- output sclk,
- output sen_clk,
- output sdi,
- input sdo,
-
- // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
- output sen_dac,
- output sen_tx_db,
- output sen_tx_adc,
- output sen_tx_dac,
- output mosi_tx,
- input miso_dac,
- input miso_tx_db,
- input miso_tx_adc,
- output sclk_tx,
-
- // RX side SPI
- output sen_rx_db,
- output sclk_rx_db,
- input sdo_rx_db,
- output sdi_rx_db,
-
- output sen_rx_adc,
- output sclk_rx_adc,
- input sdo_rx_adc,
- output sdi_rx_adc,
-
- output sen_rx_dac,
- output sclk_rx_dac,
- output sdi_rx_dac,
-
- // DB IO Pins
- inout [15:0] io_tx,
- inout [15:0] io_rx,
-
// SPI Flash
output flash_cs,
output flash_clk,
@@ -135,38 +125,60 @@ module u2plus
input flash_miso
);
+ wire CLK_TO_MAC_int, CLK_TO_MAC_int2;
+ IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC));
+ BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int));
+
// FPGA-specific pins connections
- wire aux_clk = PHY_CLK;
-
wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
- wire exp_pps_in;
- IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+ wire exp_time_in;
+ IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+ defparam exp_time_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_time_out;
+ OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+ defparam exp_time_out_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_user_in;
+ IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n));
+ defparam exp_user_in_pin.IOSTANDARD = "LVDS_25";
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+ wire exp_user_out;
+ OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out));
+ defparam exp_user_out_pin.IOSTANDARD = "LVDS_25";
reg [5:0] clock_ready_d;
- always @(posedge aux_clk)
+ always @(posedge clk_fpga)
clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
-
wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
- wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
-
- wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
- assign adc_oen_a = ~adc_oe_a;
- assign adc_oen_b = ~adc_oe_b;
- assign adc_pdn_a = ~adc_on_a;
- assign adc_pdn_b = ~adc_on_b;
-
+
+`ifdef LVDS
+ wire [13:0] adc_a, adc_b;
+ capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds
+ (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n),
+ .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p},
+ {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}),
+ .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n},
+ {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}),
+ .out({adc_a,adc_b}));
+`else
+ reg [13:0] adc_a, adc_b;
+ always @(posedge dsp_clk)
+ begin
+ adc_a <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n,
+ ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n };
+ adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n,
+ ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n };
+ end
+`endif // !`ifdef LVDS
+
// Handle Clocks
DCM DCM_INST (.CLKFB(dsp_clk),
- .CLKIN(clk_muxed),
+ .CLKIN(clk_fpga),
.DSSEN(0),
.PSCLK(0),
.PSEN(0),
@@ -207,23 +219,26 @@ module u2plus
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
// LEDs are active low outputs
- wire [4:0] leds_int;
- assign leds = ~leds_int; // drive low to turn on leds
+ wire [5:0] leds_int;
+ assign {leds,ETH_LED} = {6'b111110 ^ leds_int}; // drive low to turn on leds
// SPI
- wire miso, mosi, sclk_int;
- assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-
- assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
- (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
- (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+ wire miso, mosi, sclk;
+ assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0;
+ assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0;
+ assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0;
+ assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0;
+ assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0;
+ assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0;
+ assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0;
+ assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0;
+ assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0;
+
+ assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) |
+ (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) |
+ (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC);
+
wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
wire [7:0] GMII_TXD_unreg;
wire GMII_GTX_CLK_int;
@@ -281,16 +296,22 @@ module u2plus
.S(0) // Synchronous preset input
);
*/
- u2_core u2_core(.dsp_clk (dsp_clk),
+
+ wire [15:0] dac_a_int, dac_b_int;
+
+ always @(negedge dsp_clk) DACA <= dac_a_int;
+ always @(negedge dsp_clk) DACB <= dac_b_int;
+
+ u2plus_core u2p_c(.dsp_clk (dsp_clk),
.wb_clk (wb_clk),
.clock_ready (clock_ready),
- .clk_to_mac (clk_to_mac),
+ .clk_to_mac (CLK_TO_MAC_int2),
.pps_in (pps_in),
.leds (leds_int),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
+ .exp_pps_in (exp_time_in),
+ .exp_pps_out (exp_time_out),
.GMII_COL (GMII_COL),
.GMII_CRS (GMII_CRS),
.GMII_TXD (GMII_TXD_unreg[7:0]),
@@ -306,7 +327,6 @@ module u2plus
.MDC (MDC),
.PHY_INTn (PHY_INTn),
.PHY_RESETn (PHY_RESETn),
- .PHY_CLK (PHY_CLK),
.ser_enable (ser_enable),
.ser_prbsen (ser_prbsen),
.ser_loopen (ser_loopen),
@@ -319,12 +339,6 @@ module u2plus
.ser_r (ser_r_int[15:0]),
.ser_rklsb (ser_rklsb_int),
.ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
.adc_a (adc_a[13:0]),
.adc_ovf_a (adc_ovf_a),
.adc_on_a (adc_on_a),
@@ -333,8 +347,8 @@ module u2plus
.adc_ovf_b (adc_ovf_b),
.adc_on_b (adc_on_b),
.adc_oe_b (adc_oe_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
+ .dac_a (dac_a_int[15:0]),
+ .dac_b (dac_b_int[15:0]),
.scl_pad_i (scl_pad_i),
.scl_pad_o (scl_pad_o),
.scl_pad_oen_o (scl_pad_oen_o),
@@ -345,17 +359,18 @@ module u2plus
.clk_sel (clk_sel[1:0]),
.clk_func (clk_func),
.clk_status (clk_status),
- .sclk (sclk_int),
+ .sclk (sclk),
.mosi (mosi),
.miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
+ .sen_clk (SEN_CLK),
+ .sen_dac (SEN_DAC),
+ .sen_adc (SEN_ADC),
+ .sen_tx_db (SEN_TX_DB),
+ .sen_tx_adc (SEN_TX_ADC),
+ .sen_tx_dac (SEN_TX_DAC),
+ .sen_rx_db (SEN_RX_DB),
+ .sen_rx_adc (SEN_RX_ADC),
+ .sen_rx_dac (SEN_RX_DAC),
.io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]),
.RAM_D (RAM_D),
@@ -366,12 +381,19 @@ module u2plus
.RAM_WEn (RAM_WEn),
.RAM_OEn (RAM_OEn),
.RAM_LDn (RAM_LDn),
- .uart_tx_o (uart_tx_o),
- //.uart_rx_i (uart_rx_i),
- .uart_rx_i (),
+ .uart_tx_o (TXD[3:1]),
+ .uart_rx_i ({1'b1,RXD[3:1]}),
.uart_baud_o (),
.sim_mode (1'b0),
- .clock_divider (2)
+ .clock_divider (2),
+ .button (FPGA_RESET),
+ .spiflash_cs (flash_cs),
+ .spiflash_clk (flash_clk),
+ .spiflash_miso (flash_miso),
+ .spiflash_mosi (flash_mosi)
);
+
+ assign RAM_ZZ = 1;
+ assign RAM_BWn = 4'b1111;
endmodule // u2plus
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
new file mode 100644
index 000000000..ee9d206d8
--- /dev/null
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -0,0 +1,824 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name: u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2plus_core
+ (// Clocks
+ input dsp_clk,
+ input wb_clk,
+ output clock_ready,
+ input clk_to_mac,
+ input pps_in,
+
+ // Misc, debug
+ output [7:0] leds,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in,
+ output exp_pps_out,
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ output [7:0] GMII_TXD,
+ output GMII_TX_EN,
+ output GMII_TX_ER,
+ output GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ inout MDIO,
+ output MDC,
+ input PHY_INTn, // open drain
+ output PHY_RESETn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ output ser_tx_clk,
+ output [15:0] ser_t,
+ output ser_tklsb,
+ output ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ input por,
+ output config_success,
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_on_a,
+ output adc_oe_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_on_b,
+ output adc_oe_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+ // I2C
+ input scl_pad_i,
+ output scl_pad_o,
+ output scl_pad_oen_o,
+ input sda_pad_i,
+ output sda_pad_o,
+ output sda_pad_oen_o,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Generic SPI
+ output sclk,
+ output mosi,
+ input miso,
+ output sen_clk,
+ output sen_dac,
+ output sen_adc,
+ output sen_tx_db,
+ output sen_tx_adc,
+ output sen_tx_dac,
+ output sen_rx_db,
+ output sen_rx_adc,
+ output sen_rx_dac,
+
+ // GPIO to DBoards
+ inout [15:0] io_tx,
+ inout [15:0] io_rx,
+
+ // External RAM
+ inout [35:0] RAM_D,
+ output [20:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
+
+ // Debug stuff
+ output [3:0] uart_tx_o,
+ input [3:0] uart_rx_i,
+ output [3:0] uart_baud_o,
+ input sim_mode,
+ input [3:0] clock_divider,
+ input button,
+
+ output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi
+ );
+
+ localparam SR_BUF_POOL = 64; // Uses 1 reg
+ localparam SR_UDP_SM = 96; // 64 regs
+ localparam SR_RX_DSP = 160; // 16
+ localparam SR_RX_CTRL = 176; // 16
+ localparam SR_TIME64 = 192; // 3
+ localparam SR_SIMTIMER = 198; // 2
+ localparam SR_TX_DSP = 208; // 16
+ localparam SR_TX_CTRL = 224; // 16
+
+ // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
+ // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
+ localparam DSP_TX_FIFOSIZE = 10;
+ localparam DSP_RX_FIFOSIZE = 10;
+ localparam ETH_TX_FIFOSIZE = 10;
+ localparam ETH_RX_FIFOSIZE = 11;
+ localparam SERDES_TX_FIFOSIZE = 9;
+ localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo?
+
+ wire [7:0] set_addr, set_addr_dsp;
+ wire [31:0] set_data, set_data_dsp;
+ wire set_stb, set_stb_dsp;
+
+ wire wb_rst, dsp_rst;
+
+ wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+ wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+ wire proc_int, overrun, underrun;
+ wire [3:0] uart_tx_int, uart_rx_int;
+
+ wire [31:0] debug_gpio_0, debug_gpio_1;
+ wire [31:0] atr_lines;
+
+ wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+ debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+
+ wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+ wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+ wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+
+ wire serdes_link_up;
+ wire epoch;
+ wire [31:0] irq;
+ wire [63:0] vita_time;
+
+ // ///////////////////////////////////////////////////////////////////////////////////////////////
+ // Wishbone Single Master INTERCON
+ localparam dw = 32; // Data bus width
+ localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space
+ localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity.
+
+ wire [dw-1:0] m0_dat_o, m0_dat_i;
+ wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+ s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+ s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+ sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o;
+ wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+ wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+ wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+ wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+ wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+ wire m0_err, m0_rty;
+ wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
+
+ wb_1master #(.decode_w(8),
+ .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM
+ .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool
+ .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI
+ .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C
+ .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO
+ .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback
+ .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC
+ .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K)
+ .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC
+ .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused
+ .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART
+ .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR
+ .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused
+ .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP
+ .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash
+ .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM
+ .dw(dw),.aw(aw),.sw(sw)) wb_1master
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+ .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+ .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+ .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+ .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+ .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+ .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+ .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+ .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+ .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+ .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+ .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+ .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+ .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+ .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+ .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+ .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+ .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+ .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+ .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+ .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+ .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+ .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+ .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+ .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+ .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+ .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+ .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+ .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+ .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+ .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+ .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+ .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+ .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
+
+ //////////////////////////////////////////////////////////////////////////////////////////
+ // Reset Controller
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Processor
+ wire [31:0] if_dat;
+ wire [15:0] if_adr;
+
+ aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+ aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+ // Instruction Wishbone bus to I-RAM
+ .if_adr(if_adr),
+ .if_dat(if_dat),
+ // Data Wishbone bus to system bus fabric
+ .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+ .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+ // Interrupts and exceptions
+ .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+ assign bus_error = m0_err | m0_rty;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
+ // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone
+ // I-port connects directly to processor
+
+ wire [31:0] if_dat_boot, if_dat_main;
+ assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot;
+
+ bootram bootram(.clk(wb_clk), .reset(wb_rst),
+ .if_adr(if_adr[12:0]), .if_data(if_dat_boot),
+ .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+ .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+
+////blinkenlights v0.1
+//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000;
+//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001;
+
+////ICAP test v0.1
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b8080d54_00000000_b8080050;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8080d5c;
+defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401448_31a01468_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f4047c_80000000_b9f400cc;
+defparam bootram.RAM0.INIT_04=256'he8830000_e8601450_80000000_99fc2000_f8601450_b8000044_bc030014_f9e10000;
+defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01460_bc030010_30600000_b0000000_30630004_be24ffec;
+defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001;
+defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01460_f9e10000_3021ffe4;
+defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01464_bc030014_30800000_b0000000_e8601464;
+defparam bootram.RAM0.INIT_09=256'h06463800_20e01468_20c01468_f9e10000_2021ffec_3021001c_b60f0008_e9e10000;
+defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014;
+defparam bootram.RAM0.INIT_0B=256'hb9f40bf0_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f828;
+defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f4014c_20e00000_20c00000_80000000_b9f40d70_80000000;
+defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f40bbc_80000000_b9f40d78;
+defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec;
+defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004;
+defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000;
+defparam bootram.RAM0.INIT_11=256'hb9f402c0_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c;
+defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a00f7c_10b30000_b9f405cc_10d60000_10b30000;
+defparam bootram.RAM0.INIT_13=256'h30a00f7c_bc120040_aa430001_30a00f44_e061001c_10a30000_be520034_16439003;
+defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f40440_b800ffb4_80000000_b9f4044c;
+defparam bootram.RAM0.INIT_15=256'h80000000_b9f40414_b800ff88_80000000_b9f40420_30a00f44_80000000_b9f40b54;
+defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f403f8_30a00f48_80000000_b9f409a0_30a08000_b0000000;
+defparam bootram.RAM0.INIT_17=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fa61001c_f9e10000_3021ffe0;
+defparam bootram.RAM0.INIT_18=256'hb9f40750_80000000_b9f40408_f800200c_80000000_b9f4fef4_f860200c_306000ff;
+defparam bootram.RAM0.INIT_19=256'h30a01048_bc04013c_a4842000_e8803334_80000000_b9f403a4_30a00f80_80000000;
+defparam bootram.RAM0.INIT_1A=256'h30a010ac_bc23010c_80000000_b9f4099c_30a00000_b0000020_80000000_b9f4038c;
+defparam bootram.RAM0.INIT_1B=256'h30a010fc_bc030058_80000000_b9f40930_30a00000_b0000040_80000000_b9f4036c;
+defparam bootram.RAM0.INIT_1C=256'h30c07c00_b9f4070c_30a00000_b0000040_30e08000_b0000000_80000000_b9f4034c;
+defparam bootram.RAM0.INIT_1D=256'he9e10000_80000000_b9f40318_30a01128_80000000_b9f408c0_30a08000_b0000000;
+defparam bootram.RAM0.INIT_1E=256'hb000007f_80000000_b9f402f8_30a01164_30210020_b60f0008_30600001_ea61001c;
+defparam bootram.RAM0.INIT_1F=256'h80000000_b9f402d4_30a00ff0_12630000_be230030_80000000_b9f408bc_30a00000;
+defparam bootram.RAM0.INIT_20=256'hb0000000_30210020_b60f0008_ea61001c_e9e10000_10730000_80000000_b9f4fe1c;
+defparam bootram.RAM0.INIT_21=256'hb9f4082c_30a08000_b0000000_30c07c00_b9f40678_30a00000_b000007f_30e08000;
+defparam bootram.RAM0.INIT_22=256'hb60f0008_30600001_ea61001c_e9e10000_80000000_b9f40284_30a00fb4_80000000;
+defparam bootram.RAM0.INIT_23=256'h80000000_b9f40254_30a00f94_b800feec_80000000_b9f40264_30a01074_30210020;
+defparam bootram.RAM0.INIT_24=256'h80000000_b9f40234_30a00ff0_bc23001c_80000000_b9f40818_30a00000_b000007f;
+defparam bootram.RAM0.INIT_25=256'hb9f405e8_30a00000_b000007f_30e08000_b0000000_b800fe94_80000000_b9f4fd7c;
+defparam bootram.RAM0.INIT_26=256'h80000000_b9f401f4_30a00fb4_80000000_b9f4079c_30a08000_b0000000_30c07c00;
+defparam bootram.RAM0.INIT_27=256'h3021ffdc_80000000_b60f0008_80000000_b9f4fb84_f9e10000_3021ffe4_b800fe5c;
+defparam bootram.RAM0.INIT_28=256'h90630060_80000000_b9f402b0_12c50000_f9e10000_12650000_fac10020_fa61001c;
+defparam bootram.RAM0.INIT_29=256'he9e10000_10760000_f0130000_3273ffff_32730001_be32ffec_aa43000a_f0730000;
+defparam bootram.RAM0.INIT_2A=256'h80000000_b9f4026c_f9e10000_3021ffe4_30210024_b60f0008_eac10020_ea61001c;
+defparam bootram.RAM0.INIT_2B=256'h12650000_e0650000_f9e10000_fa61001c_3021ffe0_3021001c_b60f0008_e9e10000;
+defparam bootram.RAM0.INIT_2C=256'he9e10000_bc25fff0_90a30060_e0730000_32730001_b9f401b8_bc050018_90a30060;
+defparam bootram.RAM0.INIT_2D=256'hb9f40184_f9e10000_fac1001c_3021ffe0_30210020_b60f0008_10600000_ea61001c;
+defparam bootram.RAM0.INIT_2E=256'hf9e10000_3021ffe4_30210020_b60f0008_eac1001c_e9e10000_10760000_12c50000;
+defparam bootram.RAM0.INIT_2F=256'h9404c001_ac870002_94e08001_3021001c_b60f0008_e9e10000_80000000_b9f4013c;
+defparam bootram.RAM0.INIT_30=256'hb0000000_f860200c_80633000_84632000_84c62800_a866ffff_e880f81c_b0000000;
+defparam bootram.RAM0.INIT_31=256'h80000000_b60f0008_9404c001_80843800_ac840002_94808001_a4e70002_f860f81c;
+defparam bootram.RAM0.INIT_32=256'hb0000000_f8a0200c_88a52000_e880f81c_b0000000_9406c001_acc30002_94608001;
+defparam bootram.RAM0.INIT_33=256'h80000000_b60f0008_9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c;
+defparam bootram.RAM0.INIT_34=256'h84632000_84c62800_a866ffff_e880f820_b0000000_9404c001_ac870002_94e08001;
+defparam bootram.RAM0.INIT_35=256'h80843800_ac840002_94808001_a4e70002_f860f820_b0000000_f8602020_80633000;
+defparam bootram.RAM0.INIT_36=256'hb9f40064_80000000_b9f4fe98_f9e10000_3021ffe4_80000000_b60f0008_9404c001;
+defparam bootram.RAM0.INIT_37=256'hb9f40044_f9e10000_3021ffe4_3021001c_b60f0008_10600000_e9e10000_30a0000a;
+defparam bootram.RAM0.INIT_38=256'h3021ffe4_80000000_b60f0008_f0a01454_3021001c_b60f0008_e9e10000_30a0000a;
+defparam bootram.RAM0.INIT_39=256'h3021001c_b60f0008_e9e10000_f8603700_306000d9_30a00001_b9f4ffec_f9e10000;
+defparam bootram.RAM0.INIT_3A=256'hbc03fffc_e8603704_12650000_be120024_aa45000a_f9e10000_fa61001c_3021ffe0;
+defparam bootram.RAM0.INIT_3B=256'hb800ffdc_30a0000d_b9f4ffcc_30210020_b60f0008_ea61001c_e9e10000_fa60370c;
+defparam bootram.RAM0.INIT_3C=256'he8603704_30a0000d_be120024_aa53000a_f9e10000_12650000_fa61001c_3021ffe0;
+defparam bootram.RAM0.INIT_3D=256'h80000000_b9f4ff88_30210020_b60f0008_ea61001c_e9e10000_fa60370c_bc030008;
+defparam bootram.RAM0.INIT_3E=256'h3065ffa9_90a50060_80000000_b60f0008_e8603710_bc03fffc_e8603708_b800ffdc;
+defparam bootram.RAM0.INIT_3F=256'h16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024_16459001_3240005a;
+defparam bootram.RAM1.INIT_00=256'h13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff_3085ffd0_be52000c;
+defparam bootram.RAM1.INIT_01=256'he0790000_fb410030_fb010028_fae10024_fac10020_fa61001c_f9e10000_fb610034;
+defparam bootram.RAM1.INIT_02=256'heac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034_aa43003a_13660000;
+defparam bootram.RAM1.INIT_03=256'he8c01458_30210038_b60f0008_eb610034_eb410030_eb21002c_eb010028_eae10024;
+defparam bootram.RAM1.INIT_04=256'ha4630044_c0662000_a4a300ff_be04001c_90840060_30650001_c085c800_30a00001;
+defparam bootram.RAM1.INIT_05=256'hb9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe_b810ffac_bc23ffe4;
+defparam bootram.RAM1.INIT_06=256'hbe38ff74_93040060_e083000b_10791800_fa7b0004_10739800_12761800_66c30404;
+defparam bootram.RAM1.INIT_07=256'he0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0_e0b90005_30a0fffd;
+defparam bootram.RAM1.INIT_08=256'h12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006_66c3040c_b9f4fed8;
+defparam bootram.RAM1.INIT_09=256'h1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0_e0b90007_fafb0008;
+defparam bootram.RAM1.INIT_0A=256'ha6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000_be130060_f07b0000;
+defparam bootram.RAM1.INIT_0B=256'hd0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000_b9f4fe74_c0b6c800;
+defparam bootram.RAM1.INIT_0C=256'hbe52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001_e8fb0004_ea7b000c;
+defparam bootram.RAM1.INIT_0D=256'h10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000_eadb0008_a74300ff;
+defparam bootram.RAM1.INIT_0E=256'h16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10_107a1800_12c7b000;
+defparam bootram.RAM1.INIT_0F=256'h10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff_a6d600ff_1063c000;
+defparam bootram.RAM1.INIT_10=256'ha1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8_a4630100_e8603b10;
+defparam bootram.RAM1.INIT_11=256'ha46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10_a4a500ff_80884800;
+defparam bootram.RAM1.INIT_12=256'hbc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10_a0840100_f8603b18;
+defparam bootram.RAM1.INIT_13=256'h10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000_b60f0008_e8603b00;
+defparam bootram.RAM1.INIT_14=256'hb60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001_31200400_31000008;
+defparam bootram.RAM1.INIT_15=256'h13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030_3021ffc4_3021001c;
+defparam bootram.RAM1.INIT_16=256'h3060000b_66d60408_f8603b10_f8003b18_30600400_12670000_b9f4ff3c_fae10034;
+defparam bootram.RAM1.INIT_17=256'hf8603b10_30600528_f8803b10_30800428_f8603b18_30600001_fac03b00_f8603b04;
+defparam bootram.RAM1.INIT_18=256'hf8603b10_30600400_3261001c_12e00000_12d30000_be18009c_80000000_b9f4ff00;
+defparam bootram.RAM1.INIT_19=256'he8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8_f8803b10_30800500;
+defparam bootram.RAM1.INIT_1A=256'hbeb20034_16459003_22400010_f8610028_e8603b00_f8810024_e8803b04_f8610020;
+defparam bootram.RAM1.INIT_1B=256'h12f72800_bc32fff0_16442800_30840001_d0762000_c0732000_30a00010_10800000;
+defparam bootram.RAM1.INIT_1C=256'hbe52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800_beb20020_1658b803;
+defparam bootram.RAM1.INIT_1D=256'hb60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000_f8003b18_12d62800;
+defparam bootram.RAM1.INIT_1E=256'hf9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000_b0009f00_3021003c;
+defparam bootram.RAM1.INIT_1F=256'hb0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000_31200400_b9f4fe34;
+defparam bootram.RAM1.INIT_20=256'hb9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824;
+defparam bootram.RAM1.INIT_21=256'h80000000_b9f40100_a46300ff_be120010_aa440020_a48400ff_64830008_80000000;
+defparam bootram.RAM1.INIT_22=256'hb0000000_e063118a_bc52ffe4_16439001_32400018_bcb2fff0_16439001_32400015;
+defparam bootram.RAM1.INIT_23=256'hf9e10000_10b60000_10c50000_12c00000_fac1001c_3021ffe0_b800ffac_f860f824;
+defparam bootram.RAM1.INIT_24=256'h30210020_b60f0008_eac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40174;
+defparam bootram.RAM1.INIT_25=256'h10b60000_30c00006_b9f4fdf0_f9e10000_10f60000_32c1001c_fac10028_3021ffd4;
+defparam bootram.RAM1.INIT_26=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f400b0_30c011a4;
+defparam bootram.RAM1.INIT_27=256'hf9e10000_10f60000_32c1001c_fac10028_3021ffd4_3021002c_b60f0008_6464001f;
+defparam bootram.RAM1.INIT_28=256'h80841800_14830000_30e00006_b9f40064_30c011ac_10b60000_30c00006_b9f4fda4;
+defparam bootram.RAM1.INIT_29=256'h3021ffe4_30a011b4_3021002c_b60f0008_6464001f_eac10028_e9e10000_a884ffff;
+defparam bootram.RAM1.INIT_2A=256'hb6910000_80000000_b6110000_30a0ffff_b9f4f324_80000000_b9f4f828_f9e10000;
+defparam bootram.RAM1.INIT_2B=256'hbeb2005c_16479003_22400003_80000000_b60f0008_80000000_b60f0008_80000000;
+defparam bootram.RAM1.INIT_2C=256'h30e7fffc_bc320040_16432000_e8660000_e8850000_bc230050_a4630003_80653000;
+defparam bootram.RAM1.INIT_2D=256'hbc120028_aa47ffff_30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004;
+defparam bootram.RAM1.INIT_2E=256'haa47ffff_30e7ffff_30c60001_30a50001_be320020_16434000_e0660000_e1050000;
+defparam bootram.RAM1.INIT_2F=256'hbeb20018_16479003_2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0;
+defparam bootram.RAM1.INIT_30=256'h10e72000_11040000_bc070024_11050000_be030034_a4630003_80662800_10850000;
+defparam bootram.RAM1.INIT_31=256'h10650000_b60f0008_30c60001_be32fff0_16474000_31080001_f0680000_e0660000;
+defparam bootram.RAM1.INIT_32=256'he866000c_f8880008_e8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000;
+defparam bootram.RAM1.INIT_33=256'h16479003_22400003_31080010_be52ffd0_16479003_2240000f_f868000c_30c60010;
+defparam bootram.RAM1.INIT_34=256'hbe52ffec_16479003_22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c;
+defparam bootram.RAM1.INIT_35=256'hfa61001c_3021ffe0_e8600f34_10880000_b810ff68_11044000_10c43000_30840004;
+defparam bootram.RAM1.INIT_36=256'haa43ffff_e8730000_3273fffc_99fc1800_bc120018_aa43ffff_32600f34_f9e10000;
+defparam bootram.RAM1.INIT_37=256'hb9f4f1dc_d9e00800_3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0;
+defparam bootram.RAM1.INIT_38=256'hd9e00800_3021fff8_30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000;
+defparam bootram.RAM1.INIT_39=256'hffffffff_00000000_ffffffff_30210008_b60f0008_c9e00800_80000000_b9f4f154;
+defparam bootram.RAM1.INIT_3A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000;
+defparam bootram.RAM1.INIT_3B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120;
+defparam bootram.RAM1.INIT_3C=256'h20555352_74696e67_53746172_720a0000_6f616465_6f6f746c_322b2062_55535250;
+defparam bootram.RAM1.INIT_3D=256'h65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20;
+defparam bootram.RAM1.INIT_3E=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672;
+defparam bootram.RAM1.INIT_3F=256'h66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068_206e6576;
+defparam bootram.RAM2.INIT_00=256'h6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520_69726d77;
+defparam bootram.RAM2.INIT_01=256'h5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963;
+defparam bootram.RAM2.INIT_02=256'h726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000_2052414d;
+defparam bootram.RAM2.INIT_03=256'h6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f;
+defparam bootram.RAM2.INIT_04=256'h7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047_74696f6e;
+defparam bootram.RAM2.INIT_05=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f;
+defparam bootram.RAM2.INIT_06=256'h20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741;
+defparam bootram.RAM2.INIT_07=256'h56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164;
+defparam bootram.RAM2.INIT_08=256'h204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563_64207072;
+defparam bootram.RAM2.INIT_09=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67;
+defparam bootram.RAM2.INIT_0A=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67;
+defparam bootram.RAM2.INIT_0B=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000;
+defparam bootram.RAM2.INIT_0C=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75;
+defparam bootram.RAM2.INIT_0D=256'h00000000_6f72740a_0a0a6162_aa990000_ffffffff_b8080000_b0000000_10101200;
+defparam bootram.RAM2.INIT_0E=256'h20202020_20202020_20202020_20202020_28282820_20202828_20202020_00202020;
+defparam bootram.RAM2.INIT_0F=256'h10101010_04040410_04040404_10040404_10101010_10101010_10101010_20881010;
+defparam bootram.RAM2.INIT_10=256'h10101010_01010101_01010101_01010101_01010101_01010101_41414141_10104141;
+defparam bootram.RAM2.INIT_11=256'h10101010_02020202_02020202_02020202_02020202_02020202_42424242_10104242;
+defparam bootram.RAM2.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_20000000;
+defparam bootram.RAM2.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_1A=256'h20202020_20202020_20202020_28282020_20282828_20202020_20202020_00000000;
+defparam bootram.RAM2.INIT_1B=256'h04041010_04040404_04040404_10101010_10101010_10101010_88101010_20202020;
+defparam bootram.RAM2.INIT_1C=256'h01010110_01010101_01010101_01010101_01010101_41414101_10414141_10101010;
+defparam bootram.RAM2.INIT_1D=256'h02020210_02020202_02020202_02020202_02020202_42424202_10424242_10101010;
+defparam bootram.RAM2.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_10101020;
+defparam bootram.RAM2.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_22=256'h00000000_00001344_01000000_00000f40_00000000_00000000_00000000_00000000;
+defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+
+ ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768))
+ sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .if_adr(if_adr[14:0]), .if_data(if_dat_main),
+ .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
+ .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Buffer Pool, slave #1
+ wire rd0_ready_i, rd0_ready_o;
+ wire rd1_ready_i, rd1_ready_o;
+ wire rd2_ready_i, rd2_ready_o;
+ wire rd3_ready_i, rd3_ready_o;
+ wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+ wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+ wire wr0_ready_i, wr0_ready_o;
+ wire wr1_ready_i, wr1_ready_o;
+ wire wr2_ready_i, wr2_ready_o;
+ wire wr3_ready_i, wr3_ready_o;
+ wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+ wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+ buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+ .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+ .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+
+ .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .status(status),.sys_int_o(buffer_int),
+
+ .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+ .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+
+ // Write Interfaces
+ .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
+ .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
+ .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
+ .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
+ // Read Interfaces
+ .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
+ .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
+ .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
+ .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+ );
+
+ wire [31:0] status_enc;
+ priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // SPI -- Slave #2
+ spi_top shared_spi
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+ .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+ .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+ .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // I2C -- Slave #3
+ i2c_master_top #(.ARST_LVL(1))
+ i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
+ .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+ .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+ .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+ .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+ .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+ assign s3_dat_i[31:8] = 24'd0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // GPIOs -- Slave #4
+ nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+ .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+ .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+ .gpio( {io_tx,io_rx} )
+ );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Buffer Pool Status -- Slave #5
+
+ reg [31:0] cycle_count;
+ always @(posedge wb_clk)
+ if(wb_rst)
+ cycle_count <= 0;
+ else
+ cycle_count <= cycle_count + 1;
+
+ wb_readback_mux buff_pool_status
+ (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+ .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+
+ .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+ .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+ .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+ .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Ethernet MAC Slave #6
+
+ wire [18:0] rx_f19_data, tx_f19_data;
+ wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+
+ simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+ (.clk125(clk_to_mac), .reset(wb_rst),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .sys_clk(dsp_clk),
+ .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
+ .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+ .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+ .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+ .mdio(MDIO), .mdc(MDC),
+ .debug(debug_mac));
+
+ wire [35:0] udp_tx_data, udp_rx_data;
+ wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
+
+ udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+ .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+ .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
+ .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
+ .debug(debug_udp) );
+
+ fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+ .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
+ fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+ .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Settings Bus -- Slave #7
+ settings_bus settings_bus
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+ .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+ .strobe(set_stb),.addr(set_addr),.data(set_data));
+
+ assign s7_dat_i = 32'd0;
+
+ settings_bus_crossclock settings_bus_crossclock
+ (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+ .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+
+ // Output control lines
+ wire [7:0] clock_outs, serdes_outs, adc_outs;
+ assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+ assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+ assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+ wire phy_reset;
+ assign PHY_RESETn = ~phy_reset;
+
+ setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+ .in(set_data),.out(clock_outs),.changed());
+ setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(serdes_outs),.changed());
+ setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(adc_outs),.changed());
+ setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(phy_reset),.changed());
+
+ // /////////////////////////////////////////////////////////////////////////
+ // LEDS
+ // register 8 determines whether leds are controlled by SW or not
+ // 1 = controlled by HW, 0 = by SW
+ // In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+
+ wire [7:0] led_src, led_sw;
+ wire [7:0] led_hw = {clk_status,serdes_link_up};
+
+ setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(led_sw),.changed());
+ setting_reg #(.my_addr(8),.width(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(led_src),.changed());
+
+ assign leds = (led_src & led_hw) | (~led_src & led_sw);
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Interrupt Controller, Slave #8
+
+ assign irq= {{8'b0},
+ {uart_tx_int[3:0], uart_rx_int[3:0]},
+ {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00},
+ {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+
+ pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
+ .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+ .irq(irq) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Master Timer, Slave #9
+
+ // No longer used, replaced with simple_timer below
+ assign s9_ack = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // Simple Timer interrupts
+
+ simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+ (.clk(wb_clk), .reset(wb_rst),
+ .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+ .onetime_int(onetime_int), .periodic_int(periodic_int));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // UART, Slave #10
+
+ quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+ .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+ .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+ .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // ATR Controller, Slave #11
+
+ wire run_rx, run_tx;
+ reg run_rx_d1;
+ always @(posedge dsp_clk)
+ run_rx_d1 <= run_rx;
+
+ atr_controller atr_controller
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+ .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+ .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+ .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+
+ // //////////////////////////////////////////////////////////////////////////
+ // Time Sync, Slave #12
+
+ // No longer used, see time_64bit. Still need to handle mimo time, though
+ assign sc_ack = 0;
+
+ // /////////////////////////////////////////////////////////////////////////
+ // ICAP for reprogramming the FPGA, Slave #13 (D)
+
+ s3a_icap_wb s3a_icap_wb
+ (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb),
+ .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i));
+
+ // /////////////////////////////////////////////////////////////////////////
+ // SPI for Flash -- Slave #14 (E)
+ spi_top flash_spi
+ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o),
+ .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb),
+ .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int),
+ .ss_pad_o(spiflash_cs),
+ .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // DSP RX
+ wire [31:0] sample_rx, sample_tx;
+ wire strobe_rx, strobe_tx;
+ wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
+ wire [99:0] rx_data;
+ wire [35:0] rx1_data;
+
+ dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+ .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+ .debug(debug_rx_dsp) );
+
+ wire [31:0] vrc_debug;
+
+ vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .vita_time(vita_time), .overrun(overrun),
+ .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+ .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
+ .debug_rx(vrc_debug));
+
+ wire [3:0] vita_state;
+
+ vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+ .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+ .fifo_occupied(), .fifo_full(), .fifo_empty(),
+ .debug_rx(vita_state) );
+
+ fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+ .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
+ // ///////////////////////////////////////////////////////////////////////////////////
+ // DSP TX
+
+ wire [35:0] tx_data;
+ wire [99:0] tx1_data;
+ wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
+
+ wire [31:0] debug_vtc, debug_vtd, debug_vt;
+
+ fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
+ .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+
+ vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+ .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+ .debug(debug_vtd) );
+
+ vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .vita_time(vita_time),.underrun(underrun),
+ .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug(debug_vtc) );
+
+ assign debug_vt = debug_vtc | debug_vtd;
+
+ dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .debug(debug_tx_dsp) );
+
+ assign dsp_rst = wb_rst;
+
+ // ///////////////////////////////////////////////////////////////////////////////////
+ // SERDES
+
+ serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+ .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+ .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+ .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+ .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+ .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+ .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+ // /////////////////////////////////////////////////////////////////////////
+ // VITA Timing
+
+ time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+ (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+ .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+
+ // /////////////////////////////////////////////////////////////////////////////////////////
+ // Debug Pins
+
+ assign debug_clk = {dsp_clk, wb_clk};
+// assign debug = debug_vt;
+ assign debug = {wb_clk, wb_rst, sd_cyc, sd_stb, sd_we, sd_ack, sd_dat_o[7:0], sd_dat_i[7:0], 10'd0};
+
+ assign debug_gpio_0 = 32'd0;
+ assign debug_gpio_1 = 32'd0;
+
+endmodule // u2_core
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