diff options
| -rw-r--r-- | control_lib/SYSCTRL.sav | 24 | ||||
| -rw-r--r-- | control_lib/WB_SIM.sav | 47 | ||||
| -rw-r--r-- | control_lib/clock_control_tb.sav | 28 | ||||
| -rw-r--r-- | opencores/i2c/sim/i2c_verilog/run/ncverilog.log | 118 | ||||
| -rw-r--r-- | testbench/BOOTSTRAP.sav | 82 | ||||
| -rw-r--r-- | testbench/PAUSE.sav | 62 | ||||
| -rw-r--r-- | testbench/SERDES.sav | 35 | ||||
| -rw-r--r-- | testbench/U2_SIM.sav | 95 | ||||
| -rw-r--r-- | usrp2/boot_cpld/.gitignore (renamed from boot_cpld/.gitignore) | 0 | ||||
| -rwxr-xr-x | usrp2/boot_cpld/_impact.cmd (renamed from boot_cpld/_impact.cmd) | 0 | ||||
| -rwxr-xr-x | usrp2/boot_cpld/boot_cpld.ipf (renamed from boot_cpld/boot_cpld.ipf) | bin | 2967 -> 2967 bytes | |||
| -rwxr-xr-x | usrp2/boot_cpld/boot_cpld.ise (renamed from boot_cpld/boot_cpld.ise) | bin | 227573 -> 227573 bytes | |||
| -rwxr-xr-x | usrp2/boot_cpld/boot_cpld.lfp (renamed from boot_cpld/boot_cpld.lfp) | 0 | ||||
| -rwxr-xr-x | usrp2/boot_cpld/boot_cpld.ucf (renamed from boot_cpld/boot_cpld.ucf) | 0 | ||||
| -rwxr-xr-x | usrp2/boot_cpld/boot_cpld.v (renamed from boot_cpld/boot_cpld.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/.gitignore (renamed from control_lib/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/CRC16_D16.v (renamed from control_lib/CRC16_D16.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/atr_controller.v (renamed from control_lib/atr_controller.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/bin2gray.v (renamed from control_lib/bin2gray.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/bootrom.mem (renamed from control_lib/bootrom.mem) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/clock_bootstrap_rom.v (renamed from control_lib/clock_bootstrap_rom.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/clock_control.v (renamed from control_lib/clock_control.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/clock_control_tb.v (renamed from control_lib/clock_control_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/cmdfile (renamed from control_lib/cmdfile) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/dcache.v (renamed from control_lib/dcache.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/decoder_3_8.v (renamed from control_lib/decoder_3_8.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/dpram32.v (renamed from control_lib/dpram32.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/fifo_tb.v (renamed from control_lib/fifo_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/gray2bin.v (renamed from control_lib/gray2bin.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/gray_send.v (renamed from control_lib/gray_send.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/icache.v (renamed from control_lib/icache.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/longfifo.v (renamed from control_lib/longfifo.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/medfifo.v (renamed from control_lib/medfifo.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/mux4.v (renamed from control_lib/mux4.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/mux8.v (renamed from control_lib/mux8.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/mux_32_4.v (renamed from control_lib/mux_32_4.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/.gitignore (renamed from control_lib/newfifo/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/buffer_int.v (renamed from control_lib/newfifo/buffer_int.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/buffer_int_tb.v (renamed from control_lib/newfifo/buffer_int_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/buffer_pool.v (renamed from control_lib/newfifo/buffer_pool.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/buffer_pool_tb.v (renamed from control_lib/newfifo/buffer_pool_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo19_to_fifo36.v (renamed from control_lib/newfifo/fifo19_to_fifo36.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo19_to_ll8.v (renamed from control_lib/newfifo/fifo19_to_ll8.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo36_to_fifo18.v (renamed from control_lib/newfifo/fifo36_to_fifo18.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo36_to_fifo19.v (renamed from control_lib/newfifo/fifo36_to_fifo19.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo36_to_ll8.v (renamed from control_lib/newfifo/fifo36_to_ll8.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_2clock.v (renamed from control_lib/newfifo/fifo_2clock.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_2clock_cascade.v (renamed from control_lib/newfifo/fifo_2clock_cascade.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_cascade.v (renamed from control_lib/newfifo/fifo_cascade.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_long.v (renamed from control_lib/newfifo/fifo_long.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_new_tb.vcd (renamed from control_lib/newfifo/fifo_new_tb.vcd) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_short.v (renamed from control_lib/newfifo/fifo_short.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_spec.txt (renamed from control_lib/newfifo/fifo_spec.txt) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/fifo_tb.v (renamed from control_lib/newfifo/fifo_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/ll8_shortfifo.v (renamed from control_lib/newfifo/ll8_shortfifo.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/ll8_to_fifo19.v (renamed from control_lib/newfifo/ll8_to_fifo19.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/newfifo/ll8_to_fifo36.v (renamed from control_lib/newfifo/ll8_to_fifo36.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/nsgpio.v (renamed from control_lib/nsgpio.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/oneshot_2clk.v (renamed from control_lib/oneshot_2clk.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/pic.v (renamed from control_lib/pic.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/priority_enc.v (renamed from control_lib/priority_enc.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/ram_2port.v (renamed from control_lib/ram_2port.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/ram_harv_cache.v (renamed from control_lib/ram_harv_cache.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/ram_loader.v (renamed from control_lib/ram_loader.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/ram_wb_harvard.v (renamed from control_lib/ram_wb_harvard.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/reset_sync.v (renamed from control_lib/reset_sync.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/sd_spi.v (renamed from control_lib/sd_spi.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/sd_spi_tb.v (renamed from control_lib/sd_spi_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/sd_spi_wb.v (renamed from control_lib/sd_spi_wb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/setting_reg.v (renamed from control_lib/setting_reg.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/settings_bus.v (renamed from control_lib/settings_bus.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/shortfifo.v (renamed from control_lib/shortfifo.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/simple_uart.v (renamed from control_lib/simple_uart.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/simple_uart_rx.v (renamed from control_lib/simple_uart_rx.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/simple_uart_tx.v (renamed from control_lib/simple_uart_tx.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/spi.v (renamed from control_lib/spi.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/srl.v (renamed from control_lib/srl.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/ss_rcvr.v (renamed from control_lib/ss_rcvr.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/system_control.v (renamed from control_lib/system_control.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/system_control_tb.v (renamed from control_lib/system_control_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/traffic_cop.v (renamed from control_lib/traffic_cop.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_1master.v (renamed from control_lib/wb_1master.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_bridge_16_32.v (renamed from control_lib/wb_bridge_16_32.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_bus_writer.v (renamed from control_lib/wb_bus_writer.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_output_pins32.v (renamed from control_lib/wb_output_pins32.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_ram_block.v (renamed from control_lib/wb_ram_block.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_ram_dist.v (renamed from control_lib/wb_ram_dist.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_readback_mux.v (renamed from control_lib/wb_readback_mux.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_regfile_2clock.v (renamed from control_lib/wb_regfile_2clock.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_semaphore.v (renamed from control_lib/wb_semaphore.v) | 0 | ||||
| -rw-r--r-- | usrp2/control_lib/wb_sim.v (renamed from control_lib/wb_sim.v) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/.gitignore (renamed from coregen/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/coregen.cgp (renamed from coregen/coregen.cgp) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_generator_release_notes.txt (renamed from coregen/fifo_generator_release_notes.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_generator_ug175.pdf (renamed from coregen/fifo_generator_ug175.pdf) | bin | 1069823 -> 1069823 bytes | |||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk.ngc (renamed from coregen/fifo_xlnx_16x19_2clk.ngc) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk.v (renamed from coregen/fifo_xlnx_16x19_2clk.v) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk.veo (renamed from coregen/fifo_xlnx_16x19_2clk.veo) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk.xco (renamed from coregen/fifo_xlnx_16x19_2clk.xco) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso (renamed from coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt (renamed from coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt (renamed from coregen/fifo_xlnx_16x19_2clk_flist.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt (renamed from coregen/fifo_xlnx_16x19_2clk_readme.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl (renamed from coregen/fifo_xlnx_16x19_2clk_xmdf.tcl) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy (renamed from coregen/fifo_xlnx_2Kx36_2clk.asy) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc (renamed from coregen/fifo_xlnx_2Kx36_2clk.ngc) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym (renamed from coregen/fifo_xlnx_2Kx36_2clk.sym) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.v (renamed from coregen/fifo_xlnx_2Kx36_2clk.v) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo (renamed from coregen/fifo_xlnx_2Kx36_2clk.veo) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd (renamed from coregen/fifo_xlnx_2Kx36_2clk.vhd) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho (renamed from coregen/fifo_xlnx_2Kx36_2clk.vho) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco (renamed from coregen/fifo_xlnx_2Kx36_2clk.xco) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso (renamed from coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt (renamed from coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt (renamed from coregen/fifo_xlnx_2Kx36_2clk_flist.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt (renamed from coregen/fifo_xlnx_2Kx36_2clk_readme.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl (renamed from coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.asy (renamed from coregen/fifo_xlnx_512x36_2clk.asy) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.ngc (renamed from coregen/fifo_xlnx_512x36_2clk.ngc) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.sym (renamed from coregen/fifo_xlnx_512x36_2clk.sym) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.v (renamed from coregen/fifo_xlnx_512x36_2clk.v) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.veo (renamed from coregen/fifo_xlnx_512x36_2clk.veo) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.vhd (renamed from coregen/fifo_xlnx_512x36_2clk.vhd) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.vho (renamed from coregen/fifo_xlnx_512x36_2clk.vho) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk.xco (renamed from coregen/fifo_xlnx_512x36_2clk.xco) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso (renamed from coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt (renamed from coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt (renamed from coregen/fifo_xlnx_512x36_2clk_flist.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt (renamed from coregen/fifo_xlnx_512x36_2clk_readme.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl (renamed from coregen/fifo_xlnx_512x36_2clk_xmdf.tcl) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk.ngc (renamed from coregen/fifo_xlnx_64x36_2clk.ngc) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk.v (renamed from coregen/fifo_xlnx_64x36_2clk.v) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk.veo (renamed from coregen/fifo_xlnx_64x36_2clk.veo) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk.xco (renamed from coregen/fifo_xlnx_64x36_2clk.xco) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso (renamed from coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt (renamed from coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt (renamed from coregen/fifo_xlnx_64x36_2clk_flist.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt (renamed from coregen/fifo_xlnx_64x36_2clk_readme.txt) | 0 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl (renamed from coregen/fifo_xlnx_64x36_2clk_xmdf.tcl) | 0 | ||||
| -rw-r--r-- | usrp2/extram/.gitignore (renamed from extram/.gitignore) | 0 | ||||
| -rw-r--r-- | usrp2/extram/extram_interface.v (renamed from extram/extram_interface.v) | 0 | ||||
| -rw-r--r-- | usrp2/extram/extram_wb.v (renamed from extram/extram_wb.v) | 0 | ||||
| -rw-r--r-- | usrp2/extram/wb_zbt16_b.v (renamed from extram/wb_zbt16_b.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/BUFG.v (renamed from models/BUFG.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/CY7C1356C/cy1356.inp (renamed from models/CY7C1356C/cy1356.inp) | 0 | ||||
| -rw-r--r-- | usrp2/models/CY7C1356C/cy1356.v (renamed from models/CY7C1356C/cy1356.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/CY7C1356C/readme.txt (renamed from models/CY7C1356C/readme.txt) | 0 | ||||
| -rw-r--r-- | usrp2/models/CY7C1356C/testbench.v (renamed from models/CY7C1356C/testbench.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/FIFO_GENERATOR_V4_3.v (renamed from models/FIFO_GENERATOR_V4_3.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/M24LC024B.v (renamed from models/M24LC024B.v) | 0 | ||||
| -rw-r--r-- | usrp2/models/M24LC02B.v (renamed from models/M24LC02B.v) | 0 | ||||
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| -rw-r--r-- | usrp2/top/tcl/ise_helper.tcl (renamed from top/tcl/ise_helper.tcl) | 0 | ||||
| -rw-r--r-- | usrp2/top/u2_core/.gitignore (renamed from top/u2_core/.gitignore) | 0 | ||||
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| -rw-r--r-- | usrp2/top/u2_rev1/u2_fpga.ise (renamed from top/u2_rev1/u2_fpga.ise) | bin | 477678 -> 477678 bytes | |||
| -rwxr-xr-x | usrp2/top/u2_rev1/u2_fpga.ucf (renamed from top/u2_rev1/u2_fpga.ucf) | 0 | ||||
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| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/README (renamed from top/u2_rev3_2rx_iad/README) | 0 | ||||
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| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v (renamed from top/u2_rev3_2rx_iad/dsp_core_rx.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav (renamed from top/u2_rev3_2rx_iad/dsp_core_tb.sav) | 0 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v (renamed from top/u2_rev3_2rx_iad/dsp_core_tb.v) | 0 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3_2rx_iad/impulse.v (renamed from top/u2_rev3_2rx_iad/impulse.v) | 0 | ||||
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641 files changed, 0 insertions, 491 deletions
diff --git a/control_lib/SYSCTRL.sav b/control_lib/SYSCTRL.sav deleted file mode 100644 index 43bfef10e..000000000 --- a/control_lib/SYSCTRL.sav +++ /dev/null @@ -1,24 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -system_control_tb.aux_clk -@29 -system_control_tb.clk_fpga -@28 -system_control_tb.dsp_clk -system_control_tb.dsp_rst -system_control_tb.proc_rst -system_control_tb.rl_done -system_control_tb.rl_rst -system_control_tb.wb_clk -system_control_tb.wb_rst -system_control_tb.system_control.POR -@22 -system_control_tb.system_control.POR_ctr[3:0] -@28 -system_control_tb.clock_ready -system_control_tb.system_control.half_clk -system_control_tb.system_control.fin_ret_half -system_control_tb.system_control.fin_ret_aux -system_control_tb.system_control.gate_dsp_clk diff --git a/control_lib/WB_SIM.sav b/control_lib/WB_SIM.sav deleted file mode 100644 index 467cd35ef..000000000 --- a/control_lib/WB_SIM.sav +++ /dev/null @@ -1,47 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -wb_sim.wb_rst -wb_sim.wb_clk -@23 -wb_sim.rom_data[47:0] -@22 -wb_sim.rom_addr[15:0] -@28 -wb_sim.start -wb_sim.wb_ack -@22 -wb_sim.wb_adr[15:0] -@28 -wb_sim.wb_cyc -@22 -wb_sim.wb_dat[31:0] -wb_sim.wb_sel[3:0] -@28 -wb_sim.wb_stb -wb_sim.wb_we -@22 -wb_sim.port_output[31:0] -@28 -wb_sim.system_control.POR -wb_sim.system_control.aux_clk -wb_sim.system_control.clk_fpga -@29 -wb_sim.system_control.done -@28 -wb_sim.system_control.dsp_clk -wb_sim.system_control.fin_del1 -wb_sim.system_control.fin_del2 -wb_sim.system_control.fin_del3 -wb_sim.system_control.fin_ret_aux -@29 -wb_sim.system_control.fin_ret_fpga -@28 -wb_sim.system_control.finished -wb_sim.system_control.reset_out -wb_sim.system_control.start -wb_sim.system_control.started -wb_sim.system_control.wb_clk_o -wb_sim.system_control.wb_rst_o -wb_sim.system_control.wb_rst_o_alt diff --git a/control_lib/clock_control_tb.sav b/control_lib/clock_control_tb.sav deleted file mode 100644 index be4001dc5..000000000 --- a/control_lib/clock_control_tb.sav +++ /dev/null @@ -1,28 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-7.848898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -clock_control_tb.aux_clk -clock_control_tb.reset -clock_control_tb.sclk -clock_control_tb.sdi -clock_control_tb.sdo -clock_control_tb.sen -@22 -clock_control_tb.clock_control.counter[7:0] -@28 -clock_control_tb.clock_control.done -@22 -clock_control_tb.clock_control.entry[5:0] -@28 -clock_control_tb.clock_control.read -clock_control_tb.clock_control.reset -clock_control_tb.clock_control.sclk -clock_control_tb.clock_control.w[1:0] -clock_control_tb.sen -clock_control_tb.sdo -clock_control_tb.sclk -clock_control_tb.clock_control.done -clock_control_tb.clock_control.start -@22 -clock_control_tb.clock_control.addr_data[20:0] diff --git a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log b/opencores/i2c/sim/i2c_verilog/run/ncverilog.log deleted file mode 100644 index 420a1b9e5..000000000 --- a/opencores/i2c/sim/i2c_verilog/run/ncverilog.log +++ /dev/null @@ -1,118 +0,0 @@ -ncverilog: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc. -ncverilog: v03.40.(b001): Started on Jun 15, 2002 at 13:36:36 -ncverilog - +access+rwc - +linedebug - +define+"WAVES" - +incdir+../../../../bench/verilog - +incdir+../../../../rtl/verilog - +libext+.v - -y - /tools/synopsys/dw/sim_ver/ - ../../../../rtl/verilog/i2c_master_bit_ctrl.v - ../../../../rtl/verilog/i2c_master_byte_ctrl.v - ../../../../rtl/verilog/i2c_master_top.v - ../../../../bench/verilog/i2c_slave_model.v - ../../../../bench/verilog/wb_master_model.v - ../../../../bench/verilog/tst_bench_top.v - -ncverilog: *W,BADPRF: The +linedebug option may have an adverse performance impact. -file: ../../../../rtl/verilog/i2c_master_bit_ctrl.v - module worklib.i2c_master_bit_ctrl:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../rtl/verilog/i2c_master_byte_ctrl.v - module worklib.i2c_master_byte_ctrl:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../rtl/verilog/i2c_master_top.v - module worklib.i2c_master_top:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/i2c_slave_model.v - module worklib.i2c_slave_model:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/wb_master_model.v - module worklib.wb_master_model:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../../bench/verilog/tst_bench_top.v - module worklib.tst_bench_top:v - errors: 0, warnings: 0 -ncvlog: *W,LIBNOU: Library "/tools/synopsys/dw/sim_ver/" given but not used. - Total errors/warnings found outside modules and primitives: - errors: 0, warnings: 1 - Caching library 'worklib' ....... Done - Elaborating the design hierarchy: - Building instance overlay tables: .................... Done - Generating native compiled code: - worklib.tst_bench_top:v <0x7fb52c98> - streams: 12, words: 59009 - Loading native compiled code: .................... Done - Building instance specific data structures. - Design hierarchy summary: - Instances Unique - Modules: 6 6 - Primitives: 2 1 - Registers: 68 68 - Scalar wires: 48 - - Expanded wires: 36 2 - Vectored wires: 6 - - Always blocks: 23 23 - Initial blocks: 3 3 - Cont. assignments: 28 28 - Pseudo assignments: 11 14 - Simulation timescale: 10ps - Writing initial simulation snapshot: worklib.tst_bench_top:v -Loading snapshot worklib.tst_bench_top:v .................... Done -ncsim> source /cds/tools/inca/files/ncsimrc -ncsim> run -INFO: Signal dump enabled ... - - - -status: 0 Testbench started - - - -INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0) - -status: 19500 done reset -status: 23600 programmed registers -status: 25600 verified registers -status: 27600 enabled core -status: 30600 generate 'start', write cmd a0 (slave address+write) -status: 2582600 tip==0 -status: 2585600 write slave memory address 01 -status: 4877600 tip==0 -status: 4880600 write data a5 -status: 7172600 tip==0 -status: 7175600 write next data 5a, generate 'stop' -status: 9467600 tip==0 -status: 19467600 wait 100us -status: 19470600 generate 'start', write cmd a0 (slave address+write) -status: 22014600 tip==0 -status: 22017600 write slave address 01 -status: 24309600 tip==0 -status: 24312600 generate 'repeated start', write cmd a1 (slave address+read) -status: 26858600 tip==0 -status: 26860600 read + ack -status: 29154600 tip==0 -status: 29158600 read + ack -status: 31448600 tip==0 -status: 31452600 read + ack -status: 33744600 tip==0 -status: 33746600 received xx from 3rd read address -status: 33748600 read + nack -status: 36038600 tip==0 -status: 36040600 received xx from 4th read address -status: 36043600 generate 'start', write cmd a0 (slave address+write). Check invalid address -status: 38589600 tip==0 -status: 38592600 write slave memory address 10 -status: 40884600 tip==0 -status: 40884600 Check for nack -status: 40886600 generate 'stop' -status: 40888600 tip==0 - - -status: 43388600 Testbench done -Simulation stopped via $stop(1) at time 433886 NS + 0 -/mnt/pooh/projects/I2C/bench/verilog/tst_bench_top.v:427 $stop; -ncsim> exit -ncverilog: v03.40.(b001): Exiting on Jun 15, 2002 at 13:47:48 (total: 00:11:12) diff --git a/testbench/BOOTSTRAP.sav b/testbench/BOOTSTRAP.sav deleted file mode 100644 index 41501945f..000000000 --- a/testbench/BOOTSTRAP.sav +++ /dev/null @@ -1,82 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.cpld_clk -u2_sim_top.cpld_detached -u2_sim_top.cpld_din -u2_sim_top.cpld_done -u2_sim_top.cpld_start -u2_sim_top.aux_clk -u2_sim_top.clk_fpga -u2_sim_top.clk_sel[1:0] -u2_sim_top.clk_en[1:0] -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.ram_loader_done_i -u2_sim_top.cpld_model.sclk -u2_sim_top.cpld_model.start -u2_sim_top.u2_basic.ram_loader.rst_i -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.sclk -@22 -u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] -u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] -@28 -u2_sim_top.u2_basic.shared_spi.wb_we_i -u2_sim_top.u2_basic.shared_spi.wb_stb_i -u2_sim_top.u2_basic.shared_spi.wb_ack_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] -u2_sim_top.u2_basic.shared_spi.ctrl[13:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -u2_sim_top.u2_basic.shared_spi.char_len[6:0] -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] -u2_sim_top.u2_basic.shared_spi.rx[127:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -@22 -u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] -u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.u2_basic.control_lines.wb_cyc_i -@22 -u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] -@28 -u2_sim_top.clock_ready -u2_sim_top.u2_basic.ram_loader.done_o -u2_sim_top.u2_basic.dsp_rst -u2_sim_top.u2_basic.ram_loader_rst -u2_sim_top.u2_basic.wb_rst -@22 -u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] -@28 -u2_sim_top.u2_basic.aeMB.iwb_ack_i -u2_sim_top.u2_basic.ram_loader_done -@22 -u2_sim_top.u2_basic.iram_rd_adr[15:0] -u2_sim_top.u2_basic.iram_rd_dat[31:0] -@28 -u2_sim_top.u2_basic.iram_wr_we -u2_sim_top.u2_basic.iram_wr_stb -@22 -u2_sim_top.u2_basic.iram_wr_sel[3:0] -u2_sim_top.u2_basic.iram_wr_dat[31:0] -u2_sim_top.u2_basic.iram_wr_adr[15:0] -@28 -u2_sim_top.u2_basic.ram_loader.ram_loader_done_o -u2_sim_top.u2_basic.ID_ram.dwb_we_i -u2_sim_top.u2_basic.ID_ram.iwb_we_i -u2_sim_top.u2_basic.ram_loader.ram_we -u2_sim_top.u2_basic.ram_loader.ram_we_q -u2_sim_top.u2_basic.ram_loader.ram_we_s -u2_sim_top.u2_basic.ram_loader.wb_ack_i -u2_sim_top.u2_basic.ID_ram.iwb_ack_o -u2_sim_top.u2_basic.ID_ram.iwb_stb_i -u2_sim_top.u2_basic.ID_ram.wb_rst_i diff --git a/testbench/PAUSE.sav b/testbench/PAUSE.sav deleted file mode 100644 index f5e1ea1ac..000000000 --- a/testbench/PAUSE.sav +++ /dev/null @@ -1,62 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] u2_sim_top. -[treeopen] u2_sim_top.u2_basic. -[treeopen] u2_sim_top.u2_basic.MAC_top. -[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. -@22 -u2_sim_top.GMII_TXD[7:0] -@28 -u2_sim_top.GMII_TX_EN -@200 -- -@24 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk -@24 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 -@200 -- -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] -@28 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en -u2_sim_top.u2_basic.proc_int -@22 -u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] -u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] -@25 -u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] diff --git a/testbench/SERDES.sav b/testbench/SERDES.sav deleted file mode 100644 index 3bb6ba929..000000000 --- a/testbench/SERDES.sav +++ /dev/null @@ -1,35 +0,0 @@ -[size] 1400 967 -[pos] -1 -1 -*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] u2_sim_top. -[treeopen] u2_sim_top.u2_basic. -[treeopen] u2_sim_top.u2_basic.serdes. -@22 -u2_sim_top.u2_basic.serdes.ser_t[15:0] -@28 -u2_sim_top.u2_basic.serdes.ser_tklsb -u2_sim_top.u2_basic.serdes.ser_tkmsb -u2_sim_top.u2_basic.ram_loader.ram_loader_done_o -u2_sim_top.u2_basic.proc_int -@22 -u2_sim_top.u2_basic.serdes.fifo_space[15:0] -@28 -u2_sim_top.u2_basic.serdes.inhibit_tx -u2_sim_top.u2_basic.serdes.send_xoff -u2_sim_top.u2_basic.serdes.send_xon -u2_sim_top.u2_basic.serdes.sent -u2_sim_top.u2_basic.serdes.xoff_rcvd -u2_sim_top.u2_basic.serdes.xon_rcvd -u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o -u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o -u2_sim_top.u2_basic.serdes.serdes_rx.write -@22 -u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0] -@28 -(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -@22 -#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] -u2_sim_top.u2_basic.serdes.ser_t[15:0] -@28 -u2_sim_top.u2_basic.serdes.ser_tklsb diff --git a/testbench/U2_SIM.sav b/testbench/U2_SIM.sav deleted file mode 100644 index d320c2b6c..000000000 --- a/testbench/U2_SIM.sav +++ /dev/null @@ -1,95 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -u2_sim_top.adc_oen_a -u2_sim_top.adc_oen_b -u2_sim_top.adc_pdn_a -u2_sim_top.adc_pdn_b -u2_sim_top.aux_clk -u2_sim_top.POR -u2_sim_top.clk_fpga -u2_sim_top.clk_en[1:0] -u2_sim_top.clk_sel[1:0] -u2_sim_top.led1 -u2_sim_top.led2 -u2_sim_top.sclk -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0] -u2_sim_top.sda_pad_o -u2_sim_top.sda_pad_oen_o -u2_sim_top.sdi -u2_sim_top.sdo -u2_sim_top.sen_clk -u2_sim_top.sen_dac -u2_sim_top.ser_enable -u2_sim_top.ser_loopen -u2_sim_top.ser_prbsen -u2_sim_top.ser_rx_en -u2_sim_top.u2_basic.sysctrl.start -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.done -u2_sim_top.u2_basic.sysctrl.POR -u2_sim_top.u2_basic.sysctrl.aux_clk -u2_sim_top.u2_basic.sysctrl.clk_fpga -u2_sim_top.u2_basic.sysctrl.done -u2_sim_top.u2_basic.bus_writer.start -u2_sim_top.u2_basic.bus_writer.done -@22 -u2_sim_top.u2_basic.bus_writer.rom_addr[15:0] -u2_sim_top.u2_basic.bus_writer.rom_data[47:0] -u2_sim_top.u2_basic.bus_writer.state[3:0] -@29 -u2_sim_top.u2_basic.bus_writer.wb_ack_i -@22 -u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_clk_i -u2_sim_top.u2_basic.bus_writer.wb_cyc_o -@22 -u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0] -u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0] -@28 -u2_sim_top.u2_basic.bus_writer.wb_stb_o -u2_sim_top.u2_basic.bus_writer.wb_we_o -u2_sim_top.u2_basic.bus_writer.wb_rst_i -u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0] -u2_sim_top.sda_pad_i -u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i -u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o -@22 -u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0] -u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0] -@28 -u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i -u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i -u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o -u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i -u2_sim_top.u2_basic.control_lines.wb_cyc_i -u2_sim_top.u2_basic.control_lines.wb_stb_i -u2_sim_top.u2_basic.control_lines.wb_we_i -u2_sim_top.u2_basic.control_lines.wb_ack_o -u2_sim_top.u2_basic.s0_ack -@22 -u2_sim_top.u2_basic.control_lines.internal_reg[31:0] -u2_sim_top.u2_basic.control_lines.port_output[31:0] -@28 -u2_sim_top.u2_basic.led1 -u2_sim_top.u2_basic.led2 -@22 -u2_sim_top.u2_basic.misc_outs[7:0] -u2_sim_top.u2_basic.clock_outs[7:0] -u2_sim_top.u2_basic.adc_outs[7:0] -u2_sim_top.u2_basic.serdes_outs[7:0] -@28 -u2_sim_top.u2_basic.shared_spi.miso_pad_i -u2_sim_top.u2_basic.shared_spi.mosi_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss[7:0] -u2_sim_top.u2_basic.shared_spi.divider[15:0] -@28 -u2_sim_top.u2_basic.shared_spi.sclk_pad_o -@22 -u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] diff --git a/boot_cpld/.gitignore b/usrp2/boot_cpld/.gitignore index 45cf9a86b..45cf9a86b 100644 --- a/boot_cpld/.gitignore +++ b/usrp2/boot_cpld/.gitignore diff --git a/boot_cpld/_impact.cmd b/usrp2/boot_cpld/_impact.cmd index 4af86cb02..4af86cb02 100755 --- a/boot_cpld/_impact.cmd +++ b/usrp2/boot_cpld/_impact.cmd diff --git a/boot_cpld/boot_cpld.ipf b/usrp2/boot_cpld/boot_cpld.ipf Binary files differindex 8acb6821e..8acb6821e 100755 --- a/boot_cpld/boot_cpld.ipf +++ b/usrp2/boot_cpld/boot_cpld.ipf diff --git a/boot_cpld/boot_cpld.ise b/usrp2/boot_cpld/boot_cpld.ise Binary files differindex 7252d3768..7252d3768 100755 --- a/boot_cpld/boot_cpld.ise +++ b/usrp2/boot_cpld/boot_cpld.ise diff --git a/boot_cpld/boot_cpld.lfp b/usrp2/boot_cpld/boot_cpld.lfp index 0f0c8f2e2..0f0c8f2e2 100755 --- a/boot_cpld/boot_cpld.lfp +++ b/usrp2/boot_cpld/boot_cpld.lfp diff --git a/boot_cpld/boot_cpld.ucf b/usrp2/boot_cpld/boot_cpld.ucf index 789bb1d96..789bb1d96 100755 --- a/boot_cpld/boot_cpld.ucf +++ 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a/control_lib/bootrom.mem +++ b/usrp2/control_lib/bootrom.mem diff --git a/control_lib/clock_bootstrap_rom.v b/usrp2/control_lib/clock_bootstrap_rom.v index 46563db65..46563db65 100644 --- a/control_lib/clock_bootstrap_rom.v +++ b/usrp2/control_lib/clock_bootstrap_rom.v diff --git a/control_lib/clock_control.v b/usrp2/control_lib/clock_control.v index 1bbe6bd75..1bbe6bd75 100644 --- a/control_lib/clock_control.v +++ b/usrp2/control_lib/clock_control.v diff --git a/control_lib/clock_control_tb.v b/usrp2/control_lib/clock_control_tb.v index 4e705cf23..4e705cf23 100644 --- a/control_lib/clock_control_tb.v +++ b/usrp2/control_lib/clock_control_tb.v diff --git a/control_lib/cmdfile b/usrp2/control_lib/cmdfile index cb3756cfc..cb3756cfc 100644 --- a/control_lib/cmdfile +++ b/usrp2/control_lib/cmdfile diff --git a/control_lib/dcache.v b/usrp2/control_lib/dcache.v index 9063bf02a..9063bf02a 100644 --- a/control_lib/dcache.v +++ b/usrp2/control_lib/dcache.v diff --git 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