diff options
| -rwxr-xr-x | host/lib/ic_reg_maps/gen_ad9862_regs.py | 2 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e/codec_ctrl.cpp | 13 | 
2 files changed, 12 insertions, 3 deletions
| diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index 4444c6240..00340224c 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -123,7 +123,7 @@ ftw_23_16              23[0:7]            0  ########################################################################  ## DLL  ######################################################################## -input_clk_ctrl         24[6]              0       external, internal +input_clk_ctrl         24[6]              0       internal, external  adc_div2               24[5]              0       normal, div2  dll_mult               24[3:4]            0       1, 2, 4  dll_pd                 24[2]              0 diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 3f3523ddf..ce05ac9eb 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -82,7 +82,7 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){      //setup tx side of codec      _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; -    _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_SINGLE; //FIXME should be interleaved +    _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED;      _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control      _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS;      _ad9862_regs.interp = ad9862_regs_t::INTERP_4; @@ -92,10 +92,19 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){      _ad9862_regs.dac_a_coarse_gain = 0x3;      _ad9862_regs.dac_b_coarse_gain = 0x3; +    //setup the dll +    _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; +    _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; +    _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; +      //write the register settings to the codec -    for (uint8_t addr = 0; addr <= 50; addr++){ +    for (uint8_t addr = 0; addr <= 25; addr++){          this->send_reg(addr);      } + +    //aux adc clock +    _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; +    this->send_reg(34);  }  codec_ctrl_impl::~codec_ctrl_impl(void){ | 
