diff options
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 6 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_control.v | 11 |
2 files changed, 10 insertions, 7 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 21e826f1c..264b6e98a 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -31,7 +31,7 @@ module vita_tx_chain wire clear_seqnum; wire [31:0] current_seqnum; - assign underrun = error & ~(error_code == 1); + assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+1)) sr @@ -56,7 +56,7 @@ module vita_tx_chain vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.error(error),.error_code(error_code), + .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); @@ -84,7 +84,7 @@ module vita_tx_chain gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error & (REPORT_ERROR==1)), .sent(), + .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), .seqnum0(current_seqnum), .seqnum1(32'd0), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index ddcb6a2d2..20ad6b995 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,7 +6,7 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output error, + output error, output ack, output reg [31:0] error_code, output reg packet_consumed, @@ -65,13 +65,14 @@ module vita_tx_control wire policy_wait = error_policy[0]; wire policy_next_packet = error_policy[1]; wire policy_next_burst = error_policy[2]; - reg send_error; + reg send_error, send_ack; always @(posedge clk) if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; + send_ack <= 0; error_code <= 0; end else @@ -106,7 +107,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR_DONE; // Not really an error error_code <= CODE_EOB_ACK; - send_error <= 1; + send_ack <= 1; end else ibs_state <= IBS_CONT_BURST; @@ -146,6 +147,7 @@ module vita_tx_control IBS_ERROR_DONE : begin send_error <= 0; + send_ack <= 0; ibs_state <= IBS_IDLE; end @@ -156,6 +158,7 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); assign error = send_error; + assign ack = send_ack; always @(posedge clk) if(reset | clear) @@ -163,7 +166,7 @@ module vita_tx_control else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, + assign debug = { { now,early,late,ack,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; |